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ChibiOS
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G4 configurations update. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13323 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-02-08 08:25:37 +00:00
parent ef9ec13cfe
commit 1569c6580d
4 changed files with 9 additions and 25 deletions
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4
demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h
View File

@ -40,7 +40,9 @@
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (STM32_PLS_LEV0 | STM32_PVDE_DISABLED)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE

22
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
View File

@ -132,28 +132,6 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_USE_ADC4 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC345_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
/*
* CAN driver system settings.

4
testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h
View File

@ -42,7 +42,9 @@
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (STM32_PLS_LEV0 | STM32_PVDE_DISABLED)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE

4
tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl
View File

@ -51,7 +51,9 @@
*/
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(STM32_PLS_LEV0 | STM32_PVDE_DISABLED)"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"TRUE"}
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}