mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4339 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
b6cf9884d1
commit
175612822f
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@ -19,7 +19,7 @@
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*/
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/**
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* @file STM32/uart_lld.c
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* @file STM32/USARTv1/uart_lld.c
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* @brief STM32 low level UART driver code.
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*
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* @addtogroup UART
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@ -288,12 +288,15 @@ static void serve_usart_irq(UARTDriver *uartp) {
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/*===========================================================================*/
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#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
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#if !defined(STM32_USART1_HANDLER)
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#error "STM32_USART1_HANDLER not defined"
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#endif
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/**
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* @brief USART1 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART1_IRQHandler) {
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CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
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CH_IRQ_PROLOGUE();
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@ -304,12 +307,15 @@ CH_IRQ_HANDLER(USART1_IRQHandler) {
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#endif /* STM32_UART_USE_USART1 */
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#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
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#if !defined(STM32_USART2_HANDLER)
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#error "STM32_USART2_HANDLER not defined"
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#endif
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/**
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* @brief USART2 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART2_IRQHandler) {
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CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
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CH_IRQ_PROLOGUE();
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@ -320,12 +326,15 @@ CH_IRQ_HANDLER(USART2_IRQHandler) {
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#endif /* STM32_UART_USE_USART2 */
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#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
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#if !defined(STM32_USART3_HANDLER)
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#error "STM32_USART3_HANDLER not defined"
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#endif
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/**
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* @brief USART3 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART3_IRQHandler) {
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CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
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CH_IRQ_PROLOGUE();
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@ -394,7 +403,7 @@ void uart_lld_start(UARTDriver *uartp) {
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
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rccEnableUSART1(FALSE);
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nvicEnableVector(USART1_IRQn,
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nvicEnableVector(STM32_USART1_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
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@ -415,7 +424,7 @@ void uart_lld_start(UARTDriver *uartp) {
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
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rccEnableUSART2(FALSE);
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nvicEnableVector(USART2_IRQn,
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nvicEnableVector(STM32_USART2_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
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@ -436,7 +445,7 @@ void uart_lld_start(UARTDriver *uartp) {
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
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rccEnableUSART3(FALSE);
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nvicEnableVector(USART3_IRQn,
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nvicEnableVector(STM32_USART3_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
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@ -473,7 +482,7 @@ void uart_lld_stop(UARTDriver *uartp) {
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#if STM32_UART_USE_USART1
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if (&UARTD1 == uartp) {
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nvicDisableVector(USART1_IRQn);
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nvicDisableVector(STM32_USART1_NUMBER);
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rccDisableUSART1(FALSE);
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return;
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}
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@ -481,7 +490,7 @@ void uart_lld_stop(UARTDriver *uartp) {
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#if STM32_UART_USE_USART2
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if (&UARTD2 == uartp) {
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nvicDisableVector(USART2_IRQn);
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nvicDisableVector(STM32_USART2_NUMBER);
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rccDisableUSART2(FALSE);
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return;
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}
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@ -489,7 +498,7 @@ void uart_lld_stop(UARTDriver *uartp) {
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#if STM32_UART_USE_USART3
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if (&UARTD3 == uartp) {
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nvicDisableVector(USART3_IRQn);
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nvicDisableVector(STM32_USART3_NUMBER);
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rccDisableUSART3(FALSE);
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return;
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}
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@ -49,7 +49,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
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#define STM32_UART_USE_USART1 TRUE
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#define STM32_UART_USE_USART1 FALSE
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#endif
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/**
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_USART2 FALSE
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#endif
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/**
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
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#define STM32_UART_USE_USART3 TRUE
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#define STM32_UART_USE_USART3 FALSE
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#endif
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/**
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@ -19,7 +19,7 @@
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*/
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/**
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* @file STM32/uart_lld.c
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* @file STM32/USARTv2/uart_lld.c
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* @brief STM32 low level UART driver code.
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*
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* @addtogroup UART
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/*===========================================================================*/
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#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
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#if !defined(STM32_USART1_HANDLER)
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#error "STM32_USART1_HANDLER not defined"
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#endif
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/**
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* @brief USART1 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART1_IRQHandler) {
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CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
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CH_IRQ_PROLOGUE();
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#endif /* STM32_UART_USE_USART1 */
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#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
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#if !defined(STM32_USART2_HANDLER)
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#error "STM32_USART2_HANDLER not defined"
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#endif
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/**
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* @brief USART2 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART2_IRQHandler) {
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CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
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CH_IRQ_PROLOGUE();
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#endif /* STM32_UART_USE_USART2 */
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#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
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#if !defined(STM32_USART3_HANDLER)
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#error "STM32_USART3_HANDLER not defined"
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#endif
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/**
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* @brief USART3 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART3_IRQHandler) {
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CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
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CH_IRQ_PROLOGUE();
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
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rccEnableUSART1(FALSE);
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nvicEnableVector(USART1_IRQn,
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nvicEnableVector(STM32_USART1_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
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rccEnableUSART2(FALSE);
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nvicEnableVector(USART2_IRQn,
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nvicEnableVector(STM32_USART2_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
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rccEnableUSART3(FALSE);
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nvicEnableVector(USART3_IRQn,
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nvicEnableVector(STM32_USART3_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
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#if STM32_UART_USE_USART1
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if (&UARTD1 == uartp) {
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nvicDisableVector(USART1_IRQn);
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nvicDisableVector(STM32_USART1_NUMBER);
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rccDisableUSART1(FALSE);
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return;
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}
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#if STM32_UART_USE_USART2
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if (&UARTD2 == uartp) {
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nvicDisableVector(USART2_IRQn);
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nvicDisableVector(STM32_USART2_NUMBER);
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rccDisableUSART2(FALSE);
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return;
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}
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#if STM32_UART_USE_USART3
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if (&UARTD3 == uartp) {
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nvicDisableVector(USART3_IRQn);
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nvicDisableVector(STM32_USART3_NUMBER);
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rccDisableUSART3(FALSE);
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return;
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}
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@ -49,6 +49,15 @@
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#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
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#define STM32_TIM2_NUMBER TIM2_IRQn
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#define STM32_TIM3_NUMBER TIM3_IRQn
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/*
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* USART units.
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*/
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#define STM32_USART1_HANDLER USART1_IRQHandler
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#define STM32_USART2_HANDLER USART2_IRQHandler
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#define STM32_USART1_NUMBER USART1_IRQn
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#define STM32_USART2_NUMBER USART2_IRQn
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/** @} */
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/*===========================================================================*/
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@ -100,6 +100,21 @@
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#define STM32_TIM8_UP_NUMBER TIM8_UP_IRQn
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#endif
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#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
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/*
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* USART units.
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*/
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#define STM32_USART1_HANDLER USART1_IRQHandler
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#define STM32_USART2_HANDLER USART2_IRQHandler
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#define STM32_USART3_HANDLER USART3_IRQHandler
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#define STM32_UART4_HANDLER UART4_IRQHandler
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#define STM32_UART5_HANDLER UART5_IRQHandler
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#define STM32_USART1_NUMBER USART1_IRQn
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#define STM32_USART2_NUMBER USART2_IRQn
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#define STM32_USART3_NUMBER USART3_IRQn
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#define STM32_UART4_NUMBER UART4_IRQn
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#define STM32_UART5_NUMBER UART5_IRQn
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/** @} */
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/*===========================================================================*/
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@ -12,7 +12,6 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
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@ -78,6 +78,23 @@
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#define STM32_TIM5_NUMBER TIM5_IRQn
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#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
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#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
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/*
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* USART units.
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*/
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#define STM32_USART1_HANDLER USART1_IRQHandler
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#define STM32_USART2_HANDLER USART2_IRQHandler
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#define STM32_USART3_HANDLER USART3_IRQHandler
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#define STM32_UART4_HANDLER UART4_IRQHandler
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#define STM32_UART5_HANDLER UART5_IRQHandler
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#define STM32_USART6_HANDLER USART6_IRQHandler
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#define STM32_USART1_NUMBER USART1_IRQn
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#define STM32_USART2_NUMBER USART2_IRQn
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#define STM32_USART3_NUMBER USART3_IRQn
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#define STM32_UART4_NUMBER UART4_IRQn
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#define STM32_UART5_NUMBER UART5_IRQn
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#define STM32_USART6_NUMBER USART6_IRQn
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/** @} */
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/*===========================================================================*/
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@ -12,7 +12,6 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
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|
|
@ -78,6 +78,23 @@
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#define STM32_TIM5_NUMBER TIM5_IRQn
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#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
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#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
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/*
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* USART units.
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*/
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#define STM32_USART1_HANDLER USART1_IRQHandler
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#define STM32_USART2_HANDLER USART2_IRQHandler
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#define STM32_USART3_HANDLER USART3_IRQHandler
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#define STM32_UART4_HANDLER UART4_IRQHandler
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#define STM32_UART5_HANDLER UART5_IRQHandler
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#define STM32_USART6_HANDLER USART6_IRQHandler
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#define STM32_USART1_NUMBER USART1_IRQn
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#define STM32_USART2_NUMBER USART2_IRQn
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#define STM32_USART3_NUMBER USART3_IRQn
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#define STM32_UART4_NUMBER UART4_IRQn
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#define STM32_UART5_NUMBER UART5_IRQn
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#define STM32_USART6_NUMBER USART6_IRQn
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/** @} */
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/*===========================================================================*/
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|
|
|
@ -5,12 +5,10 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32L1xx/ext_lld_isr.c \
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${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
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|
|
|
@ -47,6 +47,17 @@
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#define STM32_TIM2_NUMBER TIM2_IRQn
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#define STM32_TIM3_NUMBER TIM3_IRQn
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#define STM32_TIM4_NUMBER TIM4_IRQn
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/*
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* USART units.
|
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*/
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#define STM32_USART1_HANDLER USART1_IRQHandler
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#define STM32_USART2_HANDLER USART2_IRQHandler
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#define STM32_USART3_HANDLER USART3_IRQHandler
|
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|
||||
#define STM32_USART1_NUMBER USART1_IRQn
|
||||
#define STM32_USART2_NUMBER USART2_IRQn
|
||||
#define STM32_USART3_NUMBER USART3_IRQn
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
|
@ -193,9 +193,9 @@
|
|||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART1 TRUE
|
||||
#define STM32_UART_USE_USART2 TRUE
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#define STM32_UART_USE_USART3 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
|
Loading…
Reference in New Issue