mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5179 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
6a21d25cb5
commit
18078ccb46
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@ -118,8 +118,28 @@ void spc_early_init(void) {
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invalid accesses to peripherals.*/
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invalid accesses to peripherals.*/
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SSCM.ERROR.R = 3; /* PAE and RAE bits. */
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SSCM.ERROR.R = 3; /* PAE and RAE bits. */
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/* FCCU CF errors clearing.*/
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FCCU.CFK.R = 0x618B7A50;
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FCCU.CFS[0].R = 0xFFFFFFFF;
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while (FCCU.CTRL.B.OPS != 3)
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;
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FCCU.CFK.R = 0x618B7A50;
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FCCU.CFS[1].R = 0xFFFFFFFF;
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while (FCCU.CTRL.B.OPS != 3)
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;
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/* FCCU NCF errors clearing.*/
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FCCU.NCFK.R = 0xAB3498FE;
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FCCU.NCFS[0].R = 0xFFFFFFFF;
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while (FCCU.CTRL.B.OPS != 3)
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;
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/* RGM errors clearing.*/
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RGM.FES.R = 0xFFFF;
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RGM.DES.R = 0xFFFF;
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/* Enabling peripheral bridges to allow any operation.*/
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/* Enabling peripheral bridges to allow any operation.*/
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AIPS.MPROT.R = 0x77777777;
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/* AIPS.MPROT.R = 0x77777777;
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AIPS.PACR0_7.R = 0;
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AIPS.PACR0_7.R = 0;
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AIPS.PACR8_15.R = 0;
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AIPS.PACR8_15.R = 0;
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AIPS.PACR16_23.R = 0;
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AIPS.PACR16_23.R = 0;
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@ -135,7 +155,7 @@ void spc_early_init(void) {
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AIPS.OPACR64_71.R = 0;
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AIPS.OPACR64_71.R = 0;
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AIPS.OPACR72_79.R = 0;
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AIPS.OPACR72_79.R = 0;
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AIPS.OPACR80_87.R = 0;
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AIPS.OPACR80_87.R = 0;
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AIPS.OPACR88_95.R = 0;
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AIPS.OPACR88_95.R = 0;*/
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/* The system must be in DRUN mode on entry, if this is not the case then
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/* The system must be in DRUN mode on entry, if this is not the case then
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it is considered a serious anomaly.*/
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it is considered a serious anomaly.*/
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@ -168,95 +168,6 @@
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.globl _coreinit
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.globl _coreinit
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.type _coreinit, @function
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.type _coreinit, @function
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_coreinit:
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_coreinit:
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* slow down the startup but there is no way around.
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*/
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.clear_ecc:
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xor %r0, %r0, %r0
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xor %r1, %r1, %r1
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xor %r2, %r2, %r2
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xor %r3, %r3, %r3
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xor %r4, %r4, %r4
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xor %r5, %r5, %r5
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xor %r6, %r6, %r6
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xor %r7, %r7, %r7
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xor %r8, %r8, %r8
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xor %r9, %r9, %r9
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xor %r10, %r10, %r10
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xor %r11, %r11, %r11
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xor %r12, %r12, %r12
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xor %r13, %r13, %r13
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xor %r14, %r14, %r14
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xor %r15, %r15, %r15
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl %cr0, %r4, %r5
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bge %cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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/*
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* Special function registers clearing, required in order to avoid
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* possible problems with lockstep mode.
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*/
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mtcrf 0xFF, %r31
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mtspr 9, %r31 /* CTR */
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mtspr 22, %r31 /* DEC */
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mtspr 26, %r31 /* SRR0-1 */
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mtspr 27, %r31
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mtspr 54, %r31 /* DECAR */
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mtspr 58, %r31 /* CSRR0-1 */
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mtspr 59, %r31
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mtspr 61, %r31 /* DEAR */
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mtspr 256, %r31 /* USPRG0 */
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mtspr 272, %r31 /* SPRG1-7 */
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mtspr 273, %r31
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mtspr 274, %r31
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mtspr 275, %r31
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mtspr 276, %r31
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mtspr 277, %r31
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mtspr 278, %r31
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mtspr 279, %r31
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mtspr 285, %r31 /* TBU */
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mtspr 284, %r31 /* TBL */
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mtspr 318, %r31 /* DVC1-2 */
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mtspr 319, %r31
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mtspr 562, %r31 /* DBCNT */
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mtspr 570, %r31 /* MCSRR0 */
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mtspr 571, %r31 /* MCSRR1 */
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mtspr 604, %r31 /* SPRG8-9 */
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mtspr 605, %r31
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/*
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* MSR initialization.
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*/
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lis %r3, MSR_DEFAULT@h
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ori %r3, %r3, MSR_DEFAULT@l
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mtMSR %r3
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/*
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/*
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* TLB0 allocated to flash.
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* TLB0 allocated to flash.
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*/
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*/
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@ -365,6 +276,114 @@ _coreinit:
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mtspr 624, %r3 /* MAS0 */
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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tlbwe
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/*
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* Enabling peripheral bridges to allow all operations from all
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* masters. Required in order to enable the following accesses to
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* peripherals.
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*/
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lis %r7, 0xFFF0
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lis %r3, 0x7777
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ori %r3, %r3, 0x7777
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stw %r3, 0(%r7) /* MPROT */
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li %r3, 0
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stw %r3, 32(%r7) /* PACR */
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stw %r3, 36(%r7)
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stw %r3, 40(%r7)
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stw %r3, 44(%r7)
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stw %r3, 64(%r7) /* OPACR */
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stw %r3, 68(%r7)
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stw %r3, 72(%r7)
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stw %r3, 76(%r7)
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stw %r3, 80(%r7)
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stw %r3, 84(%r7)
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stw %r3, 88(%r7)
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stw %r3, 92(%r7)
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stw %r3, 96(%r7)
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stw %r3, 100(%r7)
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stw %r3, 104(%r7)
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stw %r3, 108(%r7)
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* slow down the startup but there is no way around.
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*/
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xor %r0, %r0, %r0
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xor %r1, %r1, %r1
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xor %r2, %r2, %r2
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xor %r3, %r3, %r3
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xor %r4, %r4, %r4
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xor %r5, %r5, %r5
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xor %r6, %r6, %r6
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xor %r7, %r7, %r7
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xor %r8, %r8, %r8
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xor %r9, %r9, %r9
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xor %r10, %r10, %r10
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xor %r11, %r11, %r11
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xor %r12, %r12, %r12
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xor %r13, %r13, %r13
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xor %r14, %r14, %r14
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xor %r15, %r15, %r15
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl %cr0, %r4, %r5
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bge %cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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/*
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* Special function registers clearing, required in order to avoid
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* possible problems with lockstep mode.
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*/
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mtcrf 0xFF, %r31
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mtspr 9, %r31 /* CTR */
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mtspr 22, %r31 /* DEC */
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mtspr 26, %r31 /* SRR0-1 */
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mtspr 27, %r31
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mtspr 54, %r31 /* DECAR */
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mtspr 58, %r31 /* CSRR0-1 */
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mtspr 59, %r31
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mtspr 61, %r31 /* DEAR */
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mtspr 256, %r31 /* USPRG0 */
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mtspr 272, %r31 /* SPRG1-7 */
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mtspr 273, %r31
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mtspr 274, %r31
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mtspr 275, %r31
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mtspr 276, %r31
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mtspr 277, %r31
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mtspr 278, %r31
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mtspr 279, %r31
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mtspr 285, %r31 /* TBU */
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mtspr 284, %r31 /* TBL */
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mtspr 318, %r31 /* DVC1-2 */
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mtspr 319, %r31
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mtspr 562, %r31 /* DBCNT */
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mtspr 570, %r31 /* MCSRR0 */
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mtspr 571, %r31 /* MCSRR1 */
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mtspr 604, %r31 /* SPRG8-9 */
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mtspr 605, %r31
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/*
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/*
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* Cache enabled.
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* Cache enabled.
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*/
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*/
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