From 2129acb4366ba5868c9d4bf72414bdebd93ffaab Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 30 Jun 2019 13:06:37 +0000 Subject: [PATCH] Fixed F4 PLLI2S/SAI naming. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12863 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h | 5 ++--- os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h | 3 ++- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h index 84718185b..eead7483b 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h @@ -538,9 +538,8 @@ #define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */ #define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */ -#define STM32_CK48MSEL_PLLALT (1 << 27) /**< PLL48CLK source is PLLSAI - or PLLI2S depending on - device. */ +#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */ +#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */ #define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */ #define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */ diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h index 7c81be26e..818114aa3 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h @@ -317,7 +317,7 @@ * @name RCC_DCKCFGR2 register bits definitions * @{ */ -#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2CFMP1SEL mask. */ +#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2CFMP1SEL mask. */ #define STM32_I2CFMP1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */ #define STM32_I2CFMP1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */ #define STM32_I2CFMP1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */ @@ -325,6 +325,7 @@ #define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */ #define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */ #define STM32_CK48MSEL_PLLI2S (1 << 27) /**< PLL48CLK source is PLLI2S. */ +#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */ #define STM32_SDIOSEL_MASK (1 << 28) /**< SDIOSEL mask. */ #define STM32_SDIOSEL_PLL48CLK (0 << 28) /**< SDIO source is PLL48CLK. */