mirror of https://github.com/rusefi/ChibiOS.git
FPU support for CM4 (not working yet).
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3591 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
ea9053eb9e
commit
26dc203d65
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@ -5,7 +5,7 @@
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# Compiler options here.
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ifeq ($(USE_OPT),)
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USE_OPT = -O2 -ggdb -fomit-frame-pointer
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USE_OPT = -O2 -ggdb -fomit-frame-pointer -mhard-float
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endif
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# C specific options here (added to USE_OPT).
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@ -120,7 +120,7 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
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# Compiler settings
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#
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MCU = cortex-m3
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MCU = cortex-m4
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#TRGT = arm-elf-
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TRGT = arm-none-eabi-
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@ -31,18 +31,36 @@
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/**
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* @brief Internal context stacking.
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*/
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#if CORTEX_USE_FPU || defined(__DOXYGEN__)
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#define PUSH_CONTEXT() { \
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asm volatile ("vpush {s16-s31}" \
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: : : "memory"); \
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asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" \
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: : : "memory"); \
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}
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#else /* !CORTEX_USE_FPU */
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#define PUSH_CONTEXT() { \
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asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" \
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: : : "memory"); \
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}
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#endif /* !CORTEX_USE_FPU */
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/**
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* @brief Internal context unstacking.
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*/
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#if CORTEX_USE_FPU || defined(__DOXYGEN__)
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#define POP_CONTEXT() { \
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asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
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: : : "memory"); \
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asm volatile ("vpop {s16-s31}" \
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: : : "memory"); \
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}
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#else /* !CORTEX_USE_FPU */
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#define POP_CONTEXT() { \
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asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
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: : : "memory"); \
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}
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#endif /* !CORTEX_USE_FPU */
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#if !CH_OPTIMIZE_SPEED
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void _port_lock(void) {
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@ -80,12 +98,21 @@ CH_IRQ_HANDLER(SysTickVector) {
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* @note The PendSV vector is only used in advanced kernel mode.
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*/
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void SVCallVector(void) {
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uint32_t *psp;
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register struct extctx *ctxp;
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/* Current PSP value.*/
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asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory");
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#if CORTEX_USE_FPU
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/* Restoring the special registers SCB_FPCCR and FPCAR.*/
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SCB_FPCAR = *psp++;
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SCB_FPCCR = *psp++;
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#endif
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/* Discarding the current exception context and positioning the stack to
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point to the real one.*/
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asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
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ctxp++;
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ctxp = (struct extctx *)psp + 1;
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
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port_unlock_from_isr();
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}
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@ -99,16 +126,61 @@ void SVCallVector(void) {
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* @note The PendSV vector is only used in compact kernel mode.
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*/
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void PendSVVector(void) {
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uint32_t *psp;
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register struct extctx *ctxp;
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/* Current PSP value.*/
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asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory");
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#if CORTEX_USE_FPU
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/* Restoring the special registers SCB_FPCCR and FPCAR.*/
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SCB_FPCAR = *psp++;
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SCB_FPCCR = *psp++;
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#endif
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/* Discarding the current exception context and positioning the stack to
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point to the real one.*/
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asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
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ctxp++;
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ctxp = (struct extctx *)psp + 1;
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
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}
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#endif /* CORTEX_SIMPLIFIED_PRIORITY */
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/**
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* @brief Port-related initialization code.
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*/
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void _port_init(void) {
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uint32_t reg;
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/* Initialization of the vector table and priority related settings.*/
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SCB_VTOR = CORTEX_VTOR_INIT;
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SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);
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#if CORTEX_USE_FPU
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/* CP10 and CP11 set to full access.*/
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SCB_CPACR |= 0x00F00000;
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/* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
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asm volatile ("mrs %0, CONTROL" : "=r" (reg) : : "memory");
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reg |= 4;
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asm volatile ("msr CONTROL, %0" : : "r" (reg) : "memory");
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/* FPSCR and FPDSCR initially zero.*/
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reg = 0;
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asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory");
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SCB_FPDSCR = reg;
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/* Initializing the FPU context save in lazy mode.*/
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SCB_FPCCR = FPCCR_LSPEN;
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#endif
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/* Initialization of the system vectors used by the port.*/
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NVICSetSystemHandlerPriority(HANDLER_SVCALL,
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
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NVICSetSystemHandlerPriority(HANDLER_PENDSV,
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK,
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
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}
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/**
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* @brief Exception exit redirection to _port_switch_from_isr().
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*/
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@ -116,12 +188,29 @@ void _port_irq_epilogue(void) {
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port_lock_from_isr();
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if ((SCB_ICSR & ICSR_RETTOBASE)) {
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register struct extctx *ctxp;
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uint32_t *psp;
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struct extctx *ctxp;
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/* Current PSP value.*/
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asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory");
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#if CORTEX_USE_FPU
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{
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uint32_t fpccr;
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/* Saving the special registers SCB_FPCCR and FPCAR as extra context.*/
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*--psp = fpccr = SCB_FPCCR;
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*--psp = SCB_FPCAR;
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/* Now the FPCCR is modified in order to not restore the FPU status
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from the artificial return context.*/
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SCB_FPCCR = fpccr | FPCCR_LSPACT;
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}
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#endif
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/* Adding an artificial exception return context, there is no need to
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populate it fully.*/
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asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
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ctxp--;
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ctxp = (struct extctx *)psp - 1;
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
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ctxp->pc = _port_switch_from_isr;
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ctxp->xpsr = (regarm_t)0x01000000;
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@ -129,8 +129,12 @@
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#elif (CORTEX_MODEL == CORTEX_M4)
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#define CH_ARCHITECTURE_ARM_v7ME
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#define CH_ARCHITECTURE_NAME "ARMv7-ME"
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#if CORTEX_USE_FPU
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#define CH_CORE_VARIANT_NAME "Cortex-M4F"
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#else
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#define CH_CORE_VARIANT_NAME "Cortex-M4"
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#endif
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#endif
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/**
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* @brief Port-specific information string.
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@ -162,6 +166,27 @@ struct extctx {
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regarm_t lr_thd;
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regarm_t pc;
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regarm_t xpsr;
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#if CORTEX_USE_FPU || defined(__DOXYGEN__)
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regarm_t s0;
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regarm_t s1;
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regarm_t s2;
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regarm_t s3;
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regarm_t s4;
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regarm_t s5;
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regarm_t s6;
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regarm_t s7;
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regarm_t s8;
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regarm_t s9;
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regarm_t s10;
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regarm_t s11;
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regarm_t s12;
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regarm_t s13;
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regarm_t s14;
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regarm_t s15;
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regarm_t s16;
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regarm_t fpscr;
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regarm_t reserved;
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#endif /* CORTEX_USE_FPU */
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};
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struct intctx {
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@ -174,6 +199,24 @@ struct intctx {
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regarm_t r10;
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regarm_t r11;
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regarm_t lr;
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#if CORTEX_USE_FPU || defined(__DOXYGEN__)
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regarm_t s16;
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regarm_t s17;
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regarm_t s18;
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regarm_t s19;
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regarm_t s20;
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regarm_t s21;
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regarm_t s22;
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regarm_t s23;
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regarm_t s24;
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regarm_t s25;
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regarm_t s26;
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regarm_t s27;
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regarm_t s28;
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regarm_t s29;
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regarm_t s30;
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regarm_t s31;
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#endif /* CORTEX_USE_FPU */
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};
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#endif
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@ -208,16 +251,7 @@ struct intctx {
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/**
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* @brief Port-related initialization code.
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*/
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#define port_init() { \
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SCB_VTOR = CORTEX_VTOR_INIT; \
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SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
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NVICSetSystemHandlerPriority(HANDLER_SVCALL, \
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
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NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
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}
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#define port_init() _port_init()
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/**
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* @brief Kernel-lock action.
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@ -357,6 +391,7 @@ struct intctx {
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extern "C" {
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#endif
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void port_halt(void);
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void _port_init(void);
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void _port_switch(Thread *ntp, Thread *otp);
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void _port_irq_epilogue(void);
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void _port_switch_from_isr(void);
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@ -53,11 +53,6 @@ typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
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*/
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#define NVIC_ITCR (*((IOREG32 *)0xE000E004))
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/**
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* @brief NVIC STIR register.
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*/
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#define NVIC_STIR (*((IOREG32 *)0xE000EF00))
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/**
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* @brief Structure representing the SYSTICK I/O space.
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*/
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@ -66,12 +61,12 @@ typedef struct {
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IOREG32 RVR;
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IOREG32 CVR;
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IOREG32 CBVR;
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} CM3_ST;
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} CMx_ST;
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/**
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* @brief SYSTICK peripheral base address.
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*/
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#define STBase ((CM3_ST *)0xE000E010)
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#define STBase ((CMx_ST *)0xE000E010)
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#define ST_CSR (STBase->CSR)
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#define ST_RVR (STBase->RVR)
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#define ST_CVR (STBase->CVR)
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@ -111,18 +106,21 @@ typedef struct {
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IOREG32 IABR[8];
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IOREG32 unused5[56];
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IOREG32 IPR[60];
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} CM3_NVIC;
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IOREG32 unused6[644];
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IOREG32 STIR;
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} CMx_NVIC;
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/**
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* @brief NVIC peripheral base address.
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*/
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#define NVICBase ((CM3_NVIC *)0xE000E100)
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#define NVICBase ((CMx_NVIC *)0xE000E100)
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#define NVIC_ISER(n) (NVICBase->ISER[n])
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#define NVIC_ICER(n) (NVICBase->ICER[n])
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#define NVIC_ISPR(n) (NVICBase->ISPR[n])
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#define NVIC_ICPR(n) (NVICBase->ICPR[n])
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#define NVIC_IABR(n) (NVICBase->IABR[n])
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#define NVIC_IPR(n) (NVICBase->IPR[n])
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#define NVIC_STIR (NVICBase->STIR)
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/**
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* @brief Structure representing the System Control Block I/O space.
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@ -142,12 +140,19 @@ typedef struct {
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IOREG32 MMFAR;
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IOREG32 BFAR;
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IOREG32 AFSR;
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} CM3_SCB;
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IOREG32 PFR[2];
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IOREG32 DFR;
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IOREG32 ADR;
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IOREG32 MMFR[4];
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IOREG32 SAR[5];
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IOREG32 unused1[5];
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IOREG32 CPACR;
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} CMx_SCB;
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/**
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* @brief SCB peripheral base address.
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*/
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#define SCBBase ((CM3_SCB *)0xE000ED00)
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#define SCBBase ((CMx_SCB *)0xE000ED00)
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#define SCB_CPUID (SCBBase->CPUID)
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#define SCB_ICSR (SCBBase->ICSR)
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#define SCB_VTOR (SCBBase->VTOR)
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@ -162,6 +167,12 @@ typedef struct {
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#define SCB_MMFAR (SCBBase->MMFAR)
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#define SCB_BFAR (SCBBase->BFAR)
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#define SCB_AFSR (SCBBase->AFSR)
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#define SCB_PFR(n) (SCBBase->PFR[n])
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#define SCB_DFR (SCBBase->DFR)
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#define SCB_ADR (SCBBase->ADR)
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#define SCB_MMFR(n) (SCBBase->MMFR[n])
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#define SCB_SAR(n) (SCBBase->SAR[n])
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#define SCB_CPACR (SCBBase->CPACR)
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#define ICSR_VECTACTIVE_MASK (0x1FF << 0)
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#define ICSR_RETTOBASE (0x1 << 11)
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@ -172,12 +183,46 @@ typedef struct {
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#define ICSR_PENDSTSET (0x1 << 26)
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#define ICSR_PENDSVCLR (0x1 << 27)
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#define ICSR_PENDSVSET (0x1 << 28)
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#define ICSR_NMIPENDSET (0x1 << 31)
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#define ICSR_NMIPENDSET (0x1U << 31)
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#define AIRCR_VECTKEY 0x05FA0000
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#define AIRCR_PRIGROUP_MASK (0x7 << 8)
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#define AIRCR_PRIGROUP(n) ((n) << 8)
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typedef struct {
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IOREG32 unused1[1];
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IOREG32 FPCCR;
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IOREG32 FPCAR;
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IOREG32 FPDSCR;
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IOREG32 MVFR0;
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IOREG32 MVFR1;
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} CMx_FPU;
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/**
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* @brief FPU peripheral base address.
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*/
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#define FPUBase ((CMx_FPU *)0xE000EF30L)
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#define SCB_FPCCR (FPUBase->FPCCR)
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#define SCB_FPCAR (FPUBase->FPCAR)
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#define SCB_FPDSCR (FPUBase->FPDSCR)
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#define SCB_MVFR0 (FPUBase->MVFR0)
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#define SCB_MVFR1 (FPUBase->MVFR1)
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#define FPCCR_ASPEN (0x1U << 31)
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#define FPCCR_LSPEN (0x1U << 30)
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#define FPCCR_MONRDY (0x1U << 8)
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#define FPCCR_BFRDY (0x1U << 6)
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#define FPCCR_MMRDY (0x1U << 5)
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#define FPCCR_HFRDY (0x1U << 4)
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#define FPCCR_THREAD (0x1U << 3)
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#define FPCCR_USER (0x1U << 1)
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#define FPCCR_LSPACT (0x1U << 0)
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#define FPDSCR_AHP (0x1U << 26)
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#define FPDSCR_DN (0x1U << 25)
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#define FPDSCR_FZ (0x1U << 24)
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#define FPDSCR_RMODE(n) ((n) << 22)
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#ifdef __cplusplus
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extern "C" {
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#endif
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