ADCv1 changes for STM32G0xx, not finished.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13340 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c

@@ -33,6 +33,13 @@
 #define ADC1_DMA_CHANNEL                                                    \
   STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
 
+/* Headers differences patches.*/
+#if defined(ADC_IER_AWDIE)
+#define ADC_IER_AWD1IE      ADC_IER_AWDIE
+#define ADC_ISR_AWD1        ADC_ISR_AWD
+#define TR1                 TR
+#endif
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -185,9 +192,14 @@ void adc_lld_start(ADCDriver *adcp) {
                                      (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
                                      (void *)adcp);
       osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
       rccEnableADC1(true);
 
+      /* DMA setup.*/
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+#if STM32_DMA_SUPPORTS_DMAMUX
+      dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC1);
+#endif
+
       /* Clock settings.*/
       adcp->adc->CFGR2 = STM32_ADC_ADC1_CKMODE;
     }
@@ -270,8 +282,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   /* ADC setup, if it is defined a callback for the analog watch dog then it
      is enabled.*/
   adcp->adc->ISR    = adcp->adc->ISR;
-  adcp->adc->IER    = ADC_IER_OVRIE | ADC_IER_AWDIE;
+  adcp->adc->IER    = ADC_IER_OVRIE | ADC_IER_AWD1IE;
-  adcp->adc->TR     = grpp->tr;
+  adcp->adc->TR1    = grpp->tr;
   adcp->adc->SMPR   = grpp->smpr;
   adcp->adc->CHSELR = grpp->chselr;
 
@@ -325,7 +337,7 @@ void adc_lld_serve_interrupt(ADCDriver *adcp) {
          to read data fast enough.*/
       _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
     }
-    if (isr & ADC_ISR_AWD) {
+    if (isr & ADC_ISR_AWD1) {
       /* Analog watchdog error.*/
       _adc_isr_error_code(adcp, ADC_ERR_AWD);
     }

os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h

@@ -44,7 +44,7 @@
 #define ADC_SMPR_SMP_55P5       5U  /**< @brief 68 cycles conversion time.  */
 #define ADC_SMPR_SMP_71P5       6U  /**< @brief 84 cycles conversion time.  */
 #define ADC_SMPR_SMP_239P5      7U  /**< @brief 252 cycles conversion time. */
-#elif defined(STM32L0XX)
+#elif defined(STM32L0XX) || defined(STM32G0XX)
 #define ADC_SMPR_SMP_1P5        0U  /**< @brief 14 cycles conversion time   */
 #define ADC_SMPR_SMP_3P5        1U  /**< @brief 16 cycles conversion time.  */
 #define ADC_SMPR_SMP_7P5        2U  /**< @brief 20 cycles conversion time.  */
@@ -171,29 +171,80 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
+/* Supported devices checks.*/
+#if !defined(STM32F0XX) && !defined(STM32L0XX) && !defined(STM32G0XX)
+#error "ADCv1 only supports F0, L0 and G0 STM32 devices"
+#endif
+
+#if defined(STM32L0XX) || defined(STM32G0XX) ||                             \
+    defined(__DOXYGEN__)
+#define STM32_ADCV1_OVERSAMPLING            TRUE
+#else
+#define STM32_ADCV1_OVERSAMPLING            FALSE
+#endif
+
+/* Registry checks.*/
+#if !defined(STM32_HAS_ADC1)
+#error "STM32_HAS_ADC1 not defined in registry"
+#endif
+
+#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_HANDLER))
+#error "STM32_ADC1_HANDLER not defined in registry"
+#endif
+
+#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_NUMBER))
+#error "STM32_ADC1_NUMBER not defined in registry"
+#endif
+
 #if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
 #error "ADC1 not present in the selected device"
 #endif
 
+/* Units checks.*/
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+/* At least one ADC must be assigned.*/
 #if !STM32_ADC_USE_ADC1
 #error "ADC driver activated but no ADC peripheral assigned"
 #endif
 
+/* ADC IRQ priority tests.*/
 #if STM32_ADC_USE_ADC1 &&                                                   \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to ADC1"
 #endif
 
+/* DMA IRQ priority tests.*/
 #if STM32_ADC_USE_ADC1 &&                                                   \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to ADC1 DMA"
 #endif
 
+/* DMA priority tests.*/
 #if STM32_ADC_USE_ADC1 &&                                                   \
     !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
 #error "Invalid DMA priority assigned to ADC1"
 #endif
 
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM)
+#error "ADC DMA stream not defined"
+#endif
+#if STM32_DMA_SUPPORTS_DMAMUX
+
+#else /* !STM32_DMA_SUPPORTS_DMAMUX */
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
+#error "invalid DMA stream associated to ADC1"
+#endif
+
+#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
+
+/* ADC clock source checks.*/
 #if STM32_ADC_SUPPORTS_PRESCALER == TRUE
 #if STM32_ADC_PRESCALER_VALUE == 1
 #define STM32_ADC_PRESC                     0U
@@ -224,17 +275,6 @@
 #endif
 #endif
 
-/* Check on the presence of the DMA streams settings in mcuconf.h.*/
-#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM)
-#error "ADC DMA stream not defined"
-#endif
-
-/* Check on the validity of the assigned DMA channels.*/
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
-#error "invalid DMA stream associated to ADC1"
-#endif
-
 #if !defined(STM32_DMA_REQUIRED)
 #define STM32_DMA_REQUIRED
 #endif

os/hal/ports/STM32/STM32G0xx/platform.mk

@@ -26,7 +26,7 @@ else
 endif
 
 # Drivers compatible with the platform.
-#include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk