diff --git a/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h b/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h index dd94a9145..67a6ded57 100644 --- a/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h @@ -43,8 +43,9 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE +#define STM32_LSI1_ENABLED TRUE +#define STM32_LSI2_ENABLED FALSE +#define STM32_HSE32_ENABLED TRUE #define STM32_LSE_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M @@ -79,7 +80,7 @@ #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_RTCSEL STM32_RTCSEL_LSI diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk index 4f7178de5..93b3de78b 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk @@ -275,9 +275,9 @@ clean: CLEAN_RULE_HOOK @echo Cleaning @echo - $(DEPDIR) @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null - @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi + @-if [ -d "$(DEPDIR)" ]; then rmdir -p $(subst ./,,$(DEPDIR)) 2>/dev/null; fi @echo - $(BUILDDIR) - @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi + @-if [ -d "$(BUILDDIR)" ]; then rmdir -p $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi @echo @echo Done diff --git a/os/hal/boards/ST_NUCLEO48_WB55CG_USB/board.h b/os/hal/boards/ST_NUCLEO48_WB55CG_USB/board.h index 437a9329b..e65ea35e5 100644 --- a/os/hal/boards/ST_NUCLEO48_WB55CG_USB/board.h +++ b/os/hal/boards/ST_NUCLEO48_WB55CG_USB/board.h @@ -45,10 +45,6 @@ #define STM32_LSEDRV (3U << 3U) -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 32000000U -#endif - /* * Board voltages. * Required for performance limits calculation. diff --git a/os/hal/boards/ST_NUCLEO68_WB55RG/board.h b/os/hal/boards/ST_NUCLEO68_WB55RG/board.h index b5423bf05..4f721bc28 100644 --- a/os/hal/boards/ST_NUCLEO68_WB55RG/board.h +++ b/os/hal/boards/ST_NUCLEO68_WB55RG/board.h @@ -45,10 +45,6 @@ #define STM32_LSEDRV (3U << 3U) -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 32000000U -#endif - /* * Board voltages. * Required for performance limits calculation. diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v2.inc new file mode 100644 index 000000000..ef69cdba0 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v2.inc @@ -0,0 +1,101 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_lsi12.inc + * @brief Shared LSI12 clock handler. + * + * @addtogroup STM32_LSI12_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief LSI clock frequency. + */ +#define STM32_LSICLK 32000U + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_LSI1) +#error "STM32_RCC_HAS_LSI1 not defined in stm32_registry.h" +#endif + +#if !defined(STM32_RCC_HAS_LSI2) +#error "STM32_RCC_HAS_LSI2 not defined in stm32_registry.h" +#elif !defined(STM32_RCC_LSI2_TRIM_ADDR) +#error "STM32_RCC_LSI2_TRIM_ADDR not defined in stm32_registry.h" +#endif + +/* Checks on configurations.*/ +#if !defined(STM32_LSI1_ENABLED) +#error "STM32_LSI1_ENABLED not defined in mcuconf.h" +#endif + +#if !defined(STM32_LSI2_ENABLED) +#error "STM32_LSI2_ENABLED not defined in mcuconf.h" +#endif + +#if defined(STM32_LSI_ENABLED) +#error "STM32_LSI_ENABLED should not be defined in mcuconf.h" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void lsi_init(void) { + +#if STM32_LSI1_ENABLED + /* LSI1 activation.*/ + RCC->CSR |= RCC_CSR_LSI1ON; + while ((RCC->CSR & RCC_CSR_LSI1RDY) == 0U) { + } +#endif +#if STM32_LSI2_ENABLED + /* Set LSI2 trimming.*/ + uint32_t trim = ((*(uint32_t *)(STM32_RCC_LSI2_TRIM_ADDR)) & 0xFUL); + RCC->CSR |= (trim << RCC_CSR_LSI2TRIM_Pos); + /* LSI2 activation.*/ + RCC->CSR |= RCC_CSR_LSI2ON; + while ((RCC->CSR & RCC_CSR_LSI2RDY) == 0U) { + } +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi_v2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi_v2.inc new file mode 100644 index 000000000..5d21ce1fd --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi_v2.inc @@ -0,0 +1,198 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_msi_v2.inc + * @brief Shared MSI clock handler V2. + * + * @addtogroup STM32_MSI_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @name RCC_CR register bits definitions + * @{ + */ +#define STM32_MSIRANGE_MASK (15U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_100K (0U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_200K (1U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_400K (2U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_800K (3U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_1M (4U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_2M (5U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_4M (6U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_8M (7U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_16M (8U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_24M (9U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_32M (10U << RCC_CR_MSIRANGE_Pos) +#define STM32_MSIRANGE_48M (11U << RCC_CR_MSIRANGE_Pos) +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_MSI) +#error "STM32_RCC_HAS_MSI not defined in stm32_registry.h" +#endif + +/* Checks on configurations.*/ +#if !defined(STM32_MSIPLL_ENABLED) +#error "STM32_MSIPLL_ENABLED not defined in mcuconf.h" +#endif + +#if !defined(STM32_MSIRANGE) +#error "STM32_MSIRANGE not defined in mcuconf.h" +#endif + +#if !defined(STM32_LSE_ENABLED) +#error "STM32_LSE_ENABLED not defined in mcuconf.h" +#endif + +#if STM32_MSIPLL_ENABLED && !STM32_LSE_ENABLED +#error "STM32_MSIPLL_ENABLED requires LSE" +#endif + +/** + * @brief MSI frequency. + */ +#if STM32_MSIRANGE == STM32_MSIRANGE_100K + #define STM32_MSICLK 100000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_200K + #define STM32_MSICLK 200000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_400K + #define STM32_MSICLK 400000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_800K + #define STM32_MSICLK 800000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_1M + #define STM32_MSICLK 1000000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_2M + #define STM32_MSICLK 2000000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_4M + #define STM32_MSICLK 4000000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_8M + #define STM32_MSICLK 8000000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_16M + #define STM32_MSICLK 16000000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_24M + #define STM32_MSICLK 24000000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_32M + #define STM32_MSICLK 32000000U + +#elif STM32_MSIRANGE == STM32_MSIRANGE_48M + #define STM32_MSICLK 48000000U + +#else + #error "invalid STM32_MSIRANGE value specified" +#endif + +/* Some headers do not have this definition.*/ +#if !defined(RCC_CFGR_SWS_MSI) +#define RCC_CFGR_SWS_MSI 0U +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void msi_enable(void) { + + RCC->CR |= RCC_CR_MSION; + while ((RCC->CR & RCC_CR_MSIRDY) == 0U) { + /* Wait until MSI is stable.*/ + } +} + +__STATIC_INLINE void msi_disable(void) { + + RCC->CR &= ~RCC_CR_MSION; +} + +__STATIC_INLINE void msi_reset(void) { + + /* Resetting MSI defaults. + Note from RM0432: MSIRANGE can be modified when MSI is OFF (MSION=0) + or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when + MSI is ON and NOT ready (MSION=1 and MSIRDY=0).*/ + RCC->CR = (RCC->CR & ~RCC_CR_MSIRANGE_Msk) | RCC_CR_MSIRANGE_6; + + /* Making sure MSI is active and ready.*/ + msi_enable(); + + /* Clocking from MSI, in case MSI was not the default source.*/ + RCC->CFGR = RCC_CFGR_SW_MSI; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) { + /* Wait until MSI is selected.*/ + } +} + +__STATIC_INLINE void msi_init(void) { + uint32_t cr; + + /* Initial clocks setup and wait for MSI stabilization, the MSI clock is + always enabled because it is the fall back clock when PLL the fails. + Trim fields are not altered from reset values.*/ + + /* MSIRANGE can be set only when MSI is OFF or READY, it is ready after + reset.*/ +#if STM32_MSIPLL_ENABLED + cr = STM32_MSIRANGE | RCC_CR_MSIPLLEN | RCC_CR_MSION; +#else + cr = STM32_MSIRANGE | RCC_CR_MSION; +#endif + RCC->CR = cr; + while ((RCC->CR & RCC_CR_MSIRDY) == 0U) { + /* Wait until MSI is stable.*/ + } + + /* Clocking from MSI, in case MSI was not the default source.*/ + RCC->CFGR = 0U; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) + ; /* Wait until MSI is selected. */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1_v2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1_v2.inc new file mode 100644 index 000000000..ccd162377 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1_v2.inc @@ -0,0 +1,337 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_pllsai1_v2.inc + * @brief Shared PLLSAI1 handler. + * + * @addtogroup STM32_PLLSAI1_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_PLLSAI1) +#define STM32_RCC_HAS_PLLSAI1 FALSE +#endif + +#if STM32_RCC_HAS_PLLSAI1 + +/* Checks on configurations.*/ +#if !defined(STM32_PLLSRC) +#error "STM32_PLLSRC not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLLSAI1N_VALUE) +#error "STM32_PLLSAI1N_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLLSAI1_HAS_P && !defined(STM32_PLLSAI1P_VALUE) +#error "STM32_PLLSAI1P_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLLSAI1_HAS_Q && !defined(STM32_PLLSAI1Q_VALUE) +#error "STM32_PLLSAI1Q_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLLSAI1_HAS_R && !defined(STM32_PLLSAI1R_VALUE) +#error "STM32_PLLSAI1R_VALUE not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PLLIN_MAX) +#error "STM32_PLLIN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLIN_MIN) +#error "STM32_PLLIN_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLSAI1VCO_MAX) +#error "STM32_PLLSAI1VCO_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLSAI1VCO_MIN) +#error "STM32_PLLSAI1VCO_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLSAI1N_VALUE_MAX) +#error "STM32_PLLSAI1N_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLSAI1N_VALUE_MIN) +#error "STM32_PLLSAI1N_VALUE_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLLSAI1_HAS_P + +#if !defined(STM32_PLLSAI1P_VALUE_MAX) +#error "STM32_PLLSAI1P_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLSAI1P_VALUE_MIN) +#error "STM32_PLLSAI1P_VALUE_MIN not defined in hal_lld.h" +#endif + +#endif /* STM32_RCC_PLLSAI1_HAS_P */ + +#if STM32_RCC_PLLSAI1_HAS_Q + +#if !defined(STM32_PLLSAI1Q_VALUE_MAX) +#error "STM32_PLLSAI1Q_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLSAI1Q_VALUE_MIN) +#error "STM32_PLLSAI1Q_VALUE_MIN not defined in hal_lld.h" +#endif + +#endif /* STM32_RCC_PLLSAI1_HAS_Q */ + +#if STM32_RCC_PLLSAI1_HAS_R + +#if !defined(STM32_PLLSAI1R_VALUE_MAX) +#error "STM32_PLLSAI1R_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLSAI1R_VALUE_MIN) +#error "STM32_PLLSAI1R_VALUE_MIN not defined in hal_lld.h" +#endif + +#endif /* STM32_RCC_PLLSAI1_HAS_R */ + +/* Input checks.*/ +#if !defined(STM32_ACTIVATE_PLLSAI1) +#error "STM32_ACTIVATE_PLLSAI1 not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLLSAI1_HAS_P && !defined(STM32_PLLSAI1PEN) +#error "STM32_PLLSAI1PEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLLSAI1_HAS_Q && !defined(STM32_PLLSAI1QEN) +#error "STM32_PLLSAI1QEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLLSAI1_HAS_R && !defined(STM32_PLLSAI1REN) +#error "STM32_PLLSAI1REN not defined in hal_lld.h" +#endif + +#if STM32_ACTIVATE_PLLSAI1 && (STM32_PLLSAI1CLKIN == 0) +#error "PLLSAI1 activation required but no PLL clock selected" +#endif + +#if ((STM32_PLLSAI1CLKIN != 0) && \ + ((STM32_PLLSAI1CLKIN < STM32_PLLIN_MIN) || \ + (STM32_PLLSAI1CLKIN > STM32_PLLIN_MAX))) || defined(__DOXYGEN__) +#error "STM32_PLLSAI1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief STM32_PLLSAI1N field. + */ +#if ((STM32_PLLSAI1N_VALUE >= STM32_PLLSAI1N_VALUE_MIN) && \ + (STM32_PLLSAI1N_VALUE <= STM32_PLLSAI1N_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << RCC_PLLSAI1CFGR_PLLN_Pos) + +#else +#error "invalid STM32_PLLSAI1N_VALUE value specified" +#endif + +/** + * @brief PLLSAI1 VCO frequency. + */ +#define STM32_PLLSAI1VCO (STM32_PLLSAI1CLKIN * STM32_PLLSAI1N_VALUE) + +/* + * PLLSAI1 VCO frequency range check. + */ +#if STM32_ACTIVATE_PLLSAI1 && \ + ((STM32_PLLSAI1VCO < STM32_PLLSAI1VCO_MIN) || \ + (STM32_PLLSAI1VCO > STM32_PLLSAI1VCO_MAX)) || defined(__DOXYGEN__) +#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/*---------------------------------------------------------------------------*/ +/* P output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLLSAI1_HAS_P || defined(__DOXYGEN__) +/** + * @brief STM32_PLLSAI1P field. + */ +#if STM32_PLLSAI1P_VALUE >= STM32_PLLSAI1P_VALUE_MIN && \ + STM32_PLLSAI1P_VALUE <= STM32_PLLSAI1P_VALUE_MAX || defined(__DOXYGEN__) +#define STM32_PLLSAI1P ((STM32_PLLSAI1P_VALUE - 1) << RCC_PLLSAI1CFGR_PLLP_Pos) +#else +#error "invalid STM32_PLLSAI1P_VALUE value specified" +#endif + +/** + * @brief PLLSAI1 P output clock frequency. + */ +#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE) + +/* + * PLLSAI1-P output frequency range check. + */ +#if STM32_ACTIVATE_PLLSAI1 && \ + ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || \ + (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX)) || defined(__DOXYGEN__) +#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" +#endif + +#else /* !STM32_RCC_PLLSAI1_HAS_P */ +#define STM32_PLLSAI1P 0U +#define STM32_PLLSAI1PEN 0U +#endif /* !STM32_RCC_PLLSAI1_HAS_P */ + +/*---------------------------------------------------------------------------*/ +/* Q output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLLSAI1_HAS_Q || defined(__DOXYGEN__) +/** + * @brief STM32_PLLSAI1Q field. + */ +#if (STM32_PLLSAI1Q_VALUE >= STM32_PLLSAI1Q_VALUE_MIN && \ + STM32_PLLSAI1Q_VALUE <= STM32_PLLSAI1Q_VALUE_MAX) || defined(__DOXYGEN__) +#define STM32_PLLSAI1Q ((STM32_PLLSAI1Q_VALUE - 1) << RCC_PLLSAI1CFGR_PLLQ_Pos) +#else +#error "invalid STM32_PLLSAI1Q_VALUE value specified" +#endif + +/** + * @brief PLLSAI1 Q output clock frequency. + */ +#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE) + +/* + * PLLSAI1-Q output frequency range check. + */ +#if (STM32_ACTIVATE_PLLSAI1 && \ + ((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || \ + (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))) || defined(__DOXYGEN__) +#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" +#endif + +#else /* !STM32_RCC_PLLSAI1_HAS_Q */ +#define STM32_PLLSAI1Q 0U +#define STM32_PLLSAI1QEN 0U +#endif /* !STM32_RCC_PLLSAI1_HAS_Q */ + +/*---------------------------------------------------------------------------*/ +/* R output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLLSAI1_HAS_R || defined(__DOXYGEN__) +/** + * @brief STM32_PLLSAI1R field. + */ +#if ((STM32_PLLSAI1R_VALUE >= STM32_PLLSAI1R_VALUE_MIN) && \ + (STM32_PLLSAI1R_VALUE <= STM32_PLLSAI1R_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAI1R ((STM32_PLLSAI1R_VALUE - 1) << RCC_PLLSAI1CFGR_PLLR_Pos) +#else +#error "invalid STM32_PLLSAI1R_VALUE value specified" +#endif + +/** + * @brief PLLSAI1 R output clock frequency. + */ +#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE) + +/* + * PLLSAI1-R output frequency range check. + */ +#if STM32_ACTIVATE_PLLSAI1 && \ + ((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || \ + (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX)) || defined(__DOXYGEN__) +#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" +#endif + +#else /* !STM32_RCC_PLLSAI1_HAS_R */ +#define STM32_PLLSAI1R 0U +#define STM32_PLLSAI1REN 0U +#endif /* !STM32_RCC_PLLSAI1_HAS_R */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE bool pllsai1_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLLSAI1RDY) == 0U); +} + +__STATIC_INLINE void pllsai1_wait_lock(void) { + + while (pllsai1_not_locked()) { + /* Waiting for PLLSAI1 lock.*/ + } +} + +#endif /* STM32_RCC_HAS_PLLSAI1 */ + +__STATIC_INLINE void pllsai1_init(void) { + +#if STM32_RCC_HAS_PLLSAI1 +#if STM32_ACTIVATE_PLLSAI1 + /* PLLSAI1 activation.*/ + RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN | + STM32_PLLSAI1Q | STM32_PLLSAI1QEN | + STM32_PLLSAI1P | STM32_PLLSAI1PEN | + STM32_PLLSAI1N; + RCC->CR |= RCC_CR_PLLSAI1ON; + + /* Waiting for PLL lock.*/ + while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0U) + ; +#endif +#endif +} + +__STATIC_INLINE void pllsai1_deinit(void) { + +#if STM32_RCC_HAS_PLLSAI1 +#if STM32_ACTIVATE_PLLSAI1 + /* PLLSAI1 de-activation.*/ + RCC->PLLSAI1CFGR &= ~RCC_CR_PLLSAI1ON; +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32WBxx/hal_lld.c b/os/hal/ports/STM32/STM32WBxx/hal_lld.c index 7405c28ea..5ea6166b7 100644 --- a/os/hal/ports/STM32/STM32WBxx/hal_lld.c +++ b/os/hal/ports/STM32/STM32WBxx/hal_lld.c @@ -49,54 +49,65 @@ uint32_t SystemCoreClock = STM32_HCLK; /*===========================================================================*/ /** - * @brief Initializes the backup domain. - * @note WARNING! Changing RTC clock source impossible without resetting - * of the whole BKP domain. + * @brief Safe setting of flash ACR register. + * + * @param[in] acr value for the ACR register */ -static void hal_lld_backup_domain_init(void) { +__STATIC_INLINE void flash_set_acr(uint32_t acr) { - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; + FLASH->ACR = acr; + while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) { + /* Waiting for flash wait states setup.*/ } +} -#if STM32_LSE_ENABLED - /* LSE activation.*/ -#if defined(STM32_LSE_BYPASS) - /* LSE Bypass.*/ - RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; -#else - /* No LSE Bypass.*/ - RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; +/** + * @brief Configures the PWR unit. + * @note CR1, CR2 and CR5 are not initialized inside this function. + */ +__STATIC_INLINE void hal_lld_set_static_pwr(void) { + /* Static PWR configurations.*/ + PWR->CR3 = STM32_PWR_CR3; + PWR->CR4 = STM32_PWR_CR4; + PWR->PUCRA = STM32_PWR_PUCRA; + PWR->PDCRA = STM32_PWR_PDCRA; + PWR->PUCRB = STM32_PWR_PUCRB; + PWR->PDCRB = STM32_PWR_PDCRB; + PWR->PUCRC = STM32_PWR_PUCRC; + PWR->PDCRC = STM32_PWR_PDCRC; + PWR->PUCRD = STM32_PWR_PUCRD; + PWR->PDCRD = STM32_PWR_PDCRD; + PWR->PUCRE = STM32_PWR_PUCRE; + PWR->PDCRE = STM32_PWR_PDCRE; + PWR->PUCRH = STM32_PWR_PUCRH; + PWR->PDCRH = STM32_PWR_PDCRH; +} + +/** + * @brief Initializes static muxes and dividers. + */ +__STATIC_INLINE void hal_lld_set_static_clocks(void) { + uint32_t ccipr; + + /* Clock-related settings (dividers, MCO etc).*/ + RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK | + STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + + /* Waiting for PPRE2, PPRE1 and HPRE applied. */ + while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk | + RCC_CFGR_HPREF_Msk)) != + (RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF)) + ; + + /* CCIPR2 register initialization, note, must take care of the _OFF + pseudo settings.*/ + ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL | + STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL | + STM32_USART1SEL | STM32_LPUART1SEL; +#if STM32_SAI1SEL != STM32_SAI1SEL_OFF + ccipr |= STM32_SAI1SEL; #endif - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Wait until LSE is stable. */ -#endif - -#if STM32_MSIPLL_ENABLED - /* MSI PLL activation depends on LSE. Reactivating and checking for - MSI stability.*/ - RCC->CR |= RCC_CR_MSIPLLEN; - while ((RCC->CR & RCC_CR_MSIRDY) == 0) - ; /* Wait until MSI is stable. */ -#endif - -#if HAL_USE_RTC - /* If the backup domain hasn't been initialized yet then proceed with - initialization.*/ - if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { - /* Selects clock source.*/ - RCC->BDCR |= STM32_RTCSEL; - - /* RTC clock enabled.*/ - RCC->BDCR |= RCC_BDCR_RTCEN; - } -#endif /* HAL_USE_RTC */ - - /* Low speed output mode.*/ - RCC->BDCR |= STM32_LSCOSEL; + RCC->CCIPR = ccipr; } /*===========================================================================*/ @@ -114,24 +125,14 @@ static void hal_lld_backup_domain_init(void) { */ void hal_lld_init(void) { - /* Reset of all peripherals. - Note, GPIOs are not reset because initialized before this point in - board files.*/ - rccResetAHB1(~0); - rccResetAHB2(~STM32_GPIO_EN_MASK); - rccResetAHB3(~0); - rccResetAPB1R1(~0); - rccResetAPB1R2(~0); - rccResetAPB2(~0); - - /* Initializes the backup domain.*/ - hal_lld_backup_domain_init(); - /* DMA subsystems initialization.*/ #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif + /* NVIC initialization.*/ + nvicInit(); + /* IRQ subsystem initialization.*/ irqInit(); @@ -157,138 +158,57 @@ void hal_lld_init(void) { */ void stm32_clock_init(void) { -#if 1 - RCC_TypeDef *rcc = RCC; /* For inspection.*/ - (void)rcc; -#endif - #if !STM32_NO_INIT - /* Initial clocks setup and wait for MSI stabilization, the MSI clock is - always enabled because it is the fall back clock when PLL the fails. - Trim fields are not altered from reset values.*/ + /* Reset of all peripherals. + Note, GPIOs are not reset because initialized before this point in + board files.*/ + rccResetAHB1(~0); + rccResetAHB2(~STM32_GPIO_EN_MASK); + rccResetAHB3(~0); + rccResetAPB1R1(~0); + rccResetAPB1R2(~0); + rccResetAPB2(~0); - /* MSIRANGE can be set only when MSI is OFF or READY.*/ - RCC->CR = RCC_CR_MSION; - while ((RCC->CR & RCC_CR_MSIRDY) == 0) - ; /* Wait until MSI is stable. */ + /* Flash setup for selected MSI speed setting.*/ + flash_set_acr(FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | + STM32_MSI_FLASHBITS); - /* Clocking from MSI, in case MSI was not the default source.*/ - RCC->CFGR = 0; - while ((RCC->CFGR & STM32_SW_MASK) != STM32_SW_MSI) - ; /* Wait until MSI is selected. */ + /* Static PWR configurations.*/ + hal_lld_set_static_pwr(); - /* Core voltage setup.*/ - PWR->CR1 = STM32_VOS; + /* Core voltage setup, backup domain access enabled and left open.*/ + PWR->CR1 = STM32_VOS | PWR_CR1_DBP; + + /* Additional PWR configurations.*/ + PWR->CR2 = STM32_PWR_CR2; /* Wait until regulator is stable. */ while ((PWR->SR2 & PWR_SR2_VOSF) != 0) ; -#if STM32_HSI16_ENABLED - /* HSI activation.*/ - RCC->CR |= RCC_CR_HSION; - while ((RCC->CR & RCC_CR_HSIRDY) == 0) - ; /* Wait until HSI16 is stable. */ -#endif + /* MSI clock reset.*/ + msi_reset(); -#if STM32_HSI48_ENABLED - /* HSI activation.*/ - RCC->CRRCR |= RCC_CRRCR_HSI48ON; - while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0) - ; /* Wait until HSI48 is stable. */ -#endif + /* Backup domain reset.*/ + bd_reset(); -#if STM32_HSE_ENABLED - /* HSE activation.*/ - RCC->CR |= RCC_CR_HSEON; - while ((RCC->CR & RCC_CR_HSERDY) == 0) - ; /* Wait until HSE is stable. */ + /* Clocks setup.*/ + lse_init(); + lsi_init(); + msi_init(); + hsi16_init(); + hsi48_init(); + hse32_init(); - /* HSE PRE setting.*/ - RCC->CR |= STM32_HSEPRE; -#endif + /* Backup domain initializations.*/ + bd_init(); -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSI1ON; - while ((RCC->CSR & RCC_CSR_LSI1RDY) == 0) - ; /* Wait until LSI is stable. */ -#endif + /* Static clocks setup.*/ + hal_lld_set_static_clocks(); - /* Backup domain access enabled and left open.*/ - PWR->CR1 |= PWR_CR1_DBP; - -#if STM32_LSE_ENABLED - /* LSE activation.*/ -#if defined(STM32_LSE_BYPASS) - /* LSE Bypass.*/ - RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; -#else - /* No LSE Bypass.*/ - RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; -#endif - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Wait until LSE is stable. */ -#endif - - /* Flash setup for selected MSI speed setting.*/ - FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | - STM32_MSI_FLASHBITS; - - /* Changing MSIRANGE to configured value.*/ - RCC->CR |= STM32_MSIRANGE; - while ((RCC->CR & RCC_CR_MSIRDY) == 0) - ; - - /* MSI is configured SYSCLK source so wait for it to be stable as well.*/ - while ((RCC->CFGR & STM32_SW_MASK) != STM32_SW_MSI) - ; - -#if STM32_MSIPLL_ENABLED - /* MSI PLL (to LSE) activation */ - RCC->CR |= RCC_CR_MSIPLLEN; -#endif - -#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 - /* PLLM and PLLSRC are common to all PLLs.*/ - RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN | - STM32_PLLQ | STM32_PLLQEN | - STM32_PLLP | STM32_PLLPEN | - STM32_PLLN | STM32_PLLM | - STM32_PLLSRC; -#endif - -#if STM32_ACTIVATE_PLL - /* PLL activation.*/ - RCC->CR |= RCC_CR_PLLON; - - /* Waiting for PLL clock.*/ - while ((RCC->CR & RCC_CR_PLLRDY) == 0) - ; -#endif - -#if STM32_ACTIVATE_PLLSAI1 - /* PLLSAI1 activation.*/ - RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN | - STM32_PLLSAI1Q | STM32_PLLSAI1QEN | - STM32_PLLSAI1P | STM32_PLLSAI1PEN | - STM32_PLLSAI1N; - RCC->CR |= RCC_CR_PLLSAI1ON; - - /* Waiting for PLL clock.*/ - while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0) - ; -#endif - - /* Other clock-related settings (dividers, MCO etc).*/ - RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK | - STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; - - /* Waiting for PPRE2, PPRE1 and HPRE applied. */ - while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk | - RCC_CFGR_HPREF_Msk)) != - (RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF)) - ; + /* PLLs activation, if required.*/ + pll_init(); + pllsai1_init(); /* Extended clock recovery register (HCLK2, HCLK4, HCLK5). */ RCC->EXTCFGR = STM32_RFCSSSEL | STM32_C2HPRE | STM32_SHDHPRE; @@ -299,24 +219,9 @@ void stm32_clock_init(void) { (RCC_EXTCFGR_C2HPREF | RCC_EXTCFGR_SHDHPREF)) ; - /* CCIPR register initialization, note, must take care of the _OFF - pseudo settings.*/ - { - uint32_t ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL | - STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL | - STM32_USART1SEL | STM32_LPUART1SEL; -#if STM32_SAI1SEL != STM32_SAI1SEL_OFF - ccipr |= STM32_SAI1SEL; -#endif - RCC->CCIPR = ccipr; - } - /* Set flash WS's for SYSCLK source */ if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) { - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS; - while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != - (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) { - } + flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS); } /* Switching to the configured SYSCLK source if it is different from MSI.*/ @@ -329,10 +234,7 @@ void stm32_clock_init(void) { /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */ if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) { - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS; - while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != - (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) { - } + flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS); } #endif /* STM32_NO_INIT */ diff --git a/os/hal/ports/STM32/STM32WBxx/hal_lld.h b/os/hal/ports/STM32/STM32WBxx/hal_lld.h index c981140b1..9839d4ad6 100644 --- a/os/hal/ports/STM32/STM32WBxx/hal_lld.h +++ b/os/hal/ports/STM32/STM32WBxx/hal_lld.h @@ -25,7 +25,7 @@ * - STM32_LSECLK. * - STM32_LSEDRV. * - STM32_LSE_BYPASS (optionally). - * - STM32_HSECLK. + * - STM32_HSE32CLK. * . * One of the following macros must also be defined: * - STM32WB55xx. @@ -67,15 +67,6 @@ #endif /** @} */ -/** - * @name Internal clock sources - * @{ - */ -#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */ -#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */ -#define STM32_LSICLK 32000 /**< Low speed internal clock. */ -/** @} */ - /** * @name PWR_CR1 register bits definitions * @{ @@ -100,30 +91,12 @@ #define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */ /** @} */ -/** - * @name RCC_CR register bits definitions - * @{ - */ -#define STM32_MSIRANGE_MASK (15 << 4) /**< MSIRANGE field mask. */ -#define STM32_MSIRANGE_100K (0 << 4) /**< 100kHz nominal. */ -#define STM32_MSIRANGE_200K (1 << 4) /**< 200kHz nominal. */ -#define STM32_MSIRANGE_400K (2 << 4) /**< 400kHz nominal. */ -#define STM32_MSIRANGE_800K (3 << 4) /**< 800kHz nominal. */ -#define STM32_MSIRANGE_1M (4 << 4) /**< 1MHz nominal. */ -#define STM32_MSIRANGE_2M (5 << 4) /**< 2MHz nominal. */ -#define STM32_MSIRANGE_4M (6 << 4) /**< 4MHz nominal. */ -#define STM32_MSIRANGE_8M (7 << 4) /**< 8MHz nominal. */ -#define STM32_MSIRANGE_16M (8 << 4) /**< 16MHz nominal. */ -#define STM32_MSIRANGE_24M (9 << 4) /**< 24MHz nominal. */ -#define STM32_MSIRANGE_32M (10 << 4) /**< 32MHz nominal. */ -#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */ - /** * @brief HSE SYSCLK and PLL M divider prescaler. */ -#define STM32_HSEPRE_MASK (1 << 20) /**< HSEPRE mask. */ -#define STM32_HSEPRE_DIV1 (0 << 20) /**< HSE divided by 1. */ -#define STM32_HSEPRE_DIV2 (1 << 20) /**< HSE divided by 2. */ +#define STM32_HSE32PRE_MASK (1 << 20) /**< HSEPRE mask. */ +#define STM32_HSE32PRE_DIV1 (0 << 20) /**< HSE divided by 1. */ +#define STM32_HSE32PRE_DIV2 (1 << 20) /**< HSE divided by 2. */ /** @} */ /** @@ -136,35 +109,32 @@ #define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ #define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */ -#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */ -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV3 (1 << 4) /**< SYSCLK divided by 3. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV5 (2 << 4) /**< SYSCLK divided by 5. */ -#define STM32_HPRE_DIV6 (5 << 4) /**< SYSCLK divided by 6. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV10 (6 << 4) /**< SYSCLK divided by 10. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV32 (7 << 4) /**< SYSCLK divided by 32. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ +/* STM32WB CMSIS headers don't have these macros */ +#if !defined(RCC_CFGR_SW_MSI) +#define RCC_CFGR_SW_MSI (0x0U << RCC_CFGR_SW_Pos) +#endif +#if !defined(RCC_CFGR_SW_HSI) +#define RCC_CFGR_SW_HSI (0x1U << RCC_CFGR_SW_Pos) +#endif +#if !defined(RCC_CFGR_SW_HSE) +#define RCC_CFGR_SW_HSE (0x2U << RCC_CFGR_SW_Pos) +#endif +#if !defined(RCC_CFGR_SW_PLL) +#define RCC_CFGR_SW_PLL (0x3U << RCC_CFGR_SW_Pos) +#endif -#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */ -#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */ -#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ +#if !defined(RCC_CFGR_SWS_MSI) +#define RCC_CFGR_SWS_MSI (0x0U << RCC_CFGR_SWS_Pos) +#endif +#if !defined(RCC_CFGR_SWS_HSI) +#define RCC_CFGR_SWS_HSI (0x1U << RCC_CFGR_SWS_Pos) +#endif +#if !defined(RCC_CFGR_SWS_HSE) +#define RCC_CFGR_SWS_HSE (0x2U << RCC_CFGR_SWS_Pos) +#endif +#if !defined(RCC_CFGR_SWS_PLL) +#define RCC_CFGR_SWS_PLL (0x3U << RCC_CFGR_SWS_Pos) +#endif #define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */ #define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */ @@ -175,11 +145,15 @@ #define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ #define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */ #define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */ -#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */ -#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */ -#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */ -#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */ +#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. + (after stabilization) */ +#define STM32_MCOSEL_PLLRCLK (5 << 24) /**< PLLR clock on MCO pin. */ +#define STM32_MCOSEL_LSI1 (6 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSI2 (7 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSE (8 << 24) /**< LSE clock on MCO pin. */ +#define STM32_MCOSEL_HSI48 (9 << 24) /**< HSI48 clock on MCO pin. */ +#define STM32_MCOSEL_HSE2 (4 << 24) /**< HSE clock on MCO pin. + (before stabilization) */ #define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */ #define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */ @@ -295,22 +269,23 @@ #define STM32_LPTIM2SEL_HSI16 (2 << 20) /**< LPTIM2 source is HSI16. */ #define STM32_LPTIM2SEL_LSE (3 << 20) /**< LPTIM2 source is LSE. */ -#define STM32_SAI1SEL_MASK (3 << 22) /**< SAI1SEL mask. */ -#define STM32_SAI1SEL_PLLSAI1 (0 << 22) /**< SAI1 source is PLLSAI1-P. */ -#define STM32_SAI1SEL_PLL (2 << 22) /**< SAI1 source is PLL-P. */ -#define STM32_SAI1SEL_EXTCLK (3 << 22) /**< SAI1 source is external. */ -#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ +#define STM32_SAI1SEL_MASK (3 << 22) /**< SAI1SEL mask. */ +#define STM32_SAI1SEL_PLLSAI1PCLK (0 << 22) /**< SAI1 source is PLLSAI1PCLK.*/ +#define STM32_SAI1SEL_PLLPCLK (2 << 22) /**< SAI1 source is PLLPCLK. */ +#define STM32_SAI1SEL_EXTCLK (3 << 22) /**< SAI1 source is external. */ +#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ -#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */ -#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */ -#define STM32_CLK48SEL_PLLSAI1 (1 << 26) /**< CLK48 source is PLLSAI1-Q. */ -#define STM32_CLK48SEL_PLL (2 << 26) /**< CLK48 source is PLL-Q. */ -#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */ +#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */ +#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */ +#define STM32_CLK48SEL_PLLSAI1QCLK (1 << 26) /**< CLK48 source is SAI1-Q. */ +#define STM32_CLK48SEL_PLLQCLK (2 << 26) /**< CLK48 source is PLLQCLK. */ +#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */ -#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */ -#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */ -#define STM32_ADCSEL_PLLSAI1 (1 << 28) /**< ADC source is PLLSAI1-R. */ -#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */ +#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */ +#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */ +#define STM32_ADCSEL_PLLSAI1RCLK (1 << 28) /**< ADC source is PLLSAI1RCLK. */ +#define STM32_ADCSEL_PLLPCLK (2 << 28) /**< ADC source is PLLPCLK. */ +#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */ #define STM32_RNGSEL_MASK (3 << 30) /**< RNGSEL mask. */ #define STM32_RNGSEL_48CLK (0 << 30) /**< RNG source is CLK48SEL. */ @@ -359,6 +334,139 @@ #define STM32_VOS STM32_VOS_RANGE1 #endif +/** + * @brief PWR CR2 register initialization value. + */ +#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__) +#define STM32_PWR_CR2 (PWR_CR2_PLS_0) +#endif + +/** + * @brief PWR CR3 register initialization value. + */ +#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__) +#define STM32_PWR_CR3 (PWR_CR3_EIWUL) +#endif + +/** + * @brief PWR CR4 register initialization value. + */ +#if !defined(STM32_PWR_CR4) || defined(__DOXYGEN__) +#define STM32_PWR_CR4 (0U) +#endif + +/** + * @brief PWR PUCRA register initialization value. + */ +#if !defined(STM32_PWR_PUCRA) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRA (0U) +#endif + +/** + * @brief PWR PDCRA register initialization value. + */ +#if !defined(STM32_PWR_PDCRA) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRA (0U) +#endif + +/** + * @brief PWR PUCRB register initialization value. + */ +#if !defined(STM32_PWR_PUCRB) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRB (0U) +#endif + +/** + * @brief PWR PDCRB register initialization value. + */ +#if !defined(STM32_PWR_PDCRB) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRB (0U) +#endif + +/** + * @brief PWR PUCRC register initialization value. + */ +#if !defined(STM32_PWR_PUCRC) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRC (0U) +#endif + +/** + * @brief PWR PDCRC register initialization value. + */ +#if !defined(STM32_PWR_PDCRC) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRC (0U) +#endif + +/** + * @brief PWR PUCRD register initialization value. + */ +#if !defined(STM32_PWR_PUCRD) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRD (0U) +#endif + +/** + * @brief PWR PDCRD register initialization value. + */ +#if !defined(STM32_PWR_PDCRD) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRD (0U) +#endif + +/** + * @brief PWR PUCRE register initialization value. + */ +#if !defined(STM32_PWR_PUCRE) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRE (0U) +#endif + +/** + * @brief PWR PDCRE register initialization value. + */ +#if !defined(STM32_PWR_PDCRE) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRE (0U) +#endif + +/** + * @brief PWR PUCRF register initialization value. + */ +#if !defined(STM32_PWR_PUCRF) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRF (0U) +#endif + +/** + * @brief PWR PDCRF register initialization value. + */ +#if !defined(STM32_PWR_PDCRF) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRF (0U) +#endif + +/** + * @brief PWR PUCRG register initialization value. + */ +#if !defined(STM32_PWR_PUCRG) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRG (0U) +#endif + +/** + * @brief PWR PDCRG register initialization value. + */ +#if !defined(STM32_PWR_PDCRG) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRG (0U) +#endif + +/** + * @brief PWR PUCRH register initialization value. + */ +#if !defined(STM32_PWR_PUCRH) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRH (0U) +#endif + +/** + * @brief PWR PDCRH register initialization value. + */ +#if !defined(STM32_PWR_PDCRH) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRH (0U) +#endif + /** * @brief Enables or disables the programmable voltage detector. */ @@ -390,15 +498,15 @@ /** * @brief Enables or disables the LSI clock source. */ -#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSI_ENABLED TRUE +#if !defined(STM32_LSI1_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI1_ENABLED TRUE #endif /** * @brief Enables or disables the HSE clock source. */ -#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSE_ENABLED FALSE +#if !defined(STM32_HSE32_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE32_ENABLED FALSE #endif /** @@ -423,10 +531,10 @@ #endif /** - * @brief HSE and PLL M devider prescaler setting. + * @brief HSE32 prescaler value. */ -#if !defined(STM32_HSEPRE_VALUE) || defined(__DOXYGEN__) -#define STM32_HSEPRE_VALUE 1 +#if !defined(STM32_HSE32PRE) || defined(__DOXYGEN__) +#define STM32_HSE32PRE STM32_HSE32PRE_DIV1 #endif /** @@ -656,7 +764,8 @@ * @brief CLK48SEL value (48MHz clock source). */ #if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__) -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_CLK48SEL STM32_CLK48SEL_PLLQCLK +// #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK #endif /** @@ -703,10 +812,6 @@ #error "STM32_LSEDRV not defined in board.h" #endif -#if !defined(STM32_HSECLK) -#error "STM32_HSECLK not defined in board.h" -#endif - /* Voltage related limits.*/ #if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__) /** @@ -723,16 +828,6 @@ */ #define STM32_C2HPRE_MAX 32000000 -/** - * @brief Maximum HSE clock frequency at current voltage setting. - */ -#define STM32_HSECLK_MAX 32000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_MIN 32000000 - /** * @brief Maximum LSE clock frequency. */ @@ -773,16 +868,6 @@ */ #define STM32_PLLVCO_MIN 96000000 -/** - * @brief Maximum VCO clock frequency at current voltage setting. - */ -#define STM32_PLLSAI1VCO_MAX 344000000 - -/** - * @brief Minimum VCO clock frequency at current voltage setting. - */ -#define STM32_PLLSAI1VCO_MIN 64000000 - /** * @brief Maximum PLL-P output clock frequency. */ @@ -813,6 +898,16 @@ */ #define STM32_PLLR_MIN 8000000 +/** + * @brief Maximum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLSAI1VCO_MAX 344000000 + +/** + * @brief Minimum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLSAI1VCO_MIN 64000000 + /** * @brief Maximum APB1 clock frequency. */ @@ -841,8 +936,6 @@ #elif STM32_VOS == STM32_VOS_RANGE2 #define STM32_SYSCLK_MAX 16000000 #define STM32_C2HPRE_MAX 16000000 -#define STM32_HSECLK_MAX 32000000 -#define STM32_HSECLK_MIN 32000000 #define STM32_LSECLK_MAX 32768 #define STM32_LSECLK_BYP_MAX 1000000 #define STM32_LSECLK_MIN 32768 @@ -872,46 +965,43 @@ #endif /** - * @brief MSI frequency. + * @name PLL dividers limits + * @{ */ -#if STM32_MSIRANGE == STM32_MSIRANGE_100K -#define STM32_MSICLK 100000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_200K -#define STM32_MSICLK 200000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_400K -#define STM32_MSICLK 400000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_800K -#define STM32_MSICLK 800000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_1M -#define STM32_MSICLK 1000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_2M -#define STM32_MSICLK 2000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_4M -#define STM32_MSICLK 4000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_8M -#define STM32_MSICLK 8000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_16M -#define STM32_MSICLK 16000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_24M -#define STM32_MSICLK 24000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_32M -#define STM32_MSICLK 32000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_48M -#define STM32_MSICLK 48000000 -#else -#error "invalid STM32_MSIRANGE value specified" -#endif +#define STM32_PLLM_VALUE_MAX 8 +#define STM32_PLLM_VALUE_MIN 1 +#define STM32_PLLN_VALUE_MAX 127 +#define STM32_PLLN_VALUE_MIN 6 +#define STM32_PLLR_VALUE_MAX 8 +#define STM32_PLLR_VALUE_MIN 2 +#define STM32_PLLQ_VALUE_MAX 8 +#define STM32_PLLQ_VALUE_MIN 2 +#define STM32_PLLP_VALUE_MAX 32 +#define STM32_PLLP_VALUE_MIN 2 +/** @} */ /** - * @brief HSE prescale divider. + * @name PLLSAI1 dividers limits + * @{ */ -#if STM32_HSEPRE_VALUE == 1 -#define STM32_HSEPRE STM32_HSEPRE_DIV1 -#elif STM32_HSEPRE_VALUE == 2 -#define STM32_HSEPRE STM32_HSEPRE_DIV2 -#else -#error "invalid STM32_HSEPRE_VALUE value specified" -#endif +#define STM32_PLLSAI1N_VALUE_MAX 86 +#define STM32_PLLSAI1N_VALUE_MIN 4 +#define STM32_PLLSAI1R_VALUE_MAX 8 +#define STM32_PLLSAI1R_VALUE_MIN 2 +#define STM32_PLLSAI1Q_VALUE_MAX 8 +#define STM32_PLLSAI1Q_VALUE_MIN 2 +#define STM32_PLLSAI1P_VALUE_MAX 32 +#define STM32_PLLSAI1P_VALUE_MIN 2 +/** @} */ + +/* Clock handlers.*/ +#include "stm32_bd.inc" +#include "stm32_lse.inc" +#include "stm32_lsi_v2.inc" +#include "stm32_msi_v2.inc" +#include "stm32_hsi16.inc" +#include "stm32_hsi48.inc" +#include "stm32_hse32.inc" /* * HSI16 related checks. @@ -928,12 +1018,12 @@ #endif #if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \ (STM32_PLLSRC == STM32_PLLSRC_HSI16)) #error "HSI16 not enabled, required by STM32_MCOSEL" #endif -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) && \ +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) && \ (STM32_PLLSRC == STM32_PLLSRC_HSI16) #error "HSI16 not enabled, required by STM32_SAI1SEL" #endif @@ -980,17 +1070,17 @@ /* * HSE related checks. */ -#if STM32_HSE_ENABLED +#if STM32_HSE32_ENABLED - #if STM32_HSECLK == 0 + #if STM32_HSE32CLK == 0 #error "HSE frequency not defined" - #else /* STM32_HSECLK != 0 */ - #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) - #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" + #else /* STM32_HSE32CLK != 0 */ + #if STM32_HSE32CLK != 32000000 + #error "STM32_HSE32CLK is not 32 Mhz" #endif - #endif /* STM32_HSECLK != 0 */ + #endif /* STM32_HSE32CLK != 0 */ - #else /* !STM32_HSE_ENABLED */ + #else /* !STM32_HSE32_ENABLED */ #if STM32_SW == STM32_SW_HSE #error "HSE not enabled, required by STM32_SW" @@ -1001,12 +1091,12 @@ #endif #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \ (STM32_PLLSRC == STM32_PLLSRC_HSE)) #error "HSE not enabled, required by STM32_MCOSEL" #endif - #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) && \ + #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) && \ (STM32_PLLSRC == STM32_PLLSRC_HSE) #error "HSE not enabled, required by STM32_SAI1SEL" #endif @@ -1019,33 +1109,38 @@ #error "HSE not enabled, required by RFCSS" #endif -#endif /* !STM32_HSE_ENABLED */ +#endif /* !STM32_HSE32_ENABLED */ /* * LSI related checks. */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ +#if !(STM32_LSI1_ENABLED || STM32_LSI2_ENABLED) #if STM32_RTCSEL == STM32_RTCSEL_LSI - #error "LSI not enabled, required by STM32_RTCSEL" - #endif - - #if STM32_MCOSEL == STM32_MCOSEL_LSI - #error "LSI not enabled, required by STM32_MCOSEL" + #error "LSI1 or LSI2 not enabled, required by STM32_RTCSEL" #endif #if STM32_LSCOSEL == STM32_LSCOSEL_LSI - #error "LSI not enabled, required by STM32_LSCOSEL" + #error "LSI1 or LSI2 not enabled, required by STM32_LSCOSEL" #endif #if STM32_RNGSEL == STM32_RNGSEL_LSI - #error "LSI not enabled, required by STM32_RNGSEL" + #error "LSI1 or LSI2 not enabled, required by STM32_RNGSEL" #endif -#endif /* !STM32_LSI_ENABLED */ +#endif /* !(STM32_LSI1_ENABLED || STM32_LSI2_ENABLED) */ -/* TODO(ilya): STM32WBXX family has two LSI clocks, support both of them. */ +#if !STM32_LSI1_ENABLED + #if STM32_MCOSEL == STM32_MCOSEL_LSI1 + #error "LSI1 not enabled, required by STM32_MCOSEL" + #endif +#endif + +#if !STM32_LSI2_ENABLED + #if STM32_MCOSEL == STM32_MCOSEL_LSI2 + #error "LSI2 not enabled, required by STM32_MCOSEL" + #endif +#endif /* * LSE related checks. @@ -1091,22 +1186,11 @@ #warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED" #endif -/** - * @brief STM32_PLLM field. - */ -#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) || \ - defined(__DOXYGEN__) -#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4) -#else -#error "invalid STM32_PLLM_VALUE value specified" -#endif - /** * @brief PLLs input clock frequency. */ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN ((STM32_HSECLK / STM32_HSEPRE_VALUE) \ - / STM32_PLLM_VALUE) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) #elif STM32_PLLSRC == STM32_PLLSRC_MSI #define STM32_PLLCLKIN (STM32_MSICLK / STM32_PLLM_VALUE) @@ -1129,13 +1213,30 @@ #error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" #endif +/* + * PLLSAI1 enable check. + */ +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || \ + (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK) || \ + defined(__DOXYGEN__) +/** + * @brief PLLSAI1 activation flag. + */ +#define STM32_ACTIVATE_PLLSAI1 TRUE +#else +#define STM32_ACTIVATE_PLLSAI1 FALSE +#endif + /* * PLL enable check. */ -#if (STM32_HSI48_ENABLED && (STM32_CLK48SEL == STM32_CLK48SEL_PLL)) || \ +#if (STM32_HSI48_ENABLED && (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK)) || \ (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ + (STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ + (STM32_ACTIVATE_PLLSAI1) || \ defined(__DOXYGEN__) #if STM32_PLLCLKIN == 0 @@ -1150,50 +1251,13 @@ #define STM32_ACTIVATE_PLL FALSE #endif -/** - * @brief STM32_PLLN field. - */ -#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) || \ - defined(__DOXYGEN__) -#define STM32_PLLN (STM32_PLLN_VALUE << 8) -#else -#error "invalid STM32_PLLN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLP field. - */ -#if ((STM32_PLLP_VALUE >= 2) && (STM32_PLLP_VALUE <= 32)) || \ - defined(__DOXYGEN__) -#define STM32_PLLP ((STM32_PLLP_VALUE -1) << 17) -#else -#error "invalid STM32_PLLP_VALUE value specified" -#endif - -/** - * @brief STM32_PLLQ field. - */ -#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 8)) || \ - defined(__DOXYGEN__) -#define STM32_PLLQ ((STM32_PLLQ_VALUE - 1) << 25) -#else -#error "invalid STM32_PLLQ_VALUE value specified" -#endif - -/** - * @brief STM32_PLLR field. - */ -#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 8)) || \ - defined(__DOXYGEN__) -#define STM32_PLLR ((STM32_PLLR_VALUE - 1) << 29) -#else -#error "invalid STM32_PLLR_VALUE value specified" -#endif /** * @brief STM32_PLLPEN field. */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || defined(__DOXYGEN__) +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ + defined(__DOXYGEN__) #define STM32_PLLPEN (1 << 16) #else #define STM32_PLLPEN (0 << 16) @@ -1202,7 +1266,7 @@ /** * @brief STM32_PLLQEN field. */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_PLL) || defined(__DOXYGEN__) +#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || defined(__DOXYGEN__) #define STM32_PLLQEN (1 << 24) #else #define STM32_PLLQEN (0 << 24) @@ -1212,64 +1276,15 @@ * @brief STM32_PLLREN field. */ #if (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ defined(__DOXYGEN__) #define STM32_PLLREN (1 << 28) #else #define STM32_PLLREN (0 << 28) #endif -/** - * @brief PLL VCO frequency. - */ -#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) - -/* - * PLL VCO frequency range check. - */ -#if STM32_ACTIVATE_PLL && \ - ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)) -#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLL P output clock frequency. - */ -#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) - -/** - * @brief PLL Q output clock frequency. - */ -#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE) - -/** - * @brief PLL R output clock frequency. - */ -#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE) - -/* - * PLL-P output frequency range check. - */ -#if STM32_ACTIVATE_PLL && \ - ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX)) -#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" -#endif - -/* - * PLL-Q output frequency range check. - */ -#if STM32_ACTIVATE_PLL && \ - ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX)) -#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" -#endif - -/* - * PLL-R output frequency range check. - */ -#if STM32_ACTIVATE_PLL && \ - ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX)) -#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" -#endif +/* Inclusion of PLL-related checks and calculations.*/ +#include "stm32_pll_v2.inc" /** * @brief System clock source. @@ -1284,7 +1299,7 @@ #define STM32_SYSCLK STM32_HSI16CLK #elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK (STM32_HSECLK / STM32_HSEPRE_VALUE) +#define STM32_SYSCLK STM32_HSECLK #elif (STM32_SW == STM32_SW_PLL) #define STM32_SYSCLK STM32_PLL_R_CLKOUT @@ -1293,124 +1308,10 @@ #error "invalid STM32_SW value specified" #endif -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief HCLK1 frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) - -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) - -#elif STM32_HPRE == STM32_HPRE_DIV3 -#define STM32_HCLK (STM32_SYSCLK / 3) - -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) - -#elif STM32_HPRE == STM32_HPRE_DIV5 -#define STM32_HCLK (STM32_SYSCLK / 5) - -#elif STM32_HPRE == STM32_HPRE_DIV6 -#define STM32_HCLK (STM32_SYSCLK / 6) - -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) - -#elif STM32_HPRE == STM32_HPRE_DIV10 -#define STM32_HCLK (STM32_SYSCLK / 10) - -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) - -#elif STM32_HPRE == STM32_HPRE_DIV32 -#define STM32_HCLK (STM32_SYSCLK / 32) - -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) - -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) - -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) - -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) - -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* - * HCLK1 frequency check. - */ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) - -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* - * APB1 frequency check. - */ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) - -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* - * APB2 frequency check. - */ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif +/* Bus handlers.*/ +#include "stm32_ahb.inc" +#include "stm32_apb1.inc" +#include "stm32_apb2.inc" /** * @brief HCLK2 (CPU2) frequency. @@ -1517,70 +1418,10 @@ #error "invalid STM32_SHDHPRE value specified" #endif -/* - * PLLSAI1 enable check. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \ - (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \ - (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \ - defined(__DOXYGEN__) - -#if STM32_PLLCLKIN == 0 -#error "PLLSAI1 activation required but no PLL clock selected" -#endif - -/** - * @brief PLLSAI1 activation flag. - */ -#define STM32_ACTIVATE_PLLSAI1 TRUE -#else -#define STM32_ACTIVATE_PLLSAI1 FALSE -#endif - -/** - * @brief STM32_PLLSAI1N field. - */ -#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 86)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8) -#else -#error "invalid STM32_PLLSAI1N_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1P field. - */ -#if ((STM32_PLLSAI1P_VALUE >= 2) && (STM32_PLLSAI1P_VALUE <= 32)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1P ((STM32_PLLSAI1P_VALUE -1) << 17) -#else -#error "invalid STM32_PLLSAI1P_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1Q field. - */ -#if ((STM32_PLLSAI1Q_VALUE >= 2) && (STM32_PLLSAI1Q_VALUE <= 8)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1Q ((STM32_PLLSAI1Q_VALUE -1) << 25) -#else -#error "invalid STM32_PLLSAI1Q_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1R field. - */ -#if ((STM32_PLLSAI1R_VALUE >= 2) && (STM32_PLLSAI1R_VALUE <= 8)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1R ((STM32_PLLSAI1R_VALUE -1) << 29) -#else -#error "invalid STM32_PLLSAI1R_VALUE value specified" -#endif - /** * @brief STM32_PLLSAI1PEN field. */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \ +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || \ defined(__DOXYGEN__) #define STM32_PLLSAI1PEN (1 << 16) #else @@ -1590,7 +1431,7 @@ /** * @brief STM32_PLLSAI1QEN field. */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || defined(__DOXYGEN__) +#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK) || defined(__DOXYGEN__) #define STM32_PLLSAI1QEN (1 << 24) #else #define STM32_PLLSAI1QEN (0 << 24) @@ -1599,64 +1440,16 @@ /** * @brief STM32_PLLSAI1REN field. */ -#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || defined(__DOXYGEN__) +#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK) || defined(__DOXYGEN__) #define STM32_PLLSAI1REN (1 << 28) #else #define STM32_PLLSAI1REN (0 << 28) #endif -/** - * @brief PLLSAI1 VCO frequency. - */ -#define STM32_PLLSAI1VCO (STM32_PLLCLKIN * STM32_PLLSAI1N_VALUE) - -/* - * PLLSAI1 VCO frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1VCO < STM32_PLLSAI1VCO_MIN) || \ - (STM32_PLLSAI1VCO > STM32_PLLSAI1VCO_MAX)) -#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLLSAI1-P output clock frequency. - */ -#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE) - -/** - * @brief PLLSAI1-Q output clock frequency. - */ -#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE) - -/** - * @brief PLLSAI1-R output clock frequency. - */ -#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE) - -/* - * PLLSAI1-P output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX)) -#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" -#endif - -/* - * PLLSAI1-Q output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX)) -#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" -#endif - -/* - * PLLSAI1-R output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX)) -#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" -#endif +/* Inclusion of PLLSAI-related checks and calculations, all PLLs share the + same clock source so enforcing this condition.*/ +#define STM32_PLLSAI1CLKIN STM32_PLLCLKIN +#include "stm32_pllsai1_v2.inc" /** * @brief MCO divider clock frequency. @@ -1674,12 +1467,12 @@ #define STM32_MCODIVCLK STM32_HSI16CLK #elif STM32_MCOSEL == STM32_MCOSEL_HSE -#define STM32_MCODIVCLK STM32_HSECLK +#define STM32_MCODIVCLK STM32_HSE32CLK -#elif STM32_MCOSEL == STM32_MCOSEL_PLL +#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK #define STM32_MCODIVCLK STM32_PLL_P_CLKOUT -#elif STM32_MCOSEL == STM32_MCOSEL_LSI +#elif (STM32_MCOSEL == STM32_MCOSEL_LSI1 || STM32_MCOSEL == STM32_MCOSEL_LSI2) #define STM32_MCODIVCLK STM32_LSICLK #elif STM32_MCOSEL == STM32_MCOSEL_LSE @@ -1727,7 +1520,7 @@ #define STM32_RTCCLK STM32_LSICLK #elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK (STM32_HSECLK / 32) +#define STM32_RTCCLK (STM32_HSE32CLK / 32) #else #error "invalid STM32_RTCSEL value specified" @@ -1824,9 +1617,9 @@ */ #if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__) #define STM32_48CLK STM32_HSI48CLK -#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1 +#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK #define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE) -#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL +#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK #define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) #elif STM32_CLK48SEL == STM32_CLK48SEL_MSI #define STM32_48CLK STM32_MSICLK @@ -1837,9 +1630,9 @@ /** * @brief SAI1 clock frequency. */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || defined(__DOXYGEN__) +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || defined(__DOXYGEN__) #define STM32_SAI1CLK STM32_PLLSAI1_P_CLKOUT -#elif STM32_SAI1SEL == STM32_SAI1SEL_PLL +#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK #define STM32_SAI1CLK STM32_PLL_P_CLKOUT #elif STM32_SAI1SEL == STM32_SAI1SEL_EXTCLK #define STM32_SAI1CLK 0 /* Unknown, would require a board value */ @@ -1872,8 +1665,10 @@ */ #if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__) #define STM32_ADCCLK 0 -#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1 +#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK #define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT +#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK +#define STM32_ADCCLK STM32_PLL_P_CLKOUT #elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK #define STM32_ADCCLK STM32_SYSCLK #else diff --git a/os/hal/ports/STM32/STM32WBxx/platform.mk b/os/hal/ports/STM32/STM32WBxx/platform.mk index 89293412a..b397932b6 100644 --- a/os/hal/ports/STM32/STM32WBxx/platform.mk +++ b/os/hal/ports/STM32/STM32WBxx/platform.mk @@ -1,46 +1,47 @@ -# Required platform files. -PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx/stm32_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx/hal_lld.c - -# Required include directories. -PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ - $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx - -# Optional platform files. -ifeq ($(USE_SMART_BUILD),yes) - -# Configuration files directory -ifeq ($(HALCONFDIR),) - ifeq ($(CONFDIR),) - HALCONFDIR = . - else - HALCONFDIR := $(CONFDIR) - endif -endif - -HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) - -else -endif - -# Drivers compatible with the platform. -include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk - -# Shared variables -ALLCSRC += $(PLATFORMSRC) -ALLINC += $(PLATFORMINC) +# Required platform files. +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx/stm32_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx/hal_lld.c + +# Required include directories. +PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) + +else +endif + +# Drivers compatible with the platform. +include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/STM32/STM32WBxx/stm32_registry.h b/os/hal/ports/STM32/STM32WBxx/stm32_registry.h index ff6e3f163..b49a52c44 100644 --- a/os/hal/ports/STM32/STM32WBxx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32WBxx/stm32_registry.h @@ -74,6 +74,28 @@ #if defined(STM32WB55xx) || defined(__DOXYGEN__) +/* RCC attributes.*/ +#define STM32_RCC_HAS_HSI16 TRUE +#define STM32_RCC_HAS_HSI48 TRUE +#define STM32_RCC_HAS_MSI TRUE +#define STM32_RCC_HAS_LSI FALSE +#define STM32_RCC_HAS_LSI1 TRUE +#define STM32_RCC_HAS_LSI2 TRUE +#define STM32_RCC_LSI2_TRIM_ADDR 0x1FFF7548U +#define STM32_RCC_HAS_LSE TRUE +#define STM32_RCC_HAS_HSE FALSE +#define STM32_RCC_HAS_HSE32 TRUE + +#define STM32_RCC_HAS_PLL TRUE +#define STM32_RCC_PLL_HAS_P TRUE +#define STM32_RCC_PLL_HAS_Q TRUE +#define STM32_RCC_PLL_HAS_R TRUE + +#define STM32_RCC_HAS_PLLSAI1 TRUE +#define STM32_RCC_PLLSAI1_HAS_P TRUE +#define STM32_RCC_PLLSAI1_HAS_Q TRUE +#define STM32_RCC_PLLSAI1_HAS_R TRUE + /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 FALSE diff --git a/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h index 3d88b2858..0ec5ccf3c 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -43,8 +43,9 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE +#define STM32_LSI1_ENABLED TRUE +#define STM32_LSI2_ENABLED FALSE +#define STM32_HSE32_ENABLED TRUE #define STM32_LSE_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M @@ -79,7 +80,7 @@ #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_RTCSEL STM32_RTCSEL_LSI diff --git a/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h index 2187d2637..0765f37bd 100644 --- a/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -43,8 +43,9 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE +#define STM32_LSI1_ENABLED TRUE +#define STM32_LSI2_ENABLED FALSE +#define STM32_HSE32_ENABLED TRUE #define STM32_LSE_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M @@ -79,7 +80,7 @@ #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_RTCSEL STM32_RTCSEL_LSI diff --git a/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h index 82fcf5fee..857c9dc89 100644 --- a/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -43,8 +43,9 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE +#define STM32_LSI1_ENABLED TRUE +#define STM32_LSI2_ENABLED FALSE +#define STM32_HSE32_ENABLED TRUE #define STM32_LSE_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M @@ -79,7 +80,7 @@ #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_RTCSEL STM32_RTCSEL_LSI diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32wb55cg_nucleo48/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32wb55cg_nucleo48/mcuconf.h index 68b818622..3c7f166dd 100644 --- a/testhal/STM32/multi/USB_CDC/cfg/stm32wb55cg_nucleo48/mcuconf.h +++ b/testhal/STM32/multi/USB_CDC/cfg/stm32wb55cg_nucleo48/mcuconf.h @@ -43,8 +43,9 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE -#define STM32_LSI_ENABLED FALSE -#define STM32_HSE_ENABLED FALSE +#define STM32_LSI1_ENABLED FALSE +#define STM32_LSI2_ENABLED FALSE +#define STM32_HSE32_ENABLED FALSE #define STM32_LSE_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h index 68b818622..3c7f166dd 100644 --- a/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -43,8 +43,9 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE -#define STM32_LSI_ENABLED FALSE -#define STM32_HSE_ENABLED FALSE +#define STM32_LSI1_ENABLED FALSE +#define STM32_LSI2_ENABLED FALSE +#define STM32_HSE32_ENABLED FALSE #define STM32_LSE_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M diff --git a/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl index 5393108bb..57798d0dd 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl @@ -54,8 +54,9 @@ #define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"} #define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"} #define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"} -#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"} -#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"} +#define STM32_LSI1_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"} +#define STM32_LSI2_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"} +#define STM32_HSE32_ENABLED ${doc.STM32_HSE32_ENABLED!"FALSE"} #define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"} #define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"} #define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"} @@ -90,7 +91,7 @@ #define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"} #define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"} #define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"} -#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1"} +#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1QCLK"} #define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"} #define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}