mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6392 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
b45a806747
commit
2b536049a9
|
@ -165,6 +165,7 @@
|
|||
#define SPC5_HAS_FLEXCAN0 TRUE
|
||||
#define SPC5_FLEXCAN0_PCTL 16
|
||||
#define SPC5_FLEXCAN0_MB 64
|
||||
#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
|
||||
|
@ -187,6 +188,7 @@
|
|||
#define SPC5_HAS_FLEXCAN1 TRUE
|
||||
#define SPC5_FLEXCAN1_PCTL 17
|
||||
#define SPC5_FLEXCAN1_MB 64
|
||||
#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
|
||||
|
@ -209,6 +211,7 @@
|
|||
#define SPC5_HAS_FLEXCAN2 TRUE
|
||||
#define SPC5_FLEXCAN2_PCTL 18
|
||||
#define SPC5_FLEXCAN2_MB 64
|
||||
#define SPC5_FLEXCAN2_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
|
||||
|
@ -231,6 +234,7 @@
|
|||
#define SPC5_HAS_FLEXCAN3 TRUE
|
||||
#define SPC5_FLEXCAN3_PCTL 19
|
||||
#define SPC5_FLEXCAN3_MB 64
|
||||
#define SPC5_FLEXCAN3_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
|
||||
|
@ -253,6 +257,7 @@
|
|||
#define SPC5_HAS_FLEXCAN4 TRUE
|
||||
#define SPC5_FLEXCAN4_PCTL 20
|
||||
#define SPC5_FLEXCAN4_MB 64
|
||||
#define SPC5_FLEXCAN4_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
|
||||
|
@ -275,6 +280,7 @@
|
|||
#define SPC5_HAS_FLEXCAN5 TRUE
|
||||
#define SPC5_FLEXCAN5_PCTL 21
|
||||
#define SPC5_FLEXCAN5_MB 64
|
||||
#define SPC5_FLEXCAN5_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
|
||||
|
|
|
@ -110,6 +110,28 @@
|
|||
#define SPC5_SIUL_NUM_PCRS 77
|
||||
#define SPC5_SIUL_NUM_PADSELS 63
|
||||
#define SPC5_SIUL_SYSTEM_PINS 32,33
|
||||
|
||||
/* FlexCAN attributes.*/
|
||||
#define SPC5_HAS_FLEXCAN0 TRUE
|
||||
#define SPC5_FLEXCAN0_PCTL 16
|
||||
#define SPC5_FLEXCAN0_MB 32
|
||||
#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
|
||||
#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
|
||||
#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
|
||||
/** @} */
|
||||
|
||||
#endif /* _SPC560D_REGISTRY_H_ */
|
||||
|
|
|
@ -282,6 +282,7 @@
|
|||
#define SPC5_HAS_FLEXCAN0 TRUE
|
||||
#define SPC5_FLEXCAN0_PCTL 16
|
||||
#define SPC5_FLEXCAN0_MB 32
|
||||
#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67
|
||||
|
|
|
@ -128,6 +128,7 @@
|
|||
/* FlexCAN attributes.*/
|
||||
#define SPC5_HAS_FLEXCAN0 TRUE
|
||||
#define SPC5_FLEXCAN0_MB 64
|
||||
#define SPC5_FLEXCAN0_SHARED_IRQ FALSE
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector152
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector153
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_HANDLER vector155
|
||||
|
@ -173,6 +174,7 @@
|
|||
|
||||
#define SPC5_HAS_FLEXCAN1 TRUE
|
||||
#define SPC5_FLEXCAN1_MB 32
|
||||
#define SPC5_FLEXCAN1_SHARED_IRQ FALSE
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector173
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector174
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_HANDLER vector176
|
||||
|
|
|
@ -169,6 +169,7 @@
|
|||
/* FlexCAN attributes.*/
|
||||
#define SPC5_HAS_FLEXCAN0 TRUE
|
||||
#define SPC5_FLEXCAN0_MB 64
|
||||
#define SPC5_FLEXCAN0_SHARED_IRQ FALSE
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector152
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector153
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_HANDLER vector155
|
||||
|
@ -214,6 +215,7 @@
|
|||
|
||||
#define SPC5_HAS_FLEXCAN1 TRUE
|
||||
#define SPC5_FLEXCAN1_MB 64
|
||||
#define SPC5_FLEXCAN1_SHARED_IRQ FALSE
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector173
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector174
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_HANDLER vector176
|
||||
|
@ -259,6 +261,7 @@
|
|||
|
||||
#define SPC5_HAS_FLEXCAN2 TRUE
|
||||
#define SPC5_FLEXCAN2_MB 64
|
||||
#define SPC5_FLEXCAN2_SHARED_IRQ FALSE
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector280
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector281
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_HANDLER vector283
|
||||
|
|
|
@ -236,6 +236,7 @@
|
|||
#define SPC5_HAS_FLEXCAN0 TRUE
|
||||
#define SPC5_FLEXCAN0_PCTL 16
|
||||
#define SPC5_FLEXCAN0_MB 32
|
||||
#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67
|
||||
|
@ -258,6 +259,7 @@
|
|||
#define SPC5_HAS_FLEXCAN1 TRUE
|
||||
#define SPC5_FLEXCAN1_PCTL 17
|
||||
#define SPC5_FLEXCAN1_MB 32
|
||||
#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_HANDLER vector87
|
||||
|
|
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue