mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6023 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
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/*
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Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
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This file is part of Nil RTOS.
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Nil RTOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Nil RTOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32F3xx/chtimer.c
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* @brief System timer code.
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*
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* @addtogroup STM32F3_TIMER
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*/
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#include "ch.h"
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#if CH_CFG_TIMEDELTA > 0
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/*===========================================================================*/
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/* Module local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module interrupt handlers. */
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/*===========================================================================*/
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/**
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* @brief TIM2 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector7C) {
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CH_IRQ_PROLOGUE();
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STM32F3_TIM2->SR = 0;
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chSysLockFromIsr();
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chSysTimerHandlerI();
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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/* Module exported functions. */
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/*===========================================================================*/
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#endif /* CH_CFG_TIMEDELTA > 0 */
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/** @} */
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@ -0,0 +1,193 @@
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/*
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Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
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This file is part of Nil RTOS.
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Nil RTOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Nil RTOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32F3xx/niltimer.h
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* @brief System timer header file.
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*
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* @addtogroup STM32F3_TIMER
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* @{
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*/
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#ifndef _CHTIMER_H_
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#define _CHTIMER_H_
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/*===========================================================================*/
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/* Module constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module data structures and types. */
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/*===========================================================================*/
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typedef struct {
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volatile uint16_t CR1;
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uint16_t _resvd0;
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volatile uint16_t CR2;
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uint16_t _resvd1;
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volatile uint16_t SMCR;
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uint16_t _resvd2;
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volatile uint16_t DIER;
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uint16_t _resvd3;
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volatile uint16_t SR;
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uint16_t _resvd4;
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volatile uint16_t EGR;
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uint16_t _resvd5;
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volatile uint16_t CCMR1;
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uint16_t _resvd6;
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volatile uint16_t CCMR2;
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uint16_t _resvd7;
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volatile uint16_t CCER;
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uint16_t _resvd8;
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volatile uint32_t CNT;
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volatile uint16_t PSC;
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uint16_t _resvd9;
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volatile uint32_t ARR;
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volatile uint16_t RCR;
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uint16_t _resvd10;
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volatile uint32_t CCR[4];
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volatile uint16_t BDTR;
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uint16_t _resvd11;
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volatile uint16_t DCR;
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uint16_t _resvd12;
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volatile uint16_t DMAR;
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uint16_t _resvd13;
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volatile uint16_t OR;
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uint16_t _resvd14;
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} stm32f0_tim_t;
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/*===========================================================================*/
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/* Module macros. */
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/*===========================================================================*/
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#define STM32F3_TIM2 ((stm32f0_tim_t *)0x40000000)
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module inline functions. */
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/*===========================================================================*/
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/**
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* @brief Timer unit initialization.
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*
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* @notapi
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*/
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static inline void port_timer_init(void) {
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STM32F3_TIM2->ARR = 0xFFFFFFFF;
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STM32F3_TIM2->CCMR1 = 0;
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STM32F3_TIM2->CCR[0] = 0;
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STM32F3_TIM2->DIER = 0;
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STM32F3_TIM2->CR2 = 0;
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STM32F3_TIM2->EGR = 1; /* UG, CNT initialized. */
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STM32F3_TIM2->CR1 = 1; /* CEN */
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}
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/**
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* @brief Returns the system time.
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*
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* @return The system time.
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*
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* @notapi
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*/
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static inline systime_t port_timer_get_time(void) {
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return STM32F3_TIM2->CNT;
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}
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/**
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* @brief Starts the alarm.
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* @note Makes sure that no spurious alarms are triggered after
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* this call.
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*
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* @param[in] time the time to be set for the first alarm
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*
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* @notapi
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*/
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static inline void port_timer_start_alarm(systime_t time) {
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chDbgAssert((STM32F3_TIM2->DIER & 2) == 0,
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"port_timer_start_alarm(), #1",
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"already started");
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STM32F3_TIM2->CCR[0] = time;
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STM32F3_TIM2->SR = 0;
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STM32F3_TIM2->DIER = 2; /* CC1IE */
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}
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/**
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* @brief Stops the alarm interrupt.
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*
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* @notapi
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*/
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static inline void port_timer_stop_alarm(void) {
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chDbgAssert((STM32F3_TIM2->DIER & 2) != 0,
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"port_timer_stop_alarm(), #1",
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"not started");
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STM32F3_TIM2->DIER = 0;
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}
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/**
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* @brief Sets the alarm time.
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*
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* @param[in] time the time to be set for the next alarm
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*
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* @notapi
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*/
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static inline void port_timer_set_alarm(systime_t time) {
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chDbgAssert((STM32F3_TIM2->DIER & 2) != 0,
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"port_timer_set_alarm(), #1",
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"not started");
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STM32F3_TIM2->CCR[0] = time;
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}
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/**
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* @brief Returns the current alarm time.
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*
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* @return The currently set alarm time.
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*
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* @notapi
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*/
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static inline systime_t port_timer_get_alarm(void) {
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chDbgAssert((STM32F3_TIM2->DIER & 2) != 0,
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"port_timer_get_alarm(), #1",
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"not started");
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return STM32F3_TIM2->CCR[0];
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}
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#endif /* _CHTIMER_H_ */
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/** @} */
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