mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5429 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
2f5f9bd380
commit
3133defc42
|
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@ -2,7 +2,7 @@
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Connection Failed Report from
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Basic UDE Target Interface, Version: 1.10.4
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created: 03/05/13, 10:41:20
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created: 03/14/13, 16:20:20
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----------------------------------------------------------
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@ -16,45 +16,41 @@ UDE version:
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Path: C:\Program Files\pls\UDE 4.0
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Target configuration file:
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C:\ChibiStudio\chibios\demos\PPC-SPC563M-GCC\UDE\stm_xpc563m64_minimodule_debug_jtag.cfg
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C:\ChibiStudio\chibios\demos\PPC-SPC564A-GCC\UDE\stm_xpc564a_minimodule_debug_jtag.cfg
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Error messages:
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PpcJtagTargIntf: Can't connect target !
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PpcJtagTargIntf: Failed to open communication channel !
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UAD2CommDev: Can't connect Universal Access Device 2 !
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Please check:
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- Power supply of UAD2
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- Communication cable to UAD2
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PpcJtagTargIntf: Failed to access JTAG debug module !
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UDEDebugServer: - serial no. -1 was suprised removed . To correct the situation, connect the communication device again and try to establish target communication.
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UDEDebugServer: Unable to establish connection . To correct the situation, check configuration file entries and try again.
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Settings:
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PortType: CommDev
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CommDevSel: PortType=USB,Type=UAD2
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JtagViaPod: y
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PortType: Default
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CommDevSel:
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JtagViaPod: n
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TargetPort: Default
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JtagTapNumber: 0
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JtagNumOfTaps: 1
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JtagNumIrBefore: 0
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JtagNumIrAfter: 0
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MaxJtagClk: 1000
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MaxJtagClk: 5000
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AdaptiveJtagPhaseShift: y
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JtagMuxPort: -1
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JtagMuxWaitTime: 5
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JtagIoType: Jtag
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EtksArbiterMode: 0
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ConnOption: Reset
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ConnOption: Default
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UseExtReset: y
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ResetWaitTime: 50
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HaltAfterReset: y
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ChangeJtagClk: -1
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ExecInitCmds: y
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InvalidateCache: n
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InvalidateCache: y
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ChangeMsr: n
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ChangeMsrValue: 0x00000000
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ResetPulseLen: 10
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InitScript Script:
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// TLB invalidate
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SETSPR 0x3F4 0x2 0xFFFFFFFF
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// select TLB 1
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SETSPR 0x274 0x10000108 0xFFFFFFFF
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@ -82,9 +78,21 @@ Settings:
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// programm internal SRAM
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// programm external memory
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// TLB 1, entry 2
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SETSPR 0x270 0x10020000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=16MB
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SETSPR 0x271 0xC0000700 0xFFFFFFFF
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// effective page number 20000000
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SETSPR 0x272 0x20000020 0xFFFFFFFF
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// real page 20000000, UX,SX,UW,SW,UR,SR
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SETSPR 0x273 0x2000003F 0xFFFFFFFF
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// programm internal SRAM
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// TLB 1, entry 3
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SETSPR 0x270 0x10030000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=256k
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SETSPR 0x271 0xC0000400 0xFFFFFFFF
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// effective page number 40000000, I
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@ -96,7 +104,7 @@ Settings:
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// programm peripheral A modules
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// TLB 1, entry 4
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SETSPR 0x270 0x10030000 0xFFFFFFFF
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SETSPR 0x270 0x10040000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=1MB
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SETSPR 0x271 0xC0000500 0xFFFFFFFF
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// effective page number C3F00000, I
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@ -106,22 +114,24 @@ Settings:
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// cache invalidate
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SETSPR 0x3F3 0x00000003 0x00000003
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SETSPR 0x3F3 0x00000000 0x00000003
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// setup IVOPR
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// points to internal memory at 0x40000000
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SETSPR 0x3F 0x40000000 0xFFFFFFFF
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// MMU data error vector offset
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SETSPR 0x19D 0x0 0xFFFFFFFF
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// MMU instruction error vector offset
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// setup clock to 80MHz
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//SET FMPLL_SYNCR 0x28000000 0xFFFFFFFF
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//WAIT 0x5
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// disable watchdog
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SET SWT_CR 0xFF00000A
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SET SWT_SR 0x0000C520
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SET SWT_SR 0x0000D928
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SET SWT_MCR 0xFF00000A
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// set NEXUS priority to above cpu instruction for runtime access
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//SET XBAR_MPR3 0x321
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// setup clock to 120MHz
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SET 0xC3F80008 0xF000003C 0xF00F00FF
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WAIT 0x2
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SET 0xC3F8000C 0x00000001 0x000000FF
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WAIT 0x5
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SimioAddr: g_JtagSimioAccess
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FreezeTimers: y
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@ -132,7 +142,7 @@ Settings:
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ExecOnHaltCmds: n
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ExecOnHaltCmdsWhileHalted: n
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OnHaltScript Script:
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Script is empty
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EnableProgramTimeMeasurement: n
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TimerForPTM: Default
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DefUserStreamChannel: 0
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@ -142,12 +152,12 @@ Settings:
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UseRestartWhileRunningHandling: n
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UseNexus: y
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DoSramInit: y
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ForceCacheFlush: n
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ForceCacheFlush: y
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IgnoreLockedLines: n
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HandleWdtBug: n
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ForceEndOfReset: n
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UseHwResetMode: y
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HwResetMode: Execute
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UseHwResetMode: n
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HwResetMode: Simulate
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HandleNexusAccessBug: n
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UseMasterNexusIfResetState: y
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UseLocalAddressTranslation: y
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@ -155,7 +165,7 @@ Settings:
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InitSramOnlyWhenNotInitialized: n
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InvalidTlbOnReset: y
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DoNotEnableTrapSwBrp: n
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AllowResetOnCheck: n
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AllowResetOnCheck: y
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BootPasswd0: 0xFEEDFACE
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BootPasswd1: 0xCAFEBEEF
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BootPasswd2: 0xFFFFFFFF
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@ -171,21 +181,21 @@ Settings:
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JTAG target infos:
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JTAG-ID: 0x00000000
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UsedJtagClk: 0 kHz
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ExtVoltage: 0.0 V
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IntVoltageUsed: n
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ExtVoltage: 3276.7 V
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IntVoltageUsed: y
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Target infos:
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CoreName: Core
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FullCoreName: Controller0.Core
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ExtClock: 12000000
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IntClock: 80000000
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ExtClock: 8000000
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IntClock: 120000000
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SysClock: 0
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HasNexus: n
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BigEndian: n
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CanSimio: n
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CanPhysicalAccess: n
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HasSpe: n
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NumOfSimioChannels: 0
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NumOfSimioChannels: 2157080748
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JtagId: 0x00000000
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IsEarlyStep: n
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IsMaster: y
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@ -220,7 +230,7 @@ Target infos:
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Has Data Value comparators: y
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Reset Mode: 0x00000002
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STM timer base address: 0xFFF3C000
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MC_ME base address: 0x00000000
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MC_ME base address: 0xC3FDC000
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Core in Lockstep mode: n
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Core in DPM mode: n
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Core is HSM: n
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@ -246,15 +256,23 @@ Target infos:
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InactiveAfterReset: n
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Communication device:
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Type/Firmware:
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Serial Number: 0
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Type/Firmware: UAD2
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Serial Number: 326060
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Communication protocol handler:
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LastCmd: 0x0000
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LastResult: 0x0000
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ExpBytes: 0 (0x0000)
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RetBytes: 0 (0x0000)
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LastTimeout: 0
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LastCmd: 0x0410
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LastResult: 0xC023
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ExpBytes: 576 (0x0240)
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RetBytes: 576 (0x0240)
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LastTimeout: 120020
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Protocol diagnostic output:
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Diagnostic output invalid !
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LastJtagApiAddr: 0x00000000
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LastJtagApiSpr: 0x00000000
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LastJtagApiDcr: 0x00000000
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LastJtagApiError: 0x00000000
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LastJtagApiStatus: 0x00000000
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JtagApiErrorLine: 3913
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JtagApiAddInfo0: 0x00000000
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JtagApiAddInfo1: 0x00000000
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ProtErrorLine: 926
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File diff suppressed because one or more lines are too long
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@ -1,183 +0,0 @@
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[Main]
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Signature=UDE_TARGINFO_2.0
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Description=STM XPC563M Mini Module with SPC563M64 1.5M (Jtag)
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Description1=MMU preinitialized, memory mapping 1:1, VLE enabled for SRAM and Flash
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Description2=PLL set for 80MHz
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Description3=FLASH programming prepared but not enabled
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Description4=Write Filter for BAM Module
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MCUs=Controller0
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Architecture=PowerPC
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Vendor=STM
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Board=XPC563M Mini Module
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[Controller0]
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Family=PowerPC
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Type=SPC563M64
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Enabled=1
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IntClock=80000
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MemDevs=BAMWriteFilter
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ExtClock=12000
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[Controller0.Core]
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Protocol=PPCJTAG
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Enabled=1
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[Controller0.Core.LoadedAddOn]
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UDEMemtool=1
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[Controller0.Core.PpcJtagTargIntf]
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PortType=UAD2
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ResetWaitTime=50
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MaxJtagClk=1000
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DoSramInit=1
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UseNexus=1
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AdaptiveJtagPhaseShift=1
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ConnOption=Reset
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ChangeJtagClk=-1
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HaltAfterReset=1
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SimioAddr=g_JtagSimioAccess
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FreezeTimers=1
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InvalidTlbOnReset=1
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InvalidateCache=0
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ForceCacheFlush=0
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IgnoreLockedLines=0
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ExecInitCmds=1
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JtagTapNumber=0
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JtagNumOfTaps=1
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JtagNumIrBefore=0
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JtagNumIrAfter=0
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SimioAddr=g_JtagSimioAccess
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FlushCache=0
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AllowMmuSetup=1
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UseExtReset=1
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HandleWdtBug=0
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ForceEndOfReset=0
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CommDevSel=PortType=USB,Type=UAD2
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JtagViaPod=1
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TargetPort=Default
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ChangeMsr=0
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ChangeMsrValue=0x0
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ExecOnStartCmds=0
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ExecOnHaltCmds=0
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EnableProgramTimeMeasurement=0
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UseHwResetMode=1
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HandleNexusAccessBug=0
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DoNotEnableTrapSwBrp=0
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AllowResetOnCheck=0
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BootPasswd0=0xFEEDFACE
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BootPasswd1=0xCAFEBEEF
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BootPasswd2=0xFFFFFFFF
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BootPasswd3=0xFFFFFFFF
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BootPasswd4=0xFFFFFFFF
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BootPasswd5=0xFFFFFFFF
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BootPasswd6=0xFFFFFFFF
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BootPasswd7=0xFFFFFFFF
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JtagIoType=Jtag
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ExecOnHaltCmdsWhileHalted=0
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TimerForPTM=Default
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AllowBreakOnUpdateBreakpoints=0
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ClearDebugStatusOnHalt=1
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HwResetMode=Execute
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UseMasterNexusIfResetState=1
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UseLocalAddressTranslation=1
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Use64BitNexus=0
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InitSramOnlyWhenNotInitialized=0
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DisableE2EECC=0
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[Controller0.BAMWriteFilter]
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Description=BAM WriteAccess Filter
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Range0Start=0xFFFFC000
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Range0Size=0x4000
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Enabled=1
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Handler=AccessFilter
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Mode=ReadOnly
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[Controller0.PFLASH0]
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Enabled=1
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EnableMemtoolByDefault=1
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|
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[Controller0.PFLASH1]
|
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Enabled=1
|
||||
EnableMemtoolByDefault=1
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|
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[Controller0.PFLASH2]
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Enabled=1
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EnableMemtoolByDefault=1
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[Controller0.Core.PpcJtagTargIntf.InitScript]
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|
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// TLB invalidate
|
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SETSPR 0x3F4 0x2 0xFFFFFFFF
|
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// select TLB 1
|
||||
SETSPR 0x274 0x10000108 0xFFFFFFFF
|
||||
|
||||
// programm peripheral B modules
|
||||
// TLB 1, entry 0
|
||||
SETSPR 0x270 0x10000000 0xFFFFFFFF
|
||||
// Valid, protect against invalidation, global entry, size=1MB
|
||||
SETSPR 0x271 0xC0000500 0xFFFFFFFF
|
||||
// effective page number FFF00000, I,G
|
||||
SETSPR 0x272 0xFFF0000A 0xFFFFFFFF
|
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// real page FFF00000, UX,SX,UW,SW,UR,SR
|
||||
SETSPR 0x273 0xFFF0003F 0xFFFFFFFF
|
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// execute TLB write instruction
|
||||
EXECOPCODE 0x7C0007A4
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||||
|
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// programm internal Flash, no cache because of flash
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// TLB 1, entry 1
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SETSPR 0x270 0x10010000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=16MB
|
||||
SETSPR 0x271 0xC0000700 0xFFFFFFFF
|
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// effective page number 00000000
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SETSPR 0x272 0x28 0xFFFFFFFF
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// real page 00000000, UX,SX,UW,SW,UR,SR
|
||||
SETSPR 0x273 0x3F 0xFFFFFFFF
|
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// execute TLB write instruction
|
||||
EXECOPCODE 0x7C0007A4
|
||||
|
||||
// programm internal SRAM
|
||||
// TLB 1, entry 2
|
||||
SETSPR 0x270 0x10020000 0xFFFFFFFF
|
||||
// Valid, protect against invalidation, global entry, size=256k
|
||||
SETSPR 0x271 0xC0000400 0xFFFFFFFF
|
||||
// effective page number 40000000, I
|
||||
SETSPR 0x272 0x40000028 0xFFFFFFFF
|
||||
// real page 0x40000028, UX,SX,UW,SW,UR,SR
|
||||
SETSPR 0x273 0x4000003F 0xFFFFFFFF
|
||||
// execute TLB write instruction
|
||||
EXECOPCODE 0x7C0007A4
|
||||
|
||||
// programm peripheral A modules
|
||||
// TLB 1, entry 4
|
||||
SETSPR 0x270 0x10030000 0xFFFFFFFF
|
||||
// Valid, protect against invalidation, global entry, size=1MB
|
||||
SETSPR 0x271 0xC0000500 0xFFFFFFFF
|
||||
// effective page number C3F00000, I
|
||||
SETSPR 0x272 0xC3F0000A 0xFFFFFFFF
|
||||
// real page C3F00000, UX,SX,UW,SW,UR,SR
|
||||
SETSPR 0x273 0xC3F0003F 0xFFFFFFFF
|
||||
// execute TLB write instruction
|
||||
EXECOPCODE 0x7C0007A4
|
||||
|
||||
// setup IVOPR
|
||||
// points to internal memory at 0x40000000
|
||||
SETSPR 0x3F 0x40000000 0xFFFFFFFF
|
||||
// MMU data error vector offset
|
||||
SETSPR 0x19D 0x0 0xFFFFFFFF
|
||||
// MMU instruction error vector offset
|
||||
|
||||
// setup clock to 80MHz
|
||||
//SET FMPLL_SYNCR 0x28000000 0xFFFFFFFF
|
||||
//WAIT 0x5
|
||||
|
||||
// disable watchdog
|
||||
SET SWT_CR 0xFF00000A
|
||||
|
||||
// set NEXUS priority to above cpu instruction for runtime access
|
||||
//SET XBAR_MPR3 0x321
|
||||
|
||||
[Controller0.Core.PpcJtagTargIntf.OnStartScript]
|
||||
|
||||
[Controller0.Core.PpcJtagTargIntf.OnHaltScript]
|
||||
|
|
@ -52,29 +52,31 @@ void hal_lld_init(void) {
|
|||
extern void _vectors(void);
|
||||
uint32_t n;
|
||||
|
||||
#if 0
|
||||
/* FLASH wait states and prefetching setup.*/
|
||||
CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
|
||||
CFLASH0.BIUCR2.R = 0;
|
||||
CFLASH0.PFCR3.R = 0;
|
||||
FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
|
||||
FLASH_A.BIUCR2.R = 0;
|
||||
FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
|
||||
FLASH_B.BIUCR2.R = 0;
|
||||
|
||||
/* Optimal crossbar settings. The DMA priority is placed above the CPU
|
||||
priority in order to not starve I/O activities while the CPU is
|
||||
executing tight loops (FLASH and SRAM slave ports only).
|
||||
The SRAM is parked on the load/store port, for some unknown reason it
|
||||
/* The SRAM is parked on the load/store port, for some unknown reason it
|
||||
is defaulted on the instructions port and this kills performance.*/
|
||||
XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/
|
||||
XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities:
|
||||
eDMA (1): 0 (highest)
|
||||
XBAR.SGPCR2.B.PARK = 1; /* RAM slave on load/store port.*/
|
||||
|
||||
/* The DMA priority is placed above the CPU priority in order to not
|
||||
starve I/O activities while the CPU is executing tight loops (FLASH
|
||||
and SRAM slave ports only).*/
|
||||
XBAR.MPR0.R = 0x34000021; /* Flash slave port priorities:
|
||||
eDMA (4): 0 (highest)
|
||||
Core Instructions (0): 1
|
||||
Undocumented (2): 2
|
||||
Core Data (4): 3 */
|
||||
XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities:
|
||||
eDMA (1): 0 (highest)
|
||||
Core Data (1): 2
|
||||
EBI (7): 3
|
||||
Flexray (6): 4 */
|
||||
XBAR.MPR2.R = 0x34000021; /* SRAM slave port priorities:
|
||||
eDMA (4): 0 (highest)
|
||||
Core Instructions (0): 1
|
||||
Undocumented (2): 2
|
||||
Core Data (4): 3 */
|
||||
#endif
|
||||
Core Data (1): 2
|
||||
EBI (7): 3
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||||
FlexRay (6): 4 */
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/* Downcounter timer initialized for system tick use, TB enabled for debug
|
||||
and measurements.*/
|
||||
|
|
|
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Loading…
Reference in New Issue