mirror of https://github.com/rusefi/ChibiOS.git
Still WIP.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15640 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
caec54337b
commit
3565192a5d
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@ -0,0 +1,646 @@
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/*
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ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
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2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation version 3 of the License.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMvx-M-SB/chcore.h
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* @brief ARMvx-M-SB port macros and structures.
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*
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* @addtogroup ARMVXM_SB_CORE
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* @{
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*/
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#ifndef CHCORE_H
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#define CHCORE_H
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/*===========================================================================*/
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/* Module constants. */
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/*===========================================================================*/
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/* The following code is not processed when the file is included from an
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asm module because those intrinsic macros are not necessarily defined
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by the assembler too.*/
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#if !defined(_FROM_ASM_)
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/**
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* @brief Compiler name and version.
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*/
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#if defined(__GNUC__) || defined(__DOXYGEN__)
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#define PORT_COMPILER_NAME "GCC " __VERSION__
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#elif defined(__ICCARM__)
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#define PORT_COMPILER_NAME "IAR"
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#error "unsupported compiler"
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#elif defined(__CC_ARM)
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#define PORT_COMPILER_NAME "RVCT"
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#error "unsupported compiler"
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#else
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#error "unsupported compiler"
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#endif
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#endif /* !defined(_FROM_ASM_) */
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/** @} */
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/**
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* @name Port Capabilities and Constants
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* @{
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*/
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/**
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* @brief This port supports a realtime counter.
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*/
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#define PORT_SUPPORTS_RT TRUE
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/**
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* @brief Natural alignment constant.
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* @note It is the minimum alignment for pointer-size variables.
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*/
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#define PORT_NATURAL_ALIGN sizeof (void *)
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/**
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* @brief Stack alignment constant.
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* @note It is the alignment required for the stack pointer.
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*/
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#define PORT_STACK_ALIGN sizeof (stkalign_t)
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/**
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* @brief Working Areas alignment constant.
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* @note It is the alignment to be enforced for thread working areas.
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*/
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#define PORT_WORKING_AREA_ALIGN 8U
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/** @} */
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/**
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* @name Architecture
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* @{
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*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define PORT_ARCHITECTURE_ARM
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/**
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* @brief Macro defining the specific ARM architecture.
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*/
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#define PORT_ARCHITECTURE_ARM_VXM_SB
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/**
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* @brief Name of the implemented architecture.
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*/
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#define PORT_ARCHITECTURE_NAME "ARMvx-M-SB"
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/**
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* @brief Name of the architecture variant.
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*/
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#define PORT_CORE_VARIANT_NAME "Cortex-M generic"
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/**
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* @brief Port-specific information string.
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*/
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#define PORT_INFO "Sandboxed kernel mode"
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/** @} */
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Stack size for the system idle thread.
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* @details This size depends on the idle thread implementation, usually
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* the idle thread should take no more space than those reserved
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* by @p PORT_INT_REQUIRED_STACK.
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* @note In this port it is set to 64 because the idle thread does have
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* a stack frame when compiling without optimizations. You may
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* reduce this value to zero when compiling with optimizations.
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*/
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#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
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#define PORT_IDLE_THREAD_STACK_SIZE 64
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#endif
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/**
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* @brief Per-thread stack overhead for interrupts servicing.
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* @details This constant is used in the calculation of the correct working
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* area size.
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* @note The exact value depends on stack usage of your VSRs and compiler
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* options.
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*/
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#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
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#define PORT_INT_REQUIRED_STACK 256
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* The following code is not processed when the file is included from an
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asm module.*/
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#if !defined(_FROM_ASM_)
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/*===========================================================================*/
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/* Module data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during a
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* preemption-capable interrupt handler.
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* @note It is implemented to match the Cortex-Mx exception context.
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*/
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struct port_extctx {
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r12;
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uint32_t lr_thd;
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uint32_t pc;
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uint32_t xpsr;
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#if CORTEX_USE_FPU
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uint32_t s0;
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uint32_t s1;
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uint32_t s2;
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uint32_t s3;
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uint32_t s4;
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uint32_t s5;
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uint32_t s6;
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uint32_t s7;
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uint32_t s8;
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uint32_t s9;
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uint32_t s10;
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uint32_t s11;
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uint32_t s12;
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uint32_t s13;
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uint32_t s14;
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uint32_t s15;
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uint32_t fpscr;
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uint32_t reserved;
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#endif /* CORTEX_USE_FPU */
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};
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switch.
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*/
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struct port_intctx {
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#if CORTEX_USE_FPU
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uint32_t s16;
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uint32_t s17;
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uint32_t s18;
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uint32_t s19;
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uint32_t s20;
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uint32_t s21;
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uint32_t s22;
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uint32_t s23;
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uint32_t s24;
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uint32_t s25;
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uint32_t s26;
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uint32_t s27;
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uint32_t s28;
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uint32_t s29;
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uint32_t s30;
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uint32_t s31;
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#endif /* CORTEX_USE_FPU */
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uint32_t r4;
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uint32_t r5;
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uint32_t r6;
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uint32_t r7;
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uint32_t r8;
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uint32_t r9;
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uint32_t r10;
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uint32_t r11;
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uint32_t lr;
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};
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/**
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* @brief Platform dependent part of the @p thread_t structure.
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* @details In this port the structure just holds a pointer to the
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* @p port_intctx structure representing the stack pointer
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* at context switch time.
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*/
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struct port_context {
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struct port_intctx *sp;
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};
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#endif /* !defined(_FROM_ASM_) */
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/*===========================================================================*/
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/* Module macros. */
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/*===========================================================================*/
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/**
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* @brief Priority level verification macro.
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*/
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#define PORT_IRQ_IS_VALID_PRIORITY(n) false
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/**
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* @brief Priority level verification macro.
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*/
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#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) false
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/**
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* @brief Optimized thread function declaration macro.
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*/
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#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
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/* By default threads have no syscall context information.*/
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#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__)
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#define __PORT_SETUP_CONTEXT_SYSCALL(tp, wtop) \
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(tp)->ctx.syscall.psp = (uint32_t)(wtop); \
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(tp)->ctx.syscall.p = NULL;
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#else
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#define __PORT_SETUP_CONTEXT_SYSCALL(tp, wtop)
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#endif
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/* By default threads have all regions disabled.*/
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#if (PORT_SWITCHED_REGIONS_NUMBER == 0) || defined(__DOXYGEN__)
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#define __PORT_SETUP_CONTEXT_MPU(tp)
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#elif (PORT_SWITCHED_REGIONS_NUMBER == 1) || defined(__DOXYGEN__)
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#define __PORT_SETUP_CONTEXT_MPU(tp) \
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(tp)->ctx.sp->regions[0].rbar = 0U; \
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(tp)->ctx.sp->regions[0].rasr = 0U
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#elif (PORT_SWITCHED_REGIONS_NUMBER == 2) || defined(__DOXYGEN__)
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#define __PORT_SETUP_CONTEXT_MPU(tp) \
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(tp)->ctx.sp->regions[0].rbar = 0U; \
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(tp)->ctx.sp->regions[0].rasr = 0U; \
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(tp)->ctx.sp->regions[1].rbar = 0U; \
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(tp)->ctx.sp->regions[1].rasr = 0U
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#elif (PORT_SWITCHED_REGIONS_NUMBER == 3) || defined(__DOXYGEN__)
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#define __PORT_SETUP_CONTEXT_MPU(tp) \
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(tp)->ctx.sp->regions[0].rbar = 0U; \
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(tp)->ctx.sp->regions[0].rasr = 0U; \
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(tp)->ctx.sp->regions[1].rbar = 0U; \
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(tp)->ctx.sp->regions[1].rasr = 0U; \
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(tp)->ctx.sp->regions[2].rbar = 0U; \
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(tp)->ctx.sp->regions[2].rasr = 0U
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#elif (PORT_SWITCHED_REGIONS_NUMBER == 4) || defined(__DOXYGEN__)
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#define __PORT_SETUP_CONTEXT_MPU(tp) \
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(tp)->ctx.sp->regions[0].rbar = 0U; \
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(tp)->ctx.sp->regions[0].rasr = 0U; \
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(tp)->ctx.sp->regions[1].rbar = 0U; \
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(tp)->ctx.sp->regions[1].rasr = 0U; \
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(tp)->ctx.sp->regions[2].rbar = 0U; \
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(tp)->ctx.sp->regions[2].rasr = 0U; \
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(tp)->ctx.sp->regions[3].rbar = 0U; \
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(tp)->ctx.sp->regions[3].rasr = 0U
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#else
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/* Note, checked above.*/
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#endif
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/**
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* @brief Platform dependent part of the @p chThdCreateI() API.
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* @details This code usually setup the context switching frame represented
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* by an @p port_intctx structure.
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*/
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) do { \
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(tp)->ctx.sp = (struct port_intctx *)(void *) \
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((uint8_t *)(wtop) - sizeof (struct port_intctx)); \
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(tp)->ctx.sp->r4 = (uint32_t)(pf); \
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(tp)->ctx.sp->r5 = (uint32_t)(arg); \
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(tp)->ctx.sp->lr = (uint32_t)__port_thread_start; \
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__PORT_SETUP_CONTEXT_MPU(tp); \
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__PORT_SETUP_CONTEXT_SYSCALL(tp, wtop); \
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} while (false)
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|
||||
/**
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||||
* @brief Context switch area size.
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||||
*/
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#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__)
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#define PORT_WA_CTX_SIZE (sizeof (struct port_intctx) + \
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sizeof (struct port_extctx))
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#else
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#define PORT_WA_CTX_SIZE (sizeof (struct port_intctx) + \
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sizeof (struct port_extctx) + \
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||||
sizeof (struct port_extctx))
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||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Computes the thread working area global size.
|
||||
* @note There is no need to perform alignments in this macro.
|
||||
*/
|
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#define PORT_WA_SIZE(n) ((size_t)PORT_GUARD_PAGE_SIZE + \
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(size_t)PORT_WA_CTX_SIZE + \
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(size_t)(n) + \
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(size_t)PORT_INT_REQUIRED_STACK)
|
||||
|
||||
/**
|
||||
* @brief Static working area allocation.
|
||||
* @details This macro is used to allocate a static thread working area
|
||||
* aligned as both position and size.
|
||||
*
|
||||
* @param[in] s the name to be assigned to the stack array
|
||||
* @param[in] n the stack size to be assigned to the thread
|
||||
*/
|
||||
#if (PORT_ENABLE_GUARD_PAGES == FALSE) || defined(__DOXYGEN__)
|
||||
#define PORT_WORKING_AREA(s, n) \
|
||||
stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
|
||||
|
||||
#else
|
||||
#define PORT_WORKING_AREA(s, n) \
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||||
ALIGNED_VAR(32) stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief IRQ prologue code.
|
||||
* @details This macro must be inserted at the start of all IRQ handlers
|
||||
* enabled to invoke system APIs.
|
||||
*/
|
||||
#define PORT_IRQ_PROLOGUE()
|
||||
|
||||
/**
|
||||
* @brief IRQ epilogue code.
|
||||
* @details This macro must be inserted at the end of all IRQ handlers
|
||||
* enabled to invoke system APIs.
|
||||
*/
|
||||
#define PORT_IRQ_EPILOGUE() __port_irq_epilogue()
|
||||
|
||||
/**
|
||||
* @brief IRQ handler function declaration.
|
||||
* @note @p id can be a function name or a vector number depending on the
|
||||
* port implementation.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define PORT_IRQ_HANDLER(id) extern "C" void id(void)
|
||||
|
||||
#else
|
||||
#define PORT_IRQ_HANDLER(id) void id(void)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Fast IRQ handler function declaration.
|
||||
* @note @p id can be a function name or a vector number depending on the
|
||||
* port implementation.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define PORT_FAST_IRQ_HANDLER(id) extern "C" void id(void)
|
||||
|
||||
#else
|
||||
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Performs a context switch between two threads.
|
||||
* @details This is the most critical code in any port, this function
|
||||
* is responsible for the context switch between 2 threads.
|
||||
* @note The implementation of this code affects <b>directly</b> the context
|
||||
* switch performance so optimize here as much as you can.
|
||||
*
|
||||
* @param[in] ntp the thread to be switched in
|
||||
* @param[in] otp the thread to be switched out
|
||||
*/
|
||||
#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)
|
||||
#define port_switch(ntp, otp) __port_switch(ntp, otp)
|
||||
|
||||
#else
|
||||
#if PORT_ENABLE_GUARD_PAGES == FALSE
|
||||
#define port_switch(ntp, otp) do { \
|
||||
struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
|
||||
if ((stkalign_t *)(void *)(r13 - 1) < (otp)->wabase) { \
|
||||
chSysHalt("stack overflow"); \
|
||||
} \
|
||||
__port_switch(ntp, otp); \
|
||||
} while (false)
|
||||
|
||||
#else
|
||||
#define port_switch(ntp, otp) do { \
|
||||
__port_switch(ntp, otp); \
|
||||
\
|
||||
/* Setting up the guard page for the switched-in thread.*/ \
|
||||
mpuSetRegionAddress(PORT_USE_GUARD_MPU_REGION, \
|
||||
chThdGetSelfX()->wabase); \
|
||||
} while (false)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void port_init(os_instance_t *oip);
|
||||
void __port_irq_epilogue(void);
|
||||
void __port_switch(thread_t *ntp, thread_t *otp);
|
||||
void __port_thread_start(void);
|
||||
void __port_switch_from_isr(void);
|
||||
void __port_exit_from_isr(void);
|
||||
#if PORT_USE_SYSCALL == TRUE
|
||||
void port_unprivileged_jump(uint32_t pc, uint32_t psp);
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Returns a word encoding the current interrupts status.
|
||||
*
|
||||
* @return The interrupts status.
|
||||
*/
|
||||
__STATIC_FORCEINLINE syssts_t port_get_irq_status(void) {
|
||||
syssts_t sts;
|
||||
|
||||
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
|
||||
sts = (syssts_t)__get_BASEPRI();
|
||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
sts = (syssts_t)__get_PRIMASK();
|
||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
return sts;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks the interrupt status.
|
||||
*
|
||||
* @param[in] sts the interrupt status word
|
||||
*
|
||||
* @return The interrupt status.
|
||||
* @retval false the word specified a disabled interrupts status.
|
||||
* @retval true the word specified an enabled interrupts status.
|
||||
*/
|
||||
__STATIC_FORCEINLINE bool port_irq_enabled(syssts_t sts) {
|
||||
|
||||
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
|
||||
return sts == (syssts_t)CORTEX_BASEPRI_DISABLED;
|
||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
return (sts & (syssts_t)1) == (syssts_t)0;
|
||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Determines the current execution context.
|
||||
*
|
||||
* @return The execution context.
|
||||
* @retval false not running in ISR mode.
|
||||
* @retval true running in ISR mode.
|
||||
*/
|
||||
__STATIC_FORCEINLINE bool port_is_isr_context(void) {
|
||||
|
||||
return (bool)((__get_IPSR() & 0x1FFU) != 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Kernel-lock action.
|
||||
* @details In this port this function raises the base priority to kernel
|
||||
* level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_lock(void) {
|
||||
|
||||
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
|
||||
#if defined(__CM7_REV)
|
||||
#if __CM7_REV <= 1
|
||||
__disable_irq();
|
||||
#endif
|
||||
#endif
|
||||
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
|
||||
#if defined(__CM7_REV)
|
||||
#if __CM7_REV <= 1
|
||||
__enable_irq();
|
||||
#endif
|
||||
#endif
|
||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
__disable_irq();
|
||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Kernel-unlock action.
|
||||
* @details In this port this function lowers the base priority to user
|
||||
* level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_unlock(void) {
|
||||
|
||||
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
|
||||
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
|
||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
__enable_irq();
|
||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Kernel-lock action from an interrupt handler.
|
||||
* @details In this port this function raises the base priority to kernel
|
||||
* level.
|
||||
* @note Same as @p port_lock() in this port.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_lock_from_isr(void) {
|
||||
|
||||
port_lock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Kernel-unlock action from an interrupt handler.
|
||||
* @details In this port this function lowers the base priority to user
|
||||
* level.
|
||||
* @note Same as @p port_unlock() in this port.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_unlock_from_isr(void) {
|
||||
|
||||
port_unlock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables all the interrupt sources.
|
||||
* @note In this port it disables all the interrupt sources by raising
|
||||
* the priority mask to level 0.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_disable(void) {
|
||||
|
||||
__disable_irq();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the interrupt sources below kernel-level priority.
|
||||
* @note Interrupt sources above kernel level remains enabled.
|
||||
* @note In this port it raises/lowers the base priority to kernel level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_suspend(void) {
|
||||
|
||||
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
|
||||
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
|
||||
__enable_irq();
|
||||
#else
|
||||
__disable_irq();
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables all the interrupt sources.
|
||||
* @note In this port it lowers the base priority to user level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_enable(void) {
|
||||
|
||||
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
|
||||
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
|
||||
#endif
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters an architecture-dependent IRQ-waiting mode.
|
||||
* @details The function is meant to return when an interrupt becomes pending.
|
||||
* The simplest implementation is an empty function or macro but this
|
||||
* would not take advantage of architecture-specific power saving
|
||||
* modes.
|
||||
* @note Implemented as an inlined @p WFI instruction.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void port_wait_for_interrupt(void) {
|
||||
|
||||
#if CORTEX_ENABLE_WFI_IDLE == TRUE
|
||||
__WFI();
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current value of the realtime counter.
|
||||
*
|
||||
* @return The realtime counter value.
|
||||
*/
|
||||
__STATIC_FORCEINLINE rtcnt_t port_rt_get_counter_value(void) {
|
||||
|
||||
return DWT->CYCCNT;
|
||||
}
|
||||
|
||||
#endif /* !defined(_FROM_ASM_) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module late inclusions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
|
||||
#if CH_CFG_ST_TIMEDELTA > 0
|
||||
#include "chcore_timer.h"
|
||||
#endif /* CH_CFG_ST_TIMEDELTA > 0 */
|
||||
|
||||
#endif /* !defined(_FROM_ASM_) */
|
||||
|
||||
#endif /* CHCORE_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
|
||||
2015,2016,2017,2018,2019,2020,2021,2022 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation version 3 of the License.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file ARMvx-M-SB/compilers/GCC/chcoreasm.S
|
||||
* @brief ARMvx-M-SB port low level code.
|
||||
*
|
||||
* @addtogroup ARMVXM_SB_GCC_CORE
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
#define _FROM_ASM_
|
||||
#include "chlicense.h"
|
||||
#include "chconf.h"
|
||||
#include "chcore.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/*
|
||||
* RTOS-specific context offset.
|
||||
*/
|
||||
#if defined(_CHIBIOS_RT_CONF_)
|
||||
#define CONTEXT_OFFSET 12
|
||||
|
||||
#elif defined(_CHIBIOS_NIL_CONF_)
|
||||
#define CONTEXT_OFFSET 0
|
||||
|
||||
#else
|
||||
#error "invalid chconf.h"
|
||||
#endif
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
#if CORTEX_USE_FPU
|
||||
.fpu fpv4-sp-d16
|
||||
#else
|
||||
.fpu softvfp
|
||||
#endif
|
||||
|
||||
.thumb
|
||||
.text
|
||||
|
||||
/*--------------------------------------------------------------------------*
|
||||
* Performs a context switch between two threads.
|
||||
*--------------------------------------------------------------------------*/
|
||||
.thumb_func
|
||||
.globl __port_switch
|
||||
__port_switch:
|
||||
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
|
||||
#if CORTEX_USE_FPU
|
||||
/* Saving FPU context.*/
|
||||
vpush {s16-s31}
|
||||
#endif
|
||||
|
||||
str sp, [r1, #CONTEXT_OFFSET]
|
||||
/* Workaround for ARM errata 752419, always applied
|
||||
because the sandboxed code could run on any core.*/
|
||||
ldr r3, [r0, #CONTEXT_OFFSET]
|
||||
mov sp, r3
|
||||
|
||||
#if CORTEX_USE_FPU
|
||||
/* Restoring FPU context.*/
|
||||
vpop {s16-s31}
|
||||
#endif
|
||||
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
|
||||
|
||||
/*--------------------------------------------------------------------------*
|
||||
* Start a thread by invoking its work function.
|
||||
*
|
||||
* Threads execution starts here, the code leaves the system critical zone
|
||||
* and then jumps into the thread function passed in register R4. The
|
||||
* register R5 contains the thread parameter. The function chThdExit() is
|
||||
* called on thread function return.
|
||||
*--------------------------------------------------------------------------*/
|
||||
.thumb_func
|
||||
.globl __port_thread_start
|
||||
__port_thread_start:
|
||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
||||
bl __dbg_check_unlock
|
||||
#endif
|
||||
#if CH_DBG_STATISTICS
|
||||
bl __stats_stop_measure_crit_thd
|
||||
#endif
|
||||
/* VRQs enabled.*/
|
||||
svc #250
|
||||
|
||||
mov r0, r5
|
||||
blx r4
|
||||
movs r0, #0 /* MSG_OK */
|
||||
bl chThdExit
|
||||
.zombies: b .zombies
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -65,7 +65,20 @@ __crt0_vrq:
|
|||
mov.w r2, #0
|
||||
str.w r2, [r1]
|
||||
|
||||
#if !defined(SB_VECTORS_NORTOS
|
||||
#if !defined(SB_VECTORS_NORTOS)
|
||||
#if CH_DBG_STATISTICS
|
||||
bl __stats_start_measure_crit_thd
|
||||
#endif
|
||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
||||
bl __dbg_check_lock
|
||||
#endif
|
||||
// bl chSchPreemption
|
||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
||||
bl __dbg_check_unlock
|
||||
#endif
|
||||
#if CH_DBG_STATISTICS
|
||||
bl __stats_stop_measure_crit_thd
|
||||
#endif
|
||||
#endif
|
||||
|
||||
svc #255
|
||||
|
|
|
|||
Loading…
Reference in New Issue