mirror of https://github.com/rusefi/ChibiOS.git
Improved PLLSAI for STM32F446xx and STM32F469xx/79xx.
Updated mcuconf.h for STM32F446xx and STM32F469xx/79xx. Added Clock 48 selector. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9575 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -45,9 +45,18 @@
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 336
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#define STM32_PLLN_VALUE 360
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 7
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SM_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIM_VALUE 4
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#define STM32_PLLSAIP_VALUE 8
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV4
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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@ -58,18 +67,9 @@
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#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SM_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIM_VALUE 4
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
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#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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@ -45,9 +45,18 @@
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 336
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#define STM32_PLLN_VALUE 360
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 7
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SM_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIM_VALUE 4
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#define STM32_PLLSAIP_VALUE 8
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV4
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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@ -58,18 +67,9 @@
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#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SM_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIM_VALUE 4
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
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#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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@ -48,6 +48,13 @@
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#define STM32_PLLN_VALUE 336
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 7
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV4
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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@ -58,13 +65,6 @@
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#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
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#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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@ -238,8 +238,8 @@ void stm32_clock_init(void) {
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#if STM32_ACTIVATE_PLLSAI
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/* PLLSAI activation.*/
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RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ |
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STM32_PLLSAIP;
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RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
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STM32_PLLSAIQ | STM32_PLLSAIM;
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RCC->CR |= RCC_CR_PLLSAION;
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@ -838,6 +838,16 @@
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#define STM32_PLLSAIN_VALUE 192
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#endif
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/**
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* @brief PLLSAIM value.
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* @note The allowed values are 2..63.
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* @note The default value is calculated for a 96MHz SAI clock
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* output from an external 8MHz HSE clock.
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*/
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#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLSAIM_VALUE 4
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#endif
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/**
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* @brief PLLSAIR value.
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* @note The allowed values are 2..7.
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@ -851,7 +861,7 @@
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* @note The allowed values are 2, 4, 6 and 8.
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*/
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#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIP_VALUE 8
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#endif
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/**
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#define STM32_ACTIVATE_PLLSAI FALSE
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#endif
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/**
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* @brief STM32_PLLSAIM field.
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*/
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#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0)
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#else
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#error "invalid STM32_PLLSAIM_VALUE value specified"
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#endif
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/**
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* @brief STM32_PLLSAIN field.
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*/
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@ -1917,7 +1937,7 @@
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#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
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#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
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#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
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#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
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#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
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#else
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#error "invalid source selected for PLL48CLK clock"
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#endif
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