From 3f47670d696dbcb4364df101d16a27b6db62f0a0 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 12 Jan 2021 08:42:33 +0000 Subject: [PATCH] More STM32WB-related patches. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14017 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h | 28 +- os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c | 2 +- os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h | 9 +- os/hal/ports/STM32/LLD/ADCv3/notes.txt | 2 +- os/hal/ports/STM32/LLD/USBv1/stm32_usb.h | 16 +- os/hal/ports/STM32/STM32WBxx/hal_lld.c | 6 +- os/hal/ports/STM32/STM32WBxx/hal_lld.h | 6 +- .../ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h | 28 +- .../RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h | 28 +- .../TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h | 28 +- .../UART/cfg/stm32wb55rg_nucleo68/mcuconf.h | 28 +- testhal/STM32/multi/USB_CDC/.cproject | 933 ++++++++++++------ testhal/STM32/multi/USB_CDC/Makefile | 2 +- .../cfg/stm32wb55rg_nucleo68/mcuconf.h | 34 +- .../conf/mcuconf_stm32wb55xx/mcuconf.h.ftl | 22 +- tools/ftl/schema/boards/stm32wbxx_board.xsd | 21 +- 16 files changed, 826 insertions(+), 367 deletions(-) diff --git a/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h b/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h index f034e714e..dd969d10a 100644 --- a/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h @@ -15,7 +15,7 @@ */ /* - * STM32WBxx drivers configuration. + * STM32WB55xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -42,6 +42,7 @@ #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE @@ -57,6 +58,8 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_C2HPRE STM32_C2HPRE_DIV2 +#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 #define STM32_STOPWUCK STM32_STOPWUCK_MSI #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 @@ -78,7 +81,6 @@ #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI /* @@ -102,6 +104,8 @@ #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 @@ -109,14 +113,14 @@ /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 /* * GPT driver system settings. @@ -173,6 +177,12 @@ #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + /* * SPI driver system settings. */ @@ -209,6 +219,14 @@ #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 12 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 12 + /* * WDG driver system settings. */ diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c index e2262d5ba..800e5b368 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c @@ -602,7 +602,7 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC1 rccEnableADC1(true); rccResetADC1(); - ADC1_COMMON->CCR = STM32_ADC_ADC1_CLOCK_MODE | ADC_DMA_MDMA; + ADC1_COMMON->CCR = STM32_ADC_ADC1_PRESC | STM32_ADC_ADC1_CLOCK_MODE; rccDisableADC1(); #endif #endif diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h index 5188e0c6b..46278c814 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h @@ -392,7 +392,14 @@ * @brief ADC1 clock source and mode. */ #if !defined(STM32_ADC_ADC1_CLOCK_MODE) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#endif + +/** + * @brief ADC1 clock prescaler. + */ +#if !defined(STM32_ADC_ADC1_PRESC) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 #endif #endif /* defined(STM32WBXX) */ diff --git a/os/hal/ports/STM32/LLD/ADCv3/notes.txt b/os/hal/ports/STM32/LLD/ADCv3/notes.txt index fbfe6c224..05544fbe7 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/notes.txt +++ b/os/hal/ports/STM32/LLD/ADCv3/notes.txt @@ -2,7 +2,7 @@ STM32 ADCv3 driver. Driver capability: -- Supports the STM32 "fast" ADC found on F3, L4, L4+ and G4 sub-families. +- Supports the STM32 "fast" ADC found on F3, L4, L4+, G4 and WB sub-families. The file registry must export: diff --git a/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h b/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h index 9a8595ead..37391ad9a 100644 --- a/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h +++ b/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h @@ -121,19 +121,23 @@ typedef struct { /** * @brief USB registers block numeric address. */ -#if defined(USB_BASE) || defined(__DOXYGEN__) -#define STM32_USB_BASE USB_BASE +#if defined(USB1_BASE) || defined(__DOXYGEN__) + #define STM32_USB_BASE USB1_BASE +#elif defined(USB_BASE) + #define STM32_USB_BASE USB_BASE #else -#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00) + #define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00) #endif /** * @brief USB RAM numeric address. */ -#if defined(USB_PMAADDR) || defined(__DOXYGEN__) -#define STM32_USBRAM_BASE USB_PMAADDR +#if defined(USB1_PMAADDR) || defined(__DOXYGEN__) + #define STM32_USBRAM_BASE USB1_PMAADDR +#elif defined(USB_PMAADDR) + #define STM32_USBRAM_BASE USB_PMAADDR #else -#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000) + #define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000) #endif /** diff --git a/os/hal/ports/STM32/STM32WBxx/hal_lld.c b/os/hal/ports/STM32/STM32WBxx/hal_lld.c index 21f130508..7405c28ea 100644 --- a/os/hal/ports/STM32/STM32WBxx/hal_lld.c +++ b/os/hal/ports/STM32/STM32WBxx/hal_lld.c @@ -179,8 +179,10 @@ void stm32_clock_init(void) { /* Core voltage setup.*/ PWR->CR1 = STM32_VOS; - while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */ - ; /* stable. */ + + /* Wait until regulator is stable. */ + while ((PWR->SR2 & PWR_SR2_VOSF) != 0) + ; #if STM32_HSI16_ENABLED /* HSI activation.*/ diff --git a/os/hal/ports/STM32/STM32WBxx/hal_lld.h b/os/hal/ports/STM32/STM32WBxx/hal_lld.h index 833656c4b..c981140b1 100644 --- a/os/hal/ports/STM32/STM32WBxx/hal_lld.h +++ b/os/hal/ports/STM32/STM32WBxx/hal_lld.h @@ -211,7 +211,7 @@ #define STM32_SHDHPRE_DIV5 (2 << 0) /**< SYSCLK divided by 5. */ #define STM32_SHDHPRE_DIV6 (5 << 0) /**< SYSCLK divided by 6. */ #define STM32_SHDHPRE_DIV8 (10 << 0) /**< SYSCLK divided by 8. */ -#define STM32_SHDHPRE_DIV10 (6 << 0) /**< SYSCLK divided by 10. */ +#define STM32_SHDHPRE_DIV10 (6 << 0) /**< SYSCLK divided by 10. */ #define STM32_SHDHPRE_DIV16 (11 << 0) /**< SYSCLK divided by 16. */ #define STM32_SHDHPRE_DIV32 (7 << 0) /**< SYSCLK divided by 32. */ #define STM32_SHDHPRE_DIV64 (12 << 0) /**< SYSCLK divided by 64. */ @@ -243,7 +243,7 @@ */ #define STM32_RFCSS_MASK (1 << 20) /**< RFCSS field mask. */ #define STM32_RFCSS_HSI16 (0 << 20) /**< HSI16 on HCLK5 and APB3. */ -#define STM32_RFCSS_HSEDIV2 (1 << 20) /**< HSE/2 on HCLK5 and APB3. */ +#define STM32_RFCSS_HSEDIV2 (1 << 20) /**< HSE/2 on HCLK5 and APB3. */ /** @} */ /** @@ -663,7 +663,7 @@ * @brief ADCSEL value (ADCs clock source). */ #if !defined(STM32_ADCSEL) || defined(__DOXYGEN__) -#define STM32_ADCSEL STM32_CLK48SEL_PLLSAI1 +#define STM32_ADCSEL STM32_ADCSEL_SYSCLK #endif /** diff --git a/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h index 79608b8f2..c76461bc6 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -15,7 +15,7 @@ */ /* - * STM32WBxx drivers configuration. + * STM32WB55xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -42,6 +42,7 @@ #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE @@ -57,6 +58,8 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_C2HPRE STM32_C2HPRE_DIV2 +#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 #define STM32_STOPWUCK STM32_STOPWUCK_MSI #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 @@ -78,7 +81,6 @@ #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI /* @@ -102,6 +104,8 @@ #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 @@ -109,16 +113,14 @@ /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE #define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 /* * GPT driver system settings. @@ -149,8 +151,6 @@ */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM16 FALSE -#define STM32_ICU_USE_TIM17 FALSE /* * PWM driver system settings. @@ -177,6 +177,12 @@ #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + /* * SPI driver system settings. */ @@ -213,6 +219,14 @@ #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 12 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 12 + /* * WDG driver system settings. */ diff --git a/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h index 0e09d96be..82259cf61 100644 --- a/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -15,7 +15,7 @@ */ /* - * STM32WBxx drivers configuration. + * STM32WB55xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -42,6 +42,7 @@ #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE @@ -57,6 +58,8 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_C2HPRE STM32_C2HPRE_DIV2 +#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 #define STM32_STOPWUCK STM32_STOPWUCK_MSI #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 @@ -78,7 +81,6 @@ #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI /* @@ -102,6 +104,8 @@ #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 @@ -109,16 +113,14 @@ /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE #define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 /* * GPT driver system settings. @@ -149,8 +151,6 @@ */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM16 FALSE -#define STM32_ICU_USE_TIM17 FALSE /* * PWM driver system settings. @@ -177,6 +177,12 @@ #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + /* * SPI driver system settings. */ @@ -213,6 +219,14 @@ #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 12 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 12 + /* * WDG driver system settings. */ diff --git a/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h index aa263cea7..5cf33b75f 100644 --- a/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -15,7 +15,7 @@ */ /* - * STM32WBxx drivers configuration. + * STM32WB55xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -42,6 +42,7 @@ #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE @@ -57,6 +58,8 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_C2HPRE STM32_C2HPRE_DIV2 +#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 #define STM32_STOPWUCK STM32_STOPWUCK_MSI #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 @@ -78,7 +81,6 @@ #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI /* @@ -102,6 +104,8 @@ #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 @@ -109,16 +113,14 @@ /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE #define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 /* * GPT driver system settings. @@ -149,8 +151,6 @@ */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM16 FALSE -#define STM32_ICU_USE_TIM17 FALSE /* * PWM driver system settings. @@ -177,6 +177,12 @@ #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + /* * SPI driver system settings. */ @@ -213,6 +219,14 @@ #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 12 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 12 + /* * WDG driver system settings. */ diff --git a/testhal/STM32/multi/UART/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/UART/cfg/stm32wb55rg_nucleo68/mcuconf.h index edd159b9d..1a433e542 100644 --- a/testhal/STM32/multi/UART/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/UART/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -15,7 +15,7 @@ */ /* - * STM32WBxx drivers configuration. + * STM32WB55xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -42,6 +42,7 @@ #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE @@ -57,6 +58,8 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_C2HPRE STM32_C2HPRE_DIV2 +#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 #define STM32_STOPWUCK STM32_STOPWUCK_MSI #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 @@ -78,7 +81,6 @@ #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI /* @@ -102,6 +104,8 @@ #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 #define STM32_IRQ_USART1_PRIORITY 12 #define STM32_IRQ_LPUART1_PRIORITY 12 @@ -109,16 +113,14 @@ /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE #define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 /* * GPT driver system settings. @@ -149,8 +151,6 @@ */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM16 FALSE -#define STM32_ICU_USE_TIM17 FALSE /* * PWM driver system settings. @@ -177,6 +177,12 @@ #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + /* * SPI driver system settings. */ @@ -213,6 +219,14 @@ #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 12 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 12 + /* * WDG driver system settings. */ diff --git a/testhal/STM32/multi/USB_CDC/.cproject b/testhal/STM32/multi/USB_CDC/.cproject index f9e087436..f7a7e32ae 100644 --- a/testhal/STM32/multi/USB_CDC/.cproject +++ b/testhal/STM32/multi/USB_CDC/.cproject @@ -1,289 +1,650 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32/multi/USB_CDC/Makefile b/testhal/STM32/multi/USB_CDC/Makefile index e47411c45..41a20fa5c 100644 --- a/testhal/STM32/multi/USB_CDC/Makefile +++ b/testhal/STM32/multi/USB_CDC/Makefile @@ -28,7 +28,7 @@ all: +@make --no-print-directory -f ./make/stm32h743_nucleo144.make all @echo ==================================================================== @echo - @echo === Building for STM32WB55RG_Nucleo64 ============================= + @echo === Building for STM32WB55RG_Nucleo68 ============================= +@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all @echo ==================================================================== @echo diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h index 5d9ff13c3..941767d09 100644 --- a/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h +++ b/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2020 Ilya Kharin + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /* - * STM32WBxx drivers configuration. + * STM32WB55xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -42,21 +42,24 @@ #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI16_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE +#define STM32_HSI48_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE #define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED FALSE -#define STM32_MSIPLL_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_MSI #define STM32_PLLM_VALUE 1 #define STM32_PLLN_VALUE 32 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 2 +#define STM32_PLLP_VALUE 5 +#define STM32_PLLQ_VALUE 4 #define STM32_PLLR_VALUE 2 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_C2HPRE STM32_C2HPRE_DIV2 +#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 #define STM32_STOPWUCK STM32_STOPWUCK_MSI #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 @@ -76,10 +79,9 @@ #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 -#define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 -#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_CLK48SEL STM32_CLK48SEL_HSI48 +#define STM32_ADCSEL STM32_ADCSEL_NOCLK +#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK /* * IRQ system settings. @@ -102,6 +104,8 @@ #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 @@ -109,7 +113,6 @@ /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) @@ -117,6 +120,7 @@ #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 /* * GPT driver system settings. @@ -173,6 +177,12 @@ #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + /* * SPI driver system settings. */ diff --git a/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl index eda6c18f5..65c6f6204 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl @@ -52,14 +52,14 @@ #define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"} #define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"} #define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"} -#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"} +#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"} +#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"} #define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"} #define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"} -#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"} +#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"} #define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"} #define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"} -#define STM32_MSISRANGE ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"} -#define STM32_SW ${doc.STM32_SW!"STM32_SW_HSE"} +#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"} #define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"} #define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"} #define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"32"} @@ -69,6 +69,8 @@ #define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"} #define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"} #define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"} +#define STM32_C2HPRE ${doc.STM32_C2HPRE!"STM32_C2HPRE_DIV2"} +#define STM32_SHDHPRE ${doc.STM32_SHDHPRE!"STM32_SHDHPRE_DIV1"} #define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"} #define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"} #define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"} @@ -90,7 +92,6 @@ #define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"} #define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1"} #define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"} -#define STM32_SWPMI1SEL ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"} #define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"} /* @@ -104,7 +105,8 @@ #define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"} #define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"} #define STM32_IRQ_EXTI16_31_33_PRIORITY ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"} -#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"} +#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"6"} +#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"} #define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"} #define STM32_IRQ_EXTI20_21_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"} @@ -122,16 +124,14 @@ /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"} #define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"} #define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"} #define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} #define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"} -#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"} -#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"} +#define STM32_ADC_ADC1_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_IRQ_PRIORITY!"5"} #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"} -#define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"} -#define STM32_ADC_ADC123_PRESC ${doc.STM32_ADC_ADC123_PRESC!"ADC_CCR_PRESC_DIV2"} +#define STM32_ADC_ADC1_CLOCK_MODE ${doc.STM32_ADC_ADC1_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"} +#define STM32_ADC_ADC1_PRESC ${doc.STM32_ADC_ADC1_PRESC!"ADC_CCR_PRESC_DIV2"} /* * GPT driver system settings. diff --git a/tools/ftl/schema/boards/stm32wbxx_board.xsd b/tools/ftl/schema/boards/stm32wbxx_board.xsd index 409c818dd..bf07a0ff8 100644 --- a/tools/ftl/schema/boards/stm32wbxx_board.xsd +++ b/tools/ftl/schema/boards/stm32wbxx_board.xsd @@ -20,15 +20,6 @@ - - - - - - - - - @@ -36,7 +27,17 @@ - + + + + + + + + + + +