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Fixed STM32WL STM32_SPI2S2SEL name, PLLQ source name and related mcuconf.h files. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14579 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
vrepetenko 2021-06-30 07:33:47 +00:00
parent a679c6009e
commit 419b8d208a
4 changed files with 50 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h
View File

@ -86,7 +86,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2SEL STM32_SPI2SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQ
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
@ -209,7 +209,7 @@
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
@ -224,6 +224,16 @@
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/

2
os/hal/ports/STM32/STM32WLxx/hal_lld.c
View File

@ -245,7 +245,7 @@ static void hal_lld_set_static_clocks(void) {
ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_LPTIM3SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C3SEL |
STM32_I2C2SEL | STM32_I2C1SEL | STM32_LPUART1SEL |
STM32_SPI2SEL | STM32_USART2SEL | STM32_USART1SEL;
STM32_SPI2S2SEL | STM32_USART2SEL | STM32_USART1SEL;
RCC->CCIPR = ccipr;
}

11
os/hal/ports/STM32/STM32WLxx/hal_lld.h
View File

@ -263,10 +263,10 @@
#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 source is HSI16. */
#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
#define STM32_SPI2SEL_MASK (3 << 8) /**< SPI2S2SEL mask. */
#define STM32_SPI2SEL_PCLK1 (1 << 8) /**< SPI2S source is PLLQCLK. */
#define STM32_SPI2SEL_HSI16 (2 << 8) /**< SPI2S source is HSI16. */
#define STM32_SPI2SEL_I2SCKIN (3 << 8) /**< SPI2S source is External Input.*/
#define STM32_SPI2S2SEL_MASK (3 << 8) /**< SPI2S2SEL mask. */
#define STM32_SPI2S2SEL_PLLQ (1 << 8) /**< SPI2S2 source is PLLQ. */
#define STM32_SPI2S2SEL_HSI16 (2 << 8) /**< SPI2S2 source is HSI16. */
#define STM32_SPI2S2SEL_I2SCKIN (3 << 8) /**< SPI2S2 source is External Input.*/
#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */
#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */
@ -1207,7 +1207,7 @@
* @brief STM32_PLLPEN field.
*/
#if (STM32_ADC1SEL == STM32_ADCSEL_PLLP) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLP) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLP) || \
defined(__DOXYGEN__)
#define STM32_PLLPEN (1 << 16)
#else
@ -1219,6 +1219,7 @@
*/
#if (STM32_MCOSEL == STM32_MCOSEL_PLLQ) || \
(STM32_RNGSEL == STM32_RNGSEL_PLLQ) || \
(STM32_SPI2S2SEL == STM32_SPI2S2SEL_PLLQ) || \
defined(__DOXYGEN__)
#define STM32_PLLQEN (1 << 24)
#else

49
testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -86,7 +86,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2SEL STM32_SPI2SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQ
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
@ -127,7 +127,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -144,8 +144,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -161,10 +161,10 @@
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
@ -211,16 +211,29 @@
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
@ -238,12 +251,12 @@
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 TRUE
#define STM32_UART_USE_LPUART1 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*