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STM32 support enhancements, some other fixes. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4313 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2012-06-21 16:25:11 +00:00
parent 8fb998f0a5
commit 43011f1886
62 changed files with 6028 additions and 829 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
demos/ARMCM0-STM32F051-DISCOVERY/mcuconf.h
View File

@ -59,6 +59,23 @@
#define STM32_USART1SW STM32_USART1SW_PCLK #define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
/* /*
* SERIAL driver system settings. * SERIAL driver system settings.
*/ */

2
demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

453
os/hal/platforms/STM32/ext_lld.c
View File

@ -31,6 +31,8 @@
#if HAL_USE_EXT || defined(__DOXYGEN__) #if HAL_USE_EXT || defined(__DOXYGEN__)
#include "ext_lld_isr.h"
/*===========================================================================*/ /*===========================================================================*/
/* Driver local definitions. */ /* Driver local definitions. */
/*===========================================================================*/ /*===========================================================================*/
@ -56,356 +58,6 @@ EXTDriver EXTD1;
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI0_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 0);
EXTD1.config->channels[0].cb(&EXTD1, 0);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI1_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 1);
EXTD1.config->channels[1].cb(&EXTD1, 1);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI2_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 2);
EXTD1.config->channels[2].cb(&EXTD1, 2);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI3_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 3);
EXTD1.config->channels[3].cb(&EXTD1, 3);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI4_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 4);
EXTD1.config->channels[4].cb(&EXTD1, 4);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
EXTI->PR = pr;
if (pr & (1 << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
if (pr & (1 << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
if (pr & (1 << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
if (pr & (1 << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
(1 << 15));
EXTI->PR = pr;
if (pr & (1 << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
if (pr & (1 << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
if (pr & (1 << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
if (pr & (1 << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
if (pr & (1 << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[16] interrupt handler (PVD).
*
* @isr
*/
CH_IRQ_HANDLER(PVD_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[17] interrupt handler (RTC).
*
* @isr
*/
CH_IRQ_HANDLER(RTCAlarm_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
CH_IRQ_EPILOGUE();
}
#if defined(STM32L1XX_MD)
/**
* @brief EXTI[18] interrupt handler (USB_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[19] interrupt handler (TAMPER_STAMP).
*
* @isr
*/
CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[20] interrupt handler (RTC_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 20);
EXTD1.config->channels[20].cb(&EXTD1, 20);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[21]...EXTI[22] interrupt handler (COMP).
*
* @isr
*/
CH_IRQ_HANDLER(COMP_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 21) | (1 << 22));
EXTI->PR = pr;
if (pr & (1 << 21))
EXTD1.config->channels[21].cb(&EXTD1, 21);
if (pr & (1 << 22))
EXTD1.config->channels[22].cb(&EXTD1, 22);
CH_IRQ_EPILOGUE();
}
#elif defined(STM32F2XX) || defined(STM32F4XX)
/**
* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[19] interrupt handler (ETH_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 20);
EXTD1.config->channels[20].cb(&EXTD1, 20);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[21] interrupt handler (TAMPER_STAMP).
*
* @isr
*/
CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 21);
EXTD1.config->channels[21].cb(&EXTD1, 21);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[22] interrupt handler (RTC_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 22);
EXTD1.config->channels[22].cb(&EXTD1, 22);
CH_IRQ_EPILOGUE();
}
#elif defined(STM32F10X_CL)
/**
* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[19] interrupt handler (ETH_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
CH_IRQ_EPILOGUE();
}
#else
/**
* @brief EXTI[18] interrupt handler (USB_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported functions. */ /* Driver exported functions. */
/*===========================================================================*/ /*===========================================================================*/
@ -431,63 +83,9 @@ void ext_lld_init(void) {
void ext_lld_start(EXTDriver *extp) { void ext_lld_start(EXTDriver *extp) {
unsigned i; unsigned i;
if (extp->state == EXT_STOP) { if (extp->state == EXT_STOP)
/* Clock activation.*/ ext_lld_exti_irq_enable();
nvicEnableVector(EXTI0_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
nvicEnableVector(EXTI1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
nvicEnableVector(EXTI2_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
nvicEnableVector(EXTI3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
nvicEnableVector(EXTI4_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
nvicEnableVector(EXTI9_5_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
nvicEnableVector(EXTI15_10_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
nvicEnableVector(RTC_Alarm_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
#if defined(STM32L1XX_MD)
/* EXTI vectors specific to STM32L1xx.*/
nvicEnableVector(USB_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
nvicEnableVector(TAMPER_STAMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
nvicEnableVector(RTC_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
nvicEnableVector(COMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
#elif defined(STM32F2XX) || defined(STM32F4XX)
/* EXTI vectors specific to STM32F2xx/STM32F4xx.*/
nvicEnableVector(OTG_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
nvicEnableVector(ETH_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
nvicEnableVector(OTG_HS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
nvicEnableVector(TAMP_STAMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
nvicEnableVector(RTC_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
#elif defined(STM32F10X_CL)
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
nvicEnableVector(OTG_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
nvicEnableVector(ETH_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
defined(STM32F10X_HD_VL)
/* EXTI vectors specific to STM32F1xx Value Line.*/
#else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
nvicEnableVector(USB_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
#endif
}
/* Configuration of automatic channels.*/ /* Configuration of automatic channels.*/
for (i = 0; i < EXT_MAX_CHANNELS; i++) for (i = 0; i < EXT_MAX_CHANNELS; i++)
if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
@ -505,41 +103,9 @@ void ext_lld_start(EXTDriver *extp) {
*/ */
void ext_lld_stop(EXTDriver *extp) { void ext_lld_stop(EXTDriver *extp) {
if (extp->state == EXT_ACTIVE) { if (extp->state == EXT_ACTIVE)
nvicDisableVector(EXTI0_IRQn); ext_lld_exti_irq_disable();
nvicDisableVector(EXTI1_IRQn);
nvicDisableVector(EXTI2_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_Alarm_IRQn);
#if defined(STM32L1XX_MD)
/* EXTI vectors specific to STM32L1xx.*/
nvicDisableVector(USB_FS_WKUP_IRQn);
nvicDisableVector(TAMPER_STAMP_IRQn);
nvicDisableVector(RTC_WKUP_IRQn);
nvicDisableVector(COMP_IRQn);
#elif defined(STM32F2XX) || defined(STM32F4XX)
/* EXTI vectors specific to STM32F2xx/STM32F4xx.*/
nvicDisableVector(OTG_FS_WKUP_IRQn);
nvicDisableVector(ETH_WKUP_IRQn);
nvicDisableVector(OTG_HS_WKUP_IRQn);
nvicDisableVector(TAMP_STAMP_IRQn);
nvicDisableVector(RTC_WKUP_IRQn);
#elif defined(STM32F10X_CL)
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
nvicDisableVector(OTG_FS_WKUP_IRQn);
nvicDisableVector(ETH_WKUP_IRQn);
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
defined(STM32F10X_HD_VL)
/* EXTI vectors specific to STM32F1xx Value Line.*/
#else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
nvicDisableVector(USB_FS_WKUP_IRQn);
#endif
}
EXTI->EMR = 0; EXTI->EMR = 0;
EXTI->IMR = 0; EXTI->IMR = 0;
EXTI->PR = EXT_CHANNELS_MASK; EXTI->PR = EXT_CHANNELS_MASK;
@ -583,7 +149,8 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
EXT_MODE_GPIO_MASK) >> EXT_MODE_GPIO_MASK) >>
EXT_MODE_GPIO_OFF) << ((channel & 3) * 4); EXT_MODE_GPIO_OFF) << ((channel & 3) * 4);
#if defined(STM32L1XX_MD) || defined(STM32F2XX) || defined(STM32F4XX) #if defined(STM32L1XX_MD) || defined(STM32F0XX) || defined(STM32F2XX) || \
defined(STM32F4XX)
SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port; SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port;
#else /* STM32F1XX */ #else /* STM32F1XX */
AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port; AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port;

103
os/hal/platforms/STM32/ext_lld.h
View File

@ -66,109 +66,6 @@
/* Driver pre-compile time settings. */ /* Driver pre-compile time settings. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI9..5 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI15..10 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI20 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI21 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI21_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI22 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI22_IRQ_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/ /*===========================================================================*/
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/

12
os/hal/platforms/STM32/gpt_lld.h
View File

@ -49,7 +49,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__) #if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)
#define STM32_GPT_USE_TIM1 TRUE #define STM32_GPT_USE_TIM1 FALSE
#endif #endif
/** /**
@ -58,7 +58,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__) #if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__)
#define STM32_GPT_USE_TIM2 TRUE #define STM32_GPT_USE_TIM2 FALSE
#endif #endif
/** /**
@ -67,7 +67,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__) #if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__)
#define STM32_GPT_USE_TIM3 TRUE #define STM32_GPT_USE_TIM3 FALSE
#endif #endif
/** /**
@ -76,7 +76,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__) #if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__)
#define STM32_GPT_USE_TIM4 TRUE #define STM32_GPT_USE_TIM4 FALSE
#endif #endif
/** /**
@ -85,7 +85,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__) #if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__)
#define STM32_GPT_USE_TIM5 TRUE #define STM32_GPT_USE_TIM5 FALSE
#endif #endif
/** /**
@ -94,7 +94,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__) #if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__)
#define STM32_GPT_USE_TIM8 TRUE #define STM32_GPT_USE_TIM8 FALSE
#endif #endif
/** /**

12
os/hal/platforms/STM32/icu_lld.h
View File

@ -49,7 +49,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__) #if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM1 TRUE #define STM32_ICU_USE_TIM1 FALSE
#endif #endif
/** /**
@ -58,7 +58,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__) #if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM2 TRUE #define STM32_ICU_USE_TIM2 FALSE
#endif #endif
/** /**
@ -67,7 +67,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__) #if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM3 TRUE #define STM32_ICU_USE_TIM3 FALSE
#endif #endif
/** /**
@ -76,7 +76,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__) #if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM4 TRUE #define STM32_ICU_USE_TIM4 FALSE
#endif #endif
/** /**
@ -85,7 +85,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__) #if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM5 TRUE #define STM32_ICU_USE_TIM5 FALSE
#endif #endif
/** /**
@ -94,7 +94,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__) #if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM8 TRUE #define STM32_ICU_USE_TIM8 FALSE
#endif #endif
/** /**

12
os/hal/platforms/STM32/pwm_lld.h
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@ -94,7 +94,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__) #if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__)
#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM1 FALSE
#endif #endif
/** /**
@ -103,7 +103,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__) #if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__)
#define STM32_PWM_USE_TIM2 TRUE #define STM32_PWM_USE_TIM2 FALSE
#endif #endif
/** /**
@ -112,7 +112,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__) #if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__)
#define STM32_PWM_USE_TIM3 TRUE #define STM32_PWM_USE_TIM3 FALSE
#endif #endif
/** /**
@ -121,7 +121,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__) #if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__)
#define STM32_PWM_USE_TIM4 TRUE #define STM32_PWM_USE_TIM4 FALSE
#endif #endif
/** /**
@ -130,7 +130,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__) #if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__)
#define STM32_PWM_USE_TIM5 TRUE #define STM32_PWM_USE_TIM5 FALSE
#endif #endif
/** /**
@ -139,7 +139,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__) #if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__)
#define STM32_PWM_USE_TIM8 TRUE #define STM32_PWM_USE_TIM8 FALSE
#endif #endif
/** /**

207
os/hal/platforms/STM32F0xx/ext_lld_isr.c Normal file
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@ -0,0 +1,207 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F0xx/ext_lld_isr.c
* @brief STM32F0xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
#include "ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI0_1_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 0) | (1 << 1));
EXTI->PR = pr;
if (pr & (1 << 0))
EXTD1.config->channels[0].cb(&EXTD1, 0);
if (pr & (1 << 1))
EXTD1.config->channels[1].cb(&EXTD1, 1);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI2_3_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((2 << 0) | (3 << 1));
EXTI->PR = pr;
if (pr & (1 << 2))
EXTD1.config->channels[2].cb(&EXTD1, 2);
if (pr & (1 << 3))
EXTD1.config->channels[3].cb(&EXTD1, 3);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[4]...EXTI[15] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |
(1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
(1 << 14) | (1 << 15));
EXTI->PR = pr;
if (pr & (1 << 4))
EXTD1.config->channels[4].cb(&EXTD1, 4);
if (pr & (1 << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
if (pr & (1 << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
if (pr & (1 << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
if (pr & (1 << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
if (pr & (1 << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
if (pr & (1 << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
if (pr & (1 << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
if (pr & (1 << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
if (pr & (1 << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[16] interrupt handler (PVD).
*
* @isr
*/
CH_IRQ_HANDLER(PVD_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[17] interrupt handler (RTC).
*
* @isr
*/
CH_IRQ_HANDLER(RTC_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(EXTI0_1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY));
nvicEnableVector(EXTI2_3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY));
nvicEnableVector(EXTI4_15_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY));
nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
nvicEnableVector(RTC_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
}
/**
* @brief Disables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI0_1_IRQn);
nvicDisableVector(EXTI2_3_IRQn);
nvicDisableVector(EXTI4_15_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_IRQn);
}
#endif /* HAL_USE_EXT */
/** @} */

111
os/hal/platforms/STM32F0xx/ext_lld_isr.h Normal file
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@ -0,0 +1,111 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F0xx/ext_lld_isr.h
* @brief STM32F0xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
#ifndef _EXT_LLD_ISR_H_
#define _EXT_LLD_ISR_H_
#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0..1 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI2..3 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI4..15 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void ext_lld_exti_irq_enable(void);
void ext_lld_exti_irq_disable(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EXT */
#endif /* _EXT_LLD_ISR_H_ */
/** @} */

3
os/hal/platforms/STM32F0xx/hal_lld.h
View File

@ -950,7 +950,8 @@
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
/* STM32 DMA and RCC helpers.*/ /* STM32 ISR, DMA and RCC helpers.*/
#include "stm32_isr.h"
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_rcc.h" #include "stm32_rcc.h"

15
os/hal/platforms/STM32F0xx/platform.mk
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@ -1,12 +1,15 @@
# List of all the STM32F1xx platform files. # List of all the STM32F0xx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
# Required include directories # Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \ PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ ${CHIBIOS}/os/hal/platforms/STM32 \
${CHIBIOS}/os/hal/platforms/STM32 ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2

73
os/hal/platforms/STM32F0xx/stm32_isr.h Normal file
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@ -0,0 +1,73 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM3F0xx/stm32_isr.h
* @brief ISR remapper driver header.
*
* @addtogroup STM32F0xx_ISR
* @{
*/
#ifndef _STM32_ISR_H_
#define _STM32_ISR_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
#define STM32_TIM1_UP_HANDLER TIM1_BRK_UP_TRG_COM_IRQHandler
#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
#define STM32_TIM2_HANDLER TIM2_IRQHandler
#define STM32_TIM3_HANDLER TIM3_IRQHandler
#define STM32_TIM1_UP_NUMBER TIM1_BRK_UP_TRG_COM_IRQn
#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
#define STM32_TIM2_NUMBER TIM2_IRQn
#define STM32_TIM3_NUMBER TIM3_IRQn
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* _STM32_ISR_H_ */
/** @} */

454
os/hal/platforms/STM32F0xx/stm32f0xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.0.1
* @date 23-March-2012 * @date 20-April-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -61,7 +61,7 @@
* @{ * @{
*/ */
/* Uncomment the line below according to the target STM32F-0 device used in your /* Uncomment the line below according to the target STM32F0 device used in your
application application
*/ */
@ -71,8 +71,9 @@
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor. devices, you can define the device in your toolchain compiler preprocessor.
- STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory STM32F0xx devices are:
density ranges between 32 and 64 Kbytes. - STM32F050xx microcontrollers where the Flash memory density can go up to 32 Kbytes.
- STM32F051xx microcontrollers where the Flash memory density can go up to 64 Kbytes.
*/ */
#if !defined (STM32F0XX) #if !defined (STM32F0XX)
@ -138,11 +139,11 @@
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
/** /**
* @brief STM32F0xx Standard Peripheral Library version number V1.0.0 * @brief STM32F0xx Standard Peripheral Library version number V1.0.1
*/ */
#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ #define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
@ -2179,266 +2180,263 @@ typedef struct
/* */ /* */
/******************************************************************************/ /******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/ /******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */ #define RTC_TR_PM ((uint32_t)0x00400000)
#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */ #define RTC_TR_HT ((uint32_t)0x00300000)
#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */ #define RTC_TR_HT_0 ((uint32_t)0x00100000)
#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */ #define RTC_TR_HT_1 ((uint32_t)0x00200000)
#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */ #define RTC_TR_HU ((uint32_t)0x000F0000)
#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */ #define RTC_TR_HU_0 ((uint32_t)0x00010000)
#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */ #define RTC_TR_HU_1 ((uint32_t)0x00020000)
#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */ #define RTC_TR_HU_2 ((uint32_t)0x00040000)
#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */ #define RTC_TR_HU_3 ((uint32_t)0x00080000)
#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */ #define RTC_TR_MNT ((uint32_t)0x00007000)
#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */ #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */ #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */ #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */ #define RTC_TR_MNU ((uint32_t)0x00000F00)
#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */ #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */ #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */ #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */ #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */ #define RTC_TR_ST ((uint32_t)0x00000070)
#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */ #define RTC_TR_ST_0 ((uint32_t)0x00000010)
#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */ #define RTC_TR_ST_1 ((uint32_t)0x00000020)
#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */ #define RTC_TR_ST_2 ((uint32_t)0x00000040)
#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */ #define RTC_TR_SU ((uint32_t)0x0000000F)
#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */ #define RTC_TR_SU_0 ((uint32_t)0x00000001)
#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */ #define RTC_TR_SU_1 ((uint32_t)0x00000002)
#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */ #define RTC_TR_SU_2 ((uint32_t)0x00000004)
#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */ #define RTC_TR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_DR register *******************/ /******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */ #define RTC_DR_YT ((uint32_t)0x00F00000)
#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */ #define RTC_DR_YT_0 ((uint32_t)0x00100000)
#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */ #define RTC_DR_YT_1 ((uint32_t)0x00200000)
#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */ #define RTC_DR_YT_2 ((uint32_t)0x00400000)
#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */ #define RTC_DR_YT_3 ((uint32_t)0x00800000)
#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */ #define RTC_DR_YU ((uint32_t)0x000F0000)
#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */ #define RTC_DR_YU_0 ((uint32_t)0x00010000)
#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */ #define RTC_DR_YU_1 ((uint32_t)0x00020000)
#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */ #define RTC_DR_YU_2 ((uint32_t)0x00040000)
#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */ #define RTC_DR_YU_3 ((uint32_t)0x00080000)
#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */ #define RTC_DR_WDU ((uint32_t)0x0000E000)
#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */ #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */ #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */ #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */ #define RTC_DR_MT ((uint32_t)0x00001000)
#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */ #define RTC_DR_MU ((uint32_t)0x00000F00)
#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */ #define RTC_DR_MU_0 ((uint32_t)0x00000100)
#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */ #define RTC_DR_MU_1 ((uint32_t)0x00000200)
#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */ #define RTC_DR_MU_2 ((uint32_t)0x00000400)
#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */ #define RTC_DR_MU_3 ((uint32_t)0x00000800)
#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */ #define RTC_DR_DT ((uint32_t)0x00000030)
#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */ #define RTC_DR_DT_0 ((uint32_t)0x00000010)
#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */ #define RTC_DR_DT_1 ((uint32_t)0x00000020)
#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */ #define RTC_DR_DU ((uint32_t)0x0000000F)
#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */ #define RTC_DR_DU_0 ((uint32_t)0x00000001)
#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */ #define RTC_DR_DU_1 ((uint32_t)0x00000002)
#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */ #define RTC_DR_DU_2 ((uint32_t)0x00000004)
#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */ #define RTC_DR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_CR register *******************/ /******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */ #define RTC_CR_COE ((uint32_t)0x00800000)
#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */ #define RTC_CR_OSEL ((uint32_t)0x00600000)
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */ #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */ #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */ #define RTC_CR_POL ((uint32_t)0x00100000)
#define RTC_CR_CALSEL ((uint32_t)0x00080000) /*!< */ #define RTC_CR_CALSEL ((uint32_t)0x00080000)
#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */ #define RTC_CR_BCK ((uint32_t)0x00040000)
#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */ #define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */ #define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */ #define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */ #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */ #define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */ #define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_DCE ((uint32_t)0x00000080) /*!< */ #define RTC_CR_DCE ((uint32_t)0x00000080)
#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */ #define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */ #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */ #define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */ #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */ #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) /*!< */ #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */ #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */ #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */ #define RTC_ISR_TSF ((uint32_t)0x00000800)
#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */ #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */ #define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */ #define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */ #define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */ #define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */ #define RTC_ISR_SHPF ((uint32_t)0x00000008)
#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */ #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
/******************** Bits definition for RTC_PRER register *****************/ /******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */ #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */ #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_ALRMAR register ***************/ /******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */ #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */ #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */ #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */ #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */ #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */ #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */ #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */ #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */ #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */ #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */ #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */ #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */ #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */ #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */ #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */ #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */ #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */ #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */ #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */ #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */ #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */ #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */ #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */ #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */ #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */ #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */ #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */ #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */ #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */ #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */ #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */ #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */ #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */ #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */ #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */ #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */ #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */ #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */ #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */ #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_WPR register ******************/ /******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */ #define RTC_WPR_KEY ((uint32_t)0x000000FF)
/******************** Bits definition for RTC_SSR register ******************/ /******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS ((uint32_t)0x0003FFFF) /*!< */ #define RTC_SSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_SHIFTR register ***************/ /******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */ #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */ #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
/******************** Bits definition for RTC_TSTR register *****************/ /******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */ #define RTC_TSTR_PM ((uint32_t)0x00400000)
#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */ #define RTC_TSTR_HT ((uint32_t)0x00300000)
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */ #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */ #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */ #define RTC_TSTR_HU ((uint32_t)0x000F0000)
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */ #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */ #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */ #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */ #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */ #define RTC_TSTR_MNT ((uint32_t)0x00007000)
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */ #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */ #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */ #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */ #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */ #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */ #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */ #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */ #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */ #define RTC_TSTR_ST ((uint32_t)0x00000070)
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */ #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */ #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */ #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */ #define RTC_TSTR_SU ((uint32_t)0x0000000F)
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */ #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */ #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */ #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */ #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSDR register *****************/ /******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */ #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */ #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */ #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */ #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */ #define RTC_TSDR_MT ((uint32_t)0x00001000)
#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */ #define RTC_TSDR_MU ((uint32_t)0x00000F00)
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */ #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */ #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */ #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */ #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */ #define RTC_TSDR_DT ((uint32_t)0x00000030)
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */ #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */ #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */ #define RTC_TSDR_DU ((uint32_t)0x0000000F)
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */ #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */ #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */ #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */ #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSSSR register ****************/ /******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF) #define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_CAL register *****************/ /******************** Bits definition for RTC_CAL register *****************/
#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */ #define RTC_CAL_CALP ((uint32_t)0x00008000)
#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */ #define RTC_CAL_CALW8 ((uint32_t)0x00004000)
#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */ #define RTC_CAL_CALW16 ((uint32_t)0x00002000)
#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */ #define RTC_CAL_CALM ((uint32_t)0x000001FF)
#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */ #define RTC_CAL_CALM_0 ((uint32_t)0x00000001)
#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */ #define RTC_CAL_CALM_1 ((uint32_t)0x00000002)
#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */ #define RTC_CAL_CALM_2 ((uint32_t)0x00000004)
#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */ #define RTC_CAL_CALM_3 ((uint32_t)0x00000008)
#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */ #define RTC_CAL_CALM_4 ((uint32_t)0x00000010)
#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */ #define RTC_CAL_CALM_5 ((uint32_t)0x00000020)
#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */ #define RTC_CAL_CALM_6 ((uint32_t)0x00000040)
#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */ #define RTC_CAL_CALM_7 ((uint32_t)0x00000080)
#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */ #define RTC_CAL_CALM_8 ((uint32_t)0x00000100)
/******************** Bits definition for RTC_TAFCR register ****************/ /******************** Bits definition for RTC_TAFCR register ****************/
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) /*!< */ #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */ #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */ #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */ #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */ #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) /*!< */ #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */ #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */ #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */ #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */ #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */ #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */ #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) /*!< */ #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040) /*!< */ #define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) /*!< */ #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010) /*!< */ #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) /*!< */ #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) /*!< */ #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) /*!< */
/******************** Bits definition for RTC_ALRMASSR register *************/ /******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) /*!< */ #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) /*!< */ #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) /*!< */ #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) /*!< */ #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) /*!< */ #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) /*!< */ #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_BKP0R register ****************/ /******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */ #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP1R register ****************/ /******************** Bits definition for RTC_BKP1R register ****************/
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */ #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP2R register ****************/ /******************** Bits definition for RTC_BKP2R register ****************/
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */ #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP3R register ****************/ /******************** Bits definition for RTC_BKP3R register ****************/
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */ #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP4R register ****************/ /******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */ #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
/******************************************************************************/ /******************************************************************************/
/* */ /* */

342
os/hal/platforms/STM32F1xx/ext_lld_isr.c Normal file
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@ -0,0 +1,342 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F1xx/ext_lld_isr.c
* @brief STM32F1xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
#include "ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI0_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 0);
EXTD1.config->channels[0].cb(&EXTD1, 0);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI1_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 1);
EXTD1.config->channels[1].cb(&EXTD1, 1);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI2_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 2);
EXTD1.config->channels[2].cb(&EXTD1, 2);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI3_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 3);
EXTD1.config->channels[3].cb(&EXTD1, 3);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI4_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 4);
EXTD1.config->channels[4].cb(&EXTD1, 4);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
EXTI->PR = pr;
if (pr & (1 << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
if (pr & (1 << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
if (pr & (1 << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
if (pr & (1 << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
(1 << 15));
EXTI->PR = pr;
if (pr & (1 << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
if (pr & (1 << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
if (pr & (1 << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
if (pr & (1 << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
if (pr & (1 << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[16] interrupt handler (PVD).
*
* @isr
*/
CH_IRQ_HANDLER(PVD_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[17] interrupt handler (RTC).
*
* @isr
*/
CH_IRQ_HANDLER(RTCAlarm_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
CH_IRQ_EPILOGUE();
}
#if defined(STM32F10X_CL)
/**
* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[19] interrupt handler (ETH_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
CH_IRQ_EPILOGUE();
}
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
defined(STM32F10X_HD_VL)
#else /* Other STM32F1xx devices.*/
/**
* @brief EXTI[18] interrupt handler (USB_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(EXTI0_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
nvicEnableVector(EXTI1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
nvicEnableVector(EXTI2_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
nvicEnableVector(EXTI3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
nvicEnableVector(EXTI4_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
nvicEnableVector(EXTI9_5_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
nvicEnableVector(EXTI15_10_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
nvicEnableVector(RTC_Alarm_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
#if defined(STM32F10X_CL)
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
nvicEnableVector(OTG_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
nvicEnableVector(ETH_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
defined(STM32F10X_HD_VL)
/* EXTI vectors specific to STM32F1xx Value Line.*/
#else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
nvicEnableVector(USB_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
#endif
}
/**
* @brief Disables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI0_IRQn);
nvicDisableVector(EXTI1_IRQn);
nvicDisableVector(EXTI2_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_Alarm_IRQn);
#if defined(STM32F10X_CL)
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
nvicDisableVector(OTG_FS_WKUP_IRQn);
nvicDisableVector(ETH_WKUP_IRQn);
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
defined(STM32F10X_HD_VL)
/* EXTI vectors specific to STM32F1xx Value Line.*/
#else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
nvicDisableVector(USB_FS_WKUP_IRQn);
#endif
}
#endif /* HAL_USE_EXT */
/** @} */

153
os/hal/platforms/STM32F1xx/ext_lld_isr.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F1xx/ext_lld_isr.h
* @brief STM32F1xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
#ifndef _EXT_LLD_ISR_H_
#define _EXT_LLD_ISR_H_
#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI9..5 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI15..10 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void ext_lld_exti_irq_enable(void);
void ext_lld_exti_irq_disable(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EXT */
#endif /* _EXT_LLD_ISR_H_ */
/** @} */

3
os/hal/platforms/STM32F1xx/hal_lld.h
View File

@ -240,7 +240,8 @@ typedef uint32_t halrtcnt_t;
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
/* STM32 DMA and RCC helpers.*/ /* STM32 ISR, DMA and RCC helpers.*/
#include "stm32_isr.h"
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_rcc.h" #include "stm32_rcc.h"

1
os/hal/platforms/STM32F1xx/platform.mk
View File

@ -2,6 +2,7 @@
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

103
os/hal/platforms/STM32F1xx/stm32_isr.h Normal file
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@ -0,0 +1,103 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM3F1xx/stm32_isr.h
* @brief ISR remapper driver header.
*
* @addtogroup STM32F1xx_ISR
* @{
*/
#ifndef _STM32_ISR_H_
#define _STM32_ISR_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
#if defined(STM32F10X_XL)
#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
defined(STM32F10X_HD_VL)
#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
#else
#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
#endif
#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
#define STM32_TIM2_HANDLER TIM2_IRQHandler
#define STM32_TIM3_HANDLER TIM3_IRQHandler
#define STM32_TIM4_HANDLER TIM4_IRQHandler
#define STM32_TIM5_HANDLER TIM5_IRQHandler
#ifdef STM32F10X_XL
#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
#else
#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
#endif
#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler
#if defined(STM32F10X_XL)
#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
defined(STM32F10X_HD_VL)
#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM16_IRQn
#else
#define STM32_TIM1_UP_NUMBER TIM1_UP_IRQn
#endif
#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
#define STM32_TIM2_NUMBER TIM2_IRQn
#define STM32_TIM3_NUMBER TIM3_IRQn
#define STM32_TIM4_NUMBER TIM4_IRQn
#define STM32_TIM5_NUMBER TIM5_IRQn
#ifdef STM32F10X_XL
#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
#else
#define STM32_TIM8_UP_NUMBER TIM8_UP_IRQn
#endif
#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* _STM32_ISR_H_ */
/** @} */

357
os/hal/platforms/STM32F2xx/ext_lld_isr.c Normal file
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@ -0,0 +1,357 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F2xx/ext_lld_isr.c
* @brief STM32F2xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
#include "ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI0_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 0);
EXTD1.config->channels[0].cb(&EXTD1, 0);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI1_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 1);
EXTD1.config->channels[1].cb(&EXTD1, 1);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI2_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 2);
EXTD1.config->channels[2].cb(&EXTD1, 2);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI3_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 3);
EXTD1.config->channels[3].cb(&EXTD1, 3);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI4_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 4);
EXTD1.config->channels[4].cb(&EXTD1, 4);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
EXTI->PR = pr;
if (pr & (1 << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
if (pr & (1 << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
if (pr & (1 << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
if (pr & (1 << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
(1 << 15));
EXTI->PR = pr;
if (pr & (1 << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
if (pr & (1 << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
if (pr & (1 << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
if (pr & (1 << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
if (pr & (1 << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[16] interrupt handler (PVD).
*
* @isr
*/
CH_IRQ_HANDLER(PVD_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[17] interrupt handler (RTC).
*
* @isr
*/
CH_IRQ_HANDLER(RTCAlarm_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[19] interrupt handler (ETH_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 20);
EXTD1.config->channels[20].cb(&EXTD1, 20);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[21] interrupt handler (TAMPER_STAMP).
*
* @isr
*/
CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 21);
EXTD1.config->channels[21].cb(&EXTD1, 21);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[22] interrupt handler (RTC_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 22);
EXTD1.config->channels[22].cb(&EXTD1, 22);
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(EXTI0_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
nvicEnableVector(EXTI1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
nvicEnableVector(EXTI2_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
nvicEnableVector(EXTI3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
nvicEnableVector(EXTI4_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
nvicEnableVector(EXTI9_5_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
nvicEnableVector(EXTI15_10_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
nvicEnableVector(RTC_Alarm_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
nvicEnableVector(OTG_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
nvicEnableVector(ETH_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
nvicEnableVector(OTG_HS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
nvicEnableVector(TAMP_STAMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
nvicEnableVector(RTC_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
}
/**
* @brief Disables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI0_IRQn);
nvicDisableVector(EXTI1_IRQn);
nvicDisableVector(EXTI2_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_Alarm_IRQn);
nvicDisableVector(OTG_FS_WKUP_IRQn);
nvicDisableVector(ETH_WKUP_IRQn);
nvicDisableVector(OTG_HS_WKUP_IRQn);
nvicDisableVector(TAMP_STAMP_IRQn);
nvicDisableVector(RTC_WKUP_IRQn);
}
#endif /* HAL_USE_EXT */
/** @} */

174
os/hal/platforms/STM32F2xx/ext_lld_isr.h Normal file
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@ -0,0 +1,174 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F2xx/ext_lld_isr.h
* @brief STM32F2xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
#ifndef _EXT_LLD_ISR_H_
#define _EXT_LLD_ISR_H_
#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI9..5 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI15..10 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI20 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI21 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI21_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI22 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI22_IRQ_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void ext_lld_exti_irq_enable(void);
void ext_lld_exti_irq_disable(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EXT */
#endif /* _EXT_LLD_ISR_H_ */
/** @} */

3
os/hal/platforms/STM32F2xx/hal_lld.h
View File

@ -1383,7 +1383,8 @@ typedef uint32_t halrtcnt_t;
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
/* STM32 DMA and RCC helpers.*/ /* STM32 ISR, DMA and RCC helpers.*/
#include "stm32_isr.h"
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_rcc.h" #include "stm32_rcc.h"

1
os/hal/platforms/STM32F2xx/platform.mk
View File

@ -2,6 +2,7 @@
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F2xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F2xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F2xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F2xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F2xx/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

81
os/hal/platforms/STM32F2xx/stm32_isr.h Normal file
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@ -0,0 +1,81 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM3F2xx/stm32_isr.h
* @brief ISR remapper driver header.
*
* @addtogroup STM32F2xx_ISR
* @{
*/
#ifndef _STM32_ISR_H_
#define _STM32_ISR_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
#define STM32_TIM2_HANDLER TIM2_IRQHandler
#define STM32_TIM3_HANDLER TIM3_IRQHandler
#define STM32_TIM4_HANDLER TIM4_IRQHandler
#define STM32_TIM5_HANDLER TIM5_IRQHandler
#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler
#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn
#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
#define STM32_TIM2_NUMBER TIM2_IRQn
#define STM32_TIM3_NUMBER TIM3_IRQn
#define STM32_TIM4_NUMBER TIM4_IRQn
#define STM32_TIM5_NUMBER TIM5_IRQn
#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* _STM32_ISR_H_ */
/** @} */

357
os/hal/platforms/STM32F4xx/ext_lld_isr.c Normal file
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@ -0,0 +1,357 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F4xx/ext_lld_isr.c
* @brief STM32F4xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
#include "ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI0_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 0);
EXTD1.config->channels[0].cb(&EXTD1, 0);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI1_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 1);
EXTD1.config->channels[1].cb(&EXTD1, 1);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI2_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 2);
EXTD1.config->channels[2].cb(&EXTD1, 2);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI3_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 3);
EXTD1.config->channels[3].cb(&EXTD1, 3);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI4_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 4);
EXTD1.config->channels[4].cb(&EXTD1, 4);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
EXTI->PR = pr;
if (pr & (1 << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
if (pr & (1 << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
if (pr & (1 << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
if (pr & (1 << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
(1 << 15));
EXTI->PR = pr;
if (pr & (1 << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
if (pr & (1 << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
if (pr & (1 << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
if (pr & (1 << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
if (pr & (1 << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[16] interrupt handler (PVD).
*
* @isr
*/
CH_IRQ_HANDLER(PVD_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[17] interrupt handler (RTC).
*
* @isr
*/
CH_IRQ_HANDLER(RTCAlarm_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[19] interrupt handler (ETH_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 20);
EXTD1.config->channels[20].cb(&EXTD1, 20);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[21] interrupt handler (TAMPER_STAMP).
*
* @isr
*/
CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 21);
EXTD1.config->channels[21].cb(&EXTD1, 21);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[22] interrupt handler (RTC_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 22);
EXTD1.config->channels[22].cb(&EXTD1, 22);
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(EXTI0_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
nvicEnableVector(EXTI1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
nvicEnableVector(EXTI2_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
nvicEnableVector(EXTI3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
nvicEnableVector(EXTI4_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
nvicEnableVector(EXTI9_5_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
nvicEnableVector(EXTI15_10_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
nvicEnableVector(RTC_Alarm_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
nvicEnableVector(OTG_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
nvicEnableVector(ETH_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
nvicEnableVector(OTG_HS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
nvicEnableVector(TAMP_STAMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
nvicEnableVector(RTC_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
}
/**
* @brief Disables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI0_IRQn);
nvicDisableVector(EXTI1_IRQn);
nvicDisableVector(EXTI2_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_Alarm_IRQn);
nvicDisableVector(OTG_FS_WKUP_IRQn);
nvicDisableVector(ETH_WKUP_IRQn);
nvicDisableVector(OTG_HS_WKUP_IRQn);
nvicDisableVector(TAMP_STAMP_IRQn);
nvicDisableVector(RTC_WKUP_IRQn);
}
#endif /* HAL_USE_EXT */
/** @} */

174
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@ -0,0 +1,174 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F4xx/ext_lld_isr.h
* @brief STM32F4xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
#ifndef _EXT_LLD_ISR_H_
#define _EXT_LLD_ISR_H_
#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI9..5 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI15..10 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI20 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI21 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI21_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI22 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI22_IRQ_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void ext_lld_exti_irq_enable(void);
void ext_lld_exti_irq_disable(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EXT */
#endif /* _EXT_LLD_ISR_H_ */
/** @} */

3
os/hal/platforms/STM32F4xx/hal_lld.h
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@ -1403,7 +1403,8 @@ typedef uint32_t halrtcnt_t;
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
/* STM32 DMA and RCC helpers.*/ /* STM32 ISR, DMA and RCC helpers.*/
#include "stm32_isr.h"
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_rcc.h" #include "stm32_rcc.h"

1
os/hal/platforms/STM32F4xx/platform.mk
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@ -2,6 +2,7 @@
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F4xx/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

81
os/hal/platforms/STM32F4xx/stm32_isr.h Normal file
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@ -0,0 +1,81 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM3F4xx/stm32_isr.h
* @brief ISR remapper driver header.
*
* @addtogroup STM32F4xx_ISR
* @{
*/
#ifndef _STM32_ISR_H_
#define _STM32_ISR_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
#define STM32_TIM2_HANDLER TIM2_IRQHandler
#define STM32_TIM3_HANDLER TIM3_IRQHandler
#define STM32_TIM4_HANDLER TIM4_IRQHandler
#define STM32_TIM5_HANDLER TIM5_IRQHandler
#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler
#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn
#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
#define STM32_TIM2_NUMBER TIM2_IRQn
#define STM32_TIM3_NUMBER TIM3_IRQn
#define STM32_TIM4_NUMBER TIM4_IRQn
#define STM32_TIM5_NUMBER TIM5_IRQn
#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* _STM32_ISR_H_ */
/** @} */

343
os/hal/platforms/STM32L1xx/ext_lld_isr.c Normal file
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@ -0,0 +1,343 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32L1xx/ext_lld_isr.c
* @brief STM32L1xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
#include "ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI0_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 0);
EXTD1.config->channels[0].cb(&EXTD1, 0);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI1_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 1);
EXTD1.config->channels[1].cb(&EXTD1, 1);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI2_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 2);
EXTD1.config->channels[2].cb(&EXTD1, 2);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI3_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 3);
EXTD1.config->channels[3].cb(&EXTD1, 3);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI4_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 4);
EXTD1.config->channels[4].cb(&EXTD1, 4);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
EXTI->PR = pr;
if (pr & (1 << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
if (pr & (1 << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
if (pr & (1 << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
if (pr & (1 << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
(1 << 15));
EXTI->PR = pr;
if (pr & (1 << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
if (pr & (1 << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
if (pr & (1 << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
if (pr & (1 << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
if (pr & (1 << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[16] interrupt handler (PVD).
*
* @isr
*/
CH_IRQ_HANDLER(PVD_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[17] interrupt handler (RTC).
*
* @isr
*/
CH_IRQ_HANDLER(RTCAlarm_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[18] interrupt handler (USB_FS_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[19] interrupt handler (TAMPER_STAMP).
*
* @isr
*/
CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[20] interrupt handler (RTC_WKUP).
*
* @isr
*/
CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 20);
EXTD1.config->channels[20].cb(&EXTD1, 20);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[21]...EXTI[22] interrupt handler (COMP).
*
* @isr
*/
CH_IRQ_HANDLER(COMP_IRQHandler) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 21) | (1 << 22));
EXTI->PR = pr;
if (pr & (1 << 21))
EXTD1.config->channels[21].cb(&EXTD1, 21);
if (pr & (1 << 22))
EXTD1.config->channels[22].cb(&EXTD1, 22);
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(EXTI0_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
nvicEnableVector(EXTI1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
nvicEnableVector(EXTI2_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
nvicEnableVector(EXTI3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
nvicEnableVector(EXTI4_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
nvicEnableVector(EXTI9_5_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
nvicEnableVector(EXTI15_10_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
nvicEnableVector(RTC_Alarm_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
nvicEnableVector(USB_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
nvicEnableVector(TAMPER_STAMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
nvicEnableVector(RTC_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
nvicEnableVector(COMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY));
}
/**
* @brief Disables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI0_IRQn);
nvicDisableVector(EXTI1_IRQn);
nvicDisableVector(EXTI2_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_Alarm_IRQn);
nvicDisableVector(USB_FS_WKUP_IRQn);
nvicDisableVector(TAMPER_STAMP_IRQn);
nvicDisableVector(RTC_WKUP_IRQn);
nvicDisableVector(COMP_IRQn);
}
#endif /* HAL_USE_EXT */
/** @} */

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@ -0,0 +1,167 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32L1xx/ext_lld_isr.h
* @brief STM32L1xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
#ifndef _EXT_LLD_ISR_H_
#define _EXT_LLD_ISR_H_
#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI9..5 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI15..10 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI20 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#endif
/**
* @brief EXTI21..22 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void ext_lld_exti_irq_enable(void);
void ext_lld_exti_irq_disable(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EXT */
#endif /* _EXT_LLD_ISR_H_ */
/** @} */

3
os/hal/platforms/STM32L1xx/hal_lld.h
View File

@ -1044,7 +1044,8 @@ typedef uint32_t halrtcnt_t;
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
/* STM32 DMA and RCC helpers.*/ /* STM32 ISR, DMA and RCC helpers.*/
#include "stm32_isr.h"
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_rcc.h" #include "stm32_rcc.h"

2
os/hal/platforms/STM32L1xx/platform.mk
View File

@ -2,6 +2,7 @@
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32L1xx/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \
@ -17,5 +18,4 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx \ PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx \
${CHIBIOS}/os/hal/platforms/STM32 \ ${CHIBIOS}/os/hal/platforms/STM32 \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
${CHIBIOS}/os/hal/platforms/STM32/DMAv1 \
${CHIBIOS}/os/hal/platforms/STM32/USBv1 ${CHIBIOS}/os/hal/platforms/STM32/USBv1

71
os/hal/platforms/STM32L1xx/stm32_isr.h Normal file
View File

@ -0,0 +1,71 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM3L1xx/stm32_isr.h
* @brief ISR remapper driver header.
*
* @addtogroup STM32L1xx_ISR
* @{
*/
#ifndef _STM32_ISR_H_
#define _STM32_ISR_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
#define STM32_TIM2_HANDLER TIM2_IRQHandler
#define STM32_TIM3_HANDLER TIM3_IRQHandler
#define STM32_TIM4_HANDLER TIM4_IRQHandler
#define STM32_TIM2_NUMBER TIM2_IRQn
#define STM32_TIM3_NUMBER TIM3_IRQn
#define STM32_TIM4_NUMBER TIM4_IRQn
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* _STM32_ISR_H_ */
/** @} */

4
readme.txt
View File

@ -156,6 +156,9 @@
3484947)(backported to 2.4.1). 3484947)(backported to 2.4.1).
- FIX: Fixed various minor documentation errors (bug 3484942)(backported - FIX: Fixed various minor documentation errors (bug 3484942)(backported
to 2.4.1). to 2.4.1).
- NEW: Reorganized the STM32 EXT driver to have a sub-platform specific
part containing all the ISR related code, this has been necessary because
the significant differences among the various sub-families.
- NEW: Validated CAN driver on STM32F2/F4 (backported to 2.4.2). - NEW: Validated CAN driver on STM32F2/F4 (backported to 2.4.2).
- NEW: USB implementation for STM32F105/F107/2xx/F4xx devices. - NEW: USB implementation for STM32F105/F107/2xx/F4xx devices.
- NEW: Improved SerialUSB driver using the new queued mode, much smaller - NEW: Improved SerialUSB driver using the new queued mode, much smaller
@ -170,6 +173,7 @@
support several new devices. support several new devices.
- NEW: Demo for STM32F0-Discovery board. - NEW: Demo for STM32F0-Discovery board.
- NEW: Initial support for STM32F0xx devices, added a specific ADC driver. - NEW: Initial support for STM32F0xx devices, added a specific ADC driver.
Validated EXT, PAL, Serial, SPI drivers.
- NEW: Added a common ancestor class to the SDC and MMC_SPI drivers. This - NEW: Added a common ancestor class to the SDC and MMC_SPI drivers. This
allows to share code and definitions. allows to share code and definitions.
- NEW: Modified the SDC driver to implement the new block devices abstract - NEW: Modified the SDC driver to implement the new block devices abstract

10
testhal/LPC11xx/IRQ_STORM/main.c
View File

@ -170,29 +170,29 @@ static const GPTConfig gpt2cfg = {
static void print(char *p) { static void print(char *p) {
while (*p) { while (*p) {
chIOPut(&SD1, *p++); chSequentialStreamPut(&SD1, *p++);
} }
} }
static void println(char *p) { static void println(char *p) {
while (*p) { while (*p) {
chIOPut(&SD1, *p++); chSequentialStreamPut(&SD1, *p++);
} }
chIOWriteTimeout(&SD1, (uint8_t *)"\r\n", 2, TIME_INFINITE); chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2);
} }
static void printn(uint32_t n) { static void printn(uint32_t n) {
char buf[16], *p; char buf[16], *p;
if (!n) if (!n)
chIOPut(&SD1, '0'); chSequentialStreamPut(&SD1, '0');
else { else {
p = buf; p = buf;
while (n) while (n)
*p++ = (n % 10) + '0', n /= 10; *p++ = (n % 10) + '0', n /= 10;
while (p > buf) while (p > buf)
chIOPut(&SD1, *--p); chSequentialStreamPut(&SD1, *--p);
} }
} }

4
testhal/LPC11xx/IRQ_STORM/mcuconf.h
View File

@ -53,8 +53,8 @@
#define LPC11xx_GPT_USE_CT16B1 TRUE #define LPC11xx_GPT_USE_CT16B1 TRUE
#define LPC11xx_GPT_USE_CT32B0 TRUE #define LPC11xx_GPT_USE_CT32B0 TRUE
#define LPC11xx_GPT_USE_CT32B1 TRUE #define LPC11xx_GPT_USE_CT32B1 TRUE
#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 0 #define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 1
#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 1 #define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 3
#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2 #define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2
#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2 #define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2

10
testhal/LPC13xx/IRQ_STORM/main.c
View File

@ -170,29 +170,29 @@ static const GPTConfig gpt2cfg = {
static void print(char *p) { static void print(char *p) {
while (*p) { while (*p) {
chIOPut(&SD1, *p++); chSequentialStreamPut(&SD1, *p++);
} }
} }
static void println(char *p) { static void println(char *p) {
while (*p) { while (*p) {
chIOPut(&SD1, *p++); chSequentialStreamPut(&SD1, *p++);
} }
chIOWriteTimeout(&SD1, (uint8_t *)"\r\n", 2, TIME_INFINITE); chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2);
} }
static void printn(uint32_t n) { static void printn(uint32_t n) {
char buf[16], *p; char buf[16], *p;
if (!n) if (!n)
chIOPut(&SD1, '0'); chSequentialStreamPut(&SD1, '0');
else { else {
p = buf; p = buf;
while (n) while (n)
*p++ = (n % 10) + '0', n /= 10; *p++ = (n % 10) + '0', n /= 10;
while (p > buf) while (p > buf)
chIOPut(&SD1, *--p); chSequentialStreamPut(&SD1, *--p);
} }
} }

2
testhal/LPC13xx/IRQ_STORM/mcuconf.h
View File

@ -54,7 +54,7 @@
#define LPC13xx_GPT_USE_CT32B0 TRUE #define LPC13xx_GPT_USE_CT32B0 TRUE
#define LPC13xx_GPT_USE_CT32B1 TRUE #define LPC13xx_GPT_USE_CT32B1 TRUE
#define LPC13xx_GPT_CT16B0_IRQ_PRIORITY 2 #define LPC13xx_GPT_CT16B0_IRQ_PRIORITY 2
#define LPC13xx_GPT_CT16B1_IRQ_PRIORITY 2 #define LPC13xx_GPT_CT16B1_IRQ_PRIORITY 6
#define LPC13xx_GPT_CT32B0_IRQ_PRIORITY 2 #define LPC13xx_GPT_CT32B0_IRQ_PRIORITY 2
#define LPC13xx_GPT_CT32B1_IRQ_PRIORITY 2 #define LPC13xx_GPT_CT32B1_IRQ_PRIORITY 2

17
testhal/STM32F0xx/ADC/mcuconf.h
View File

@ -59,6 +59,23 @@
#define STM32_USART1SW STM32_USART1SW_PCLK #define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
/* /*
* SERIAL driver system settings. * SERIAL driver system settings.
*/ */

207
testhal/STM32F0xx/EXT/Makefile Normal file
View File

@ -0,0 +1,207 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../../..
include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
#include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F051x8.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m0
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
INCDIR += $(STM32INC)
USE_OPT += -DUSE_STDPERIPH_DRIVER
endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

535
testhal/STM32F0xx/EXT/chconf.h Normal file
View File

@ -0,0 +1,535 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE TRUE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS TRUE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT TRUE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Block size for MMC transfers.
*/
#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
#define MMC_SECTOR_SIZE 512
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/**
* @brief Number of positive insertion queries before generating the
* insertion event.
*/
#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
#define MMC_POLLING_INTERVAL 10
#endif
/**
* @brief Interval, in milliseconds, between insertion queries.
*/
#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
#define MMC_POLLING_DELAY 10
#endif
/**
* @brief Uses the SPI polled API for small data transfers.
* @details Polled transfers usually improve performance because it
* saves two context switches and interrupt servicing. Note
* that this option has no effect on large transfers which
* are always performed using DMAs/IRQs.
*/
#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
#define MMC_USE_SPI_POLLING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "ch.h"
#include "hal.h"
static void led4off(void *arg) {
(void)arg;
palClearPad(GPIOC, GPIOC_LED4);
}
/* Triggered when the button is pressed or released. The LED4 is set to ON.*/
static void extcb1(EXTDriver *extp, expchannel_t channel) {
static VirtualTimer vt4;
(void)extp;
(void)channel;
palSetPad(GPIOC, GPIOC_LED4);
chSysLockFromIsr();
if (chVTIsArmedI(&vt4))
chVTResetI(&vt4);
/* LED4 set to OFF after 200mS.*/
chVTSetI(&vt4, MS2ST(200), led4off, NULL);
chSysUnlockFromIsr();
}
static const EXTConfig extcfg = {
{
{EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}
}
};
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the EXT driver 1.
*/
extStart(&EXTD1, &extcfg);
/*
* Normal main() thread activity, in this demo it enables and disables the
* button EXT channel using 5 seconds intervals.
*/
while (TRUE) {
chThdSleepMilliseconds(5000);
extChannelDisable(&EXTD1, 0);
chThdSleepMilliseconds(5000);
extChannelEnable(&EXTD1, 0);
}
}

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* STM32F0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_HSI14_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 TRUE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 3
#define STM32_SERIAL_USART2_PRIORITY 3
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()

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*****************************************************************************
** ChibiOS/RT HAL - EXT driver demo for STM32F0xx. **
*****************************************************************************
** TARGET **
The demo will on an STMicroelectronics STM32F0-Discovery board.
** The Demo **
The application demonstrates the use of the STM32F0xx EXT driver.
** Board Setup **
None required.
** Build Procedure **
The demo has been tested using the free Codesourcery GCC-based toolchain
and YAGARTO.
Just modify the TRGT line in the makefile in order to use different GCC ports.
** Notes **
Some files used by the demo are not part of ChibiOS/RT but are copyright of
ST Microelectronics and are licensed under a different license.
Also note that not all the files present in the ST library are distributed
with ChibiOS/RT, you can find the whole library on the ST web site:
http://www.st.com

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##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../../..
include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
#include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F051x8.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m0
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
INCDIR += $(STM32INC)
USE_OPT += -DUSE_STDPERIPH_DRIVER
endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

535
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@ -0,0 +1,535 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT TRUE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Block size for MMC transfers.
*/
#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
#define MMC_SECTOR_SIZE 512
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/**
* @brief Number of positive insertion queries before generating the
* insertion event.
*/
#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
#define MMC_POLLING_INTERVAL 10
#endif
/**
* @brief Interval, in milliseconds, between insertion queries.
*/
#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
#define MMC_POLLING_DELAY 10
#endif
/**
* @brief Uses the SPI polled API for small data transfers.
* @details Polled transfers usually improve performance because it
* saves two context switches and interrupt servicing. Note
* that this option has no effect on large transfers which
* are always performed using DMAs/IRQs.
*/
#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
#define MMC_USE_SPI_POLLING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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testhal/STM32F0xx/IRQ_STORM/main.c Normal file
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@ -0,0 +1,332 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdlib.h>
#include "ch.h"
#include "hal.h"
/*===========================================================================*/
/* Configurable settings. */
/*===========================================================================*/
#ifndef RANDOMIZE
#define RANDOMIZE FALSE
#endif
#ifndef ITERATIONS
#define ITERATIONS 100
#endif
#ifndef NUM_THREADS
#define NUM_THREADS 4
#endif
#ifndef MAILBOX_SIZE
#define MAILBOX_SIZE 4
#endif
/*===========================================================================*/
/* Test related code. */
/*===========================================================================*/
#define MSG_SEND_LEFT 0
#define MSG_SEND_RIGHT 1
static bool_t saturated;
/*
* Mailboxes and buffers.
*/
static Mailbox mb[NUM_THREADS];
static msg_t b[NUM_THREADS][MAILBOX_SIZE];
/*
* Test worker threads.
*/
static WORKING_AREA(waWorkerThread[NUM_THREADS], 128);
static msg_t WorkerThread(void *arg) {
static volatile unsigned x = 0;
static unsigned cnt = 0;
unsigned me = (unsigned)arg;
unsigned target;
unsigned r;
msg_t msg;
chRegSetThreadName("worker");
/* Work loop.*/
while (TRUE) {
/* Waiting for a message.*/
chMBFetch(&mb[me], &msg, TIME_INFINITE);
#if RANDOMIZE
/* Pseudo-random delay.*/
{
chSysLock();
r = rand() & 15;
chSysUnlock();
while (r--)
x++;
}
#else
/* Fixed delay.*/
{
r = me >> 4;
while (r--)
x++;
}
#endif
/* Deciding in which direction to re-send the message.*/
if (msg == MSG_SEND_LEFT)
target = me - 1;
else
target = me + 1;
if (target < NUM_THREADS) {
/* If this thread is not at the end of a chain re-sending the message,
note this check works because the variable target is unsigned.*/
msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE);
if (msg != RDY_OK)
saturated = TRUE;
}
else {
/* Provides a visual feedback about the system.*/
if (++cnt >= 500) {
cnt = 0;
palTogglePad(GPIOC, GPIOC_LED4);
}
}
}
}
/*
* GPT2 callback.
*/
static void gpt2cb(GPTDriver *gptp) {
msg_t msg;
(void)gptp;
chSysLockFromIsr();
msg = chMBPostI(&mb[0], MSG_SEND_RIGHT);
if (msg != RDY_OK)
saturated = TRUE;
chSysUnlockFromIsr();
}
/*
* GPT3 callback.
*/
static void gpt3cb(GPTDriver *gptp) {
msg_t msg;
(void)gptp;
chSysLockFromIsr();
msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT);
if (msg != RDY_OK)
saturated = TRUE;
chSysUnlockFromIsr();
}
/*
* GPT2 configuration.
*/
static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/
};
/*
* GPT3 configuration.
*/
static const GPTConfig gpt3cfg = {
1000000, /* 1MHz timer clock.*/
gpt3cb /* Timer callback.*/
};
/*===========================================================================*/
/* Generic demo code. */
/*===========================================================================*/
static void print(char *p) {
while (*p) {
chSequentialStreamPut(&SD1, *p++);
}
}
static void println(char *p) {
while (*p) {
chSequentialStreamPut(&SD1, *p++);
}
chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2);
}
static void printn(uint32_t n) {
char buf[16], *p;
if (!n)
chSequentialStreamPut(&SD1, '0');
else {
p = buf;
while (n)
*p++ = (n % 10) + '0', n /= 10;
while (p > buf)
chSequentialStreamPut(&SD1, *--p);
}
}
/*
* Application entry point.
*/
int main(void) {
unsigned i;
gptcnt_t interval, threshold, worst;
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Prepares the Serial driver 1 and GPT drivers 2 and 3.
*/
sdStart(&SD1, NULL);
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1)); /* USART1 TX. */
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(1)); /* USART1 RX. */
gptStart(&GPTD2, &gpt2cfg);
gptStart(&GPTD3, &gpt3cfg);
/*
* Initializes the mailboxes and creates the worker threads.
*/
for (i = 0; i < NUM_THREADS; i++) {
chMBInit(&mb[i], b[i], MAILBOX_SIZE);
chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i],
NORMALPRIO - 20, WorkerThread, (void *)i);
}
/*
* Test procedure.
*/
println("");
println("*** ChibiOS/RT IRQ-STORM long duration test");
println("***");
print("*** Kernel: ");
println(CH_KERNEL_VERSION);
print("*** Compiled: ");
println(__DATE__ " - " __TIME__);
#ifdef CH_COMPILER_NAME
print("*** Compiler: ");
println(CH_COMPILER_NAME);
#endif
print("*** Architecture: ");
println(CH_ARCHITECTURE_NAME);
#ifdef CH_CORE_VARIANT_NAME
print("*** Core Variant: ");
println(CH_CORE_VARIANT_NAME);
#endif
#ifdef CH_PORT_INFO
print("*** Port Info: ");
println(CH_PORT_INFO);
#endif
#ifdef PLATFORM_NAME
print("*** Platform: ");
println(PLATFORM_NAME);
#endif
#ifdef BOARD_NAME
print("*** Test Board: ");
println(BOARD_NAME);
#endif
println("***");
print("*** System Clock: ");
printn(STM32_SYSCLK);
println("");
print("*** Iterations: ");
printn(ITERATIONS);
println("");
print("*** Randomize: ");
printn(RANDOMIZE);
println("");
print("*** Threads: ");
printn(NUM_THREADS);
println("");
print("*** Mailbox size: ");
printn(MAILBOX_SIZE);
println("");
println("");
worst = 0;
for (i = 1; i <= ITERATIONS; i++){
print("Iteration ");
printn(i);
println("");
saturated = FALSE;
threshold = 0;
for (interval = 2000; interval >= 20; interval -= interval / 10) {
gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/
gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/
chThdSleepMilliseconds(1000);
gptStopTimer(&GPTD2);
gptStopTimer(&GPTD3);
if (!saturated)
print(".");
else {
print("#");
if (threshold == 0)
threshold = interval;
}
}
/* Gives the worker threads a chance to empty the mailboxes before next
cycle.*/
chThdSleepMilliseconds(20);
println("");
print("Saturated at ");
printn(threshold);
println(" uS");
println("");
if (threshold > worst)
worst = threshold;
}
gptStopTimer(&GPTD2);
gptStopTimer(&GPTD3);
print("Worst case at ");
printn(worst);
println(" uS");
println("");
println("Test Complete");
/*
* Normal main() thread activity, nothing in this test.
*/
while (TRUE) {
chThdSleepMilliseconds(5000);
}
return 0;
}

111
testhal/STM32F0xx/IRQ_STORM/mcuconf.h Normal file
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@ -0,0 +1,111 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* STM32F0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_HSI14_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 TRUE
#define STM32_GPT_USE_TIM3 TRUE
#define STM32_GPT_TIM1_IRQ_PRIORITY 2
#define STM32_GPT_TIM2_IRQ_PRIORITY 1
#define STM32_GPT_TIM3_IRQ_PRIORITY 3
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 TRUE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 3
#define STM32_SERIAL_USART2_PRIORITY 3
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()

31
testhal/STM32F0xx/IRQ_STORM/readme.txt Normal file
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@ -0,0 +1,31 @@
*****************************************************************************
** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32F0xx. **
*****************************************************************************
** TARGET **
The demo will on an STMicroelectronics STM32F0-Discovery board.
** The Demo **
The application demonstrates the use of the STM32F0xx GPT, PAL and Serial
drivers in order to implement a system stress demo.
** Board Setup **
None.
** Build Procedure **
The demo has been tested using the free Codesourcery GCC-based toolchain
and YAGARTO.
Just modify the TRGT line in the makefile in order to use different GCC ports.
** Notes **
Some files used by the demo are not part of ChibiOS/RT but are copyright of
ST Microelectronics and are licensed under a different license.
Also note that not all the files present in the ST library are distributed
with ChibiOS/RT, you can find the whole library on the ST web site:
http://www.st.com

10
testhal/STM32F1xx/IRQ_STORM/main.c
View File

@ -170,29 +170,29 @@ static const GPTConfig gpt2cfg = {
static void print(char *p) { static void print(char *p) {
while (*p) { while (*p) {
chIOPut(&SD2, *p++); chSequentialStreamPut(&SD2, *p++);
} }
} }
static void println(char *p) { static void println(char *p) {
while (*p) { while (*p) {
chIOPut(&SD2, *p++); chSequentialStreamPut(&SD2, *p++);
} }
chIOWriteTimeout(&SD2, (uint8_t *)"\r\n", 2, TIME_INFINITE); chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2);
} }
static void printn(uint32_t n) { static void printn(uint32_t n) {
char buf[16], *p; char buf[16], *p;
if (!n) if (!n)
chIOPut(&SD2, '0'); chSequentialStreamPut(&SD2, '0');
else { else {
p = buf; p = buf;
while (n) while (n)
*p++ = (n % 10) + '0', n /= 10; *p++ = (n % 10) + '0', n /= 10;
while (p > buf) while (p > buf)
chIOPut(&SD2, *--p); chSequentialStreamPut(&SD2, *--p);
} }
} }

10
testhal/STM32F4xx/IRQ_STORM/main.c
View File

@ -170,29 +170,29 @@ static const GPTConfig gpt3cfg = {
static void print(char *p) { static void print(char *p) {
while (*p) { while (*p) {
chIOPut(&SD2, *p++); chSequentialStreamPut(&SD2, *p++);
} }
} }
static void println(char *p) { static void println(char *p) {
while (*p) { while (*p) {
chIOPut(&SD2, *p++); chSequentialStreamPut(&SD2, *p++);
} }
chIOWriteTimeout(&SD2, (uint8_t *)"\r\n", 2, TIME_INFINITE); chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2);
} }
static void printn(uint32_t n) { static void printn(uint32_t n) {
char buf[16], *p; char buf[16], *p;
if (!n) if (!n)
chIOPut(&SD2, '0'); chSequentialStreamPut(&SD2, '0');
else { else {
p = buf; p = buf;
while (n) while (n)
*p++ = (n % 10) + '0', n /= 10; *p++ = (n % 10) + '0', n /= 10;
while (p > buf) while (p > buf)
chIOPut(&SD2, *--p); chSequentialStreamPut(&SD2, *--p);
} }
} }

2
testhal/STM32L1xx/ADC/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

2
testhal/STM32L1xx/EXT/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

2
testhal/STM32L1xx/GPT/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

2
testhal/STM32L1xx/IRQ_STORM/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

2
testhal/STM32L1xx/IRQ_STORM/readme.txt
View File

@ -1,5 +1,5 @@
***************************************************************************** *****************************************************************************
** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32L1xx. ** ** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32L1xx. **
***************************************************************************** *****************************************************************************
** TARGET ** ** TARGET **

2
testhal/STM32L1xx/PVD/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

2
testhal/STM32L1xx/PWM-ICU/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

2
testhal/STM32L1xx/SPI/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.

2
testhal/STM32L1xx/UART/mcuconf.h
View File

@ -86,6 +86,8 @@
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
/* /*
* GPT driver system settings. * GPT driver system settings.