rusefi
/
ChibiOS
mirror of https://github.com/rusefi/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5357 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-03-04 15:11:20 +00:00
parent 9ddf162200
commit 43391f094a
4 changed files with 279 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
View File

@ -82,6 +82,7 @@ CH_IRQ_HANDLER(vector11) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 0; EDMA.CIRQR.R = 0;
if (channels[0] != NULL)
channels[0]->dma_func(0, channels[0]->dma_param); channels[0]->dma_func(0, channels[0]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -100,6 +101,7 @@ CH_IRQ_HANDLER(vector12) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 1; EDMA.CIRQR.R = 1;
if (channels[1] != NULL)
channels[1]->dma_func(1, channels[1]->dma_param); channels[1]->dma_func(1, channels[1]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -118,6 +120,7 @@ CH_IRQ_HANDLER(vector13) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 2; EDMA.CIRQR.R = 2;
if (channels[2] != NULL)
channels[2]->dma_func(2, channels[2]->dma_param); channels[2]->dma_func(2, channels[2]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -136,6 +139,7 @@ CH_IRQ_HANDLER(vector14) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 3; EDMA.CIRQR.R = 3;
if (channels[3] != NULL)
channels[3]->dma_func(3, channels[3]->dma_param); channels[3]->dma_func(3, channels[3]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -154,6 +158,7 @@ CH_IRQ_HANDLER(vector15) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 4; EDMA.CIRQR.R = 4;
if (channels[4] != NULL)
channels[4]->dma_func(4, channels[4]->dma_param); channels[4]->dma_func(4, channels[4]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -172,6 +177,7 @@ CH_IRQ_HANDLER(vector16) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 5; EDMA.CIRQR.R = 5;
if (channels[5] != NULL)
channels[5]->dma_func(5, channels[5]->dma_param); channels[5]->dma_func(5, channels[5]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -190,6 +196,7 @@ CH_IRQ_HANDLER(vector17) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 6; EDMA.CIRQR.R = 6;
if (channels[6] != NULL)
channels[6]->dma_func(6, channels[6]->dma_param); channels[6]->dma_func(6, channels[6]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -208,6 +215,7 @@ CH_IRQ_HANDLER(vector18) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 7; EDMA.CIRQR.R = 7;
if (channels[7] != NULL)
channels[7]->dma_func(7, channels[7]->dma_param); channels[7]->dma_func(7, channels[7]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -226,6 +234,7 @@ CH_IRQ_HANDLER(vector19) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 8; EDMA.CIRQR.R = 8;
if (channels[8] != NULL)
channels[8]->dma_func(8, channels[8]->dma_param); channels[8]->dma_func(8, channels[8]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -244,6 +253,7 @@ CH_IRQ_HANDLER(vector20) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 9; EDMA.CIRQR.R = 9;
if (channels[9] != NULL)
channels[9]->dma_func(9, channels[9]->dma_param); channels[9]->dma_func(9, channels[9]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -262,6 +272,7 @@ CH_IRQ_HANDLER(vector21) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 10; EDMA.CIRQR.R = 10;
if (channels[10] != NULL)
channels[10]->dma_func(10, channels[10]->dma_param); channels[10]->dma_func(10, channels[10]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -280,6 +291,7 @@ CH_IRQ_HANDLER(vector22) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 11; EDMA.CIRQR.R = 11;
if (channels[11] != NULL)
channels[11]->dma_func(11, channels[11]->dma_param); channels[11]->dma_func(11, channels[11]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -298,6 +310,7 @@ CH_IRQ_HANDLER(vector23) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 12; EDMA.CIRQR.R = 12;
if (channels[12] != NULL)
channels[12]->dma_func(12, channels[12]->dma_param); channels[12]->dma_func(12, channels[12]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -316,6 +329,7 @@ CH_IRQ_HANDLER(vector24) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 13; EDMA.CIRQR.R = 13;
if (channels[13] != NULL)
channels[13]->dma_func(13, channels[13]->dma_param); channels[13]->dma_func(13, channels[13]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -334,6 +348,7 @@ CH_IRQ_HANDLER(vector25) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 14; EDMA.CIRQR.R = 14;
if (channels[14] != NULL)
channels[14]->dma_func(14, channels[14]->dma_param); channels[14]->dma_func(14, channels[14]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -352,6 +367,7 @@ CH_IRQ_HANDLER(vector26) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 15; EDMA.CIRQR.R = 15;
if (channels[15] != NULL)
channels[15]->dma_func(15, channels[15]->dma_param); channels[15]->dma_func(15, channels[15]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -371,6 +387,7 @@ CH_IRQ_HANDLER(vector27) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 16; EDMA.CIRQR.R = 16;
if (channels[16] != NULL)
channels[16]->dma_func(16, channels[16]->dma_param); channels[16]->dma_func(16, channels[16]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -389,6 +406,7 @@ CH_IRQ_HANDLER(vector28) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 17; EDMA.CIRQR.R = 17;
if (channels[17] != NULL)
channels[17]->dma_func(17, channels[17]->dma_param); channels[17]->dma_func(17, channels[17]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -407,6 +425,7 @@ CH_IRQ_HANDLER(vector29) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 18; EDMA.CIRQR.R = 18;
if (channels[18] != NULL)
channels[18]->dma_func(18, channels[18]->dma_param); channels[18]->dma_func(18, channels[18]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -425,6 +444,7 @@ CH_IRQ_HANDLER(vector30) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 19; EDMA.CIRQR.R = 19;
if (channels[19] != NULL)
channels[19]->dma_func(19, channels[19]->dma_param); channels[19]->dma_func(19, channels[19]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -443,6 +463,7 @@ CH_IRQ_HANDLER(vector31) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 20; EDMA.CIRQR.R = 20;
if (channels[20] != NULL)
channels[20]->dma_func(20, channels[20]->dma_param); channels[20]->dma_func(20, channels[20]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -461,6 +482,7 @@ CH_IRQ_HANDLER(vector32) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 21; EDMA.CIRQR.R = 21;
if (channels[21] != NULL)
channels[21]->dma_func(21, channels[21]->dma_param); channels[21]->dma_func(21, channels[21]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -479,6 +501,7 @@ CH_IRQ_HANDLER(vector33) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 22; EDMA.CIRQR.R = 22;
if (channels[22] != NULL)
channels[22]->dma_func(22, channels[22]->dma_param); channels[22]->dma_func(22, channels[22]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -497,6 +520,7 @@ CH_IRQ_HANDLER(vector34) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 23; EDMA.CIRQR.R = 23;
if (channels[23] != NULL)
channels[23]->dma_func(23, channels[23]->dma_param); channels[23]->dma_func(23, channels[23]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -515,6 +539,7 @@ CH_IRQ_HANDLER(vector35) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 24; EDMA.CIRQR.R = 24;
if (channels[24] != NULL)
channels[24]->dma_func(24, channels[24]->dma_param); channels[24]->dma_func(24, channels[24]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -533,6 +558,7 @@ CH_IRQ_HANDLER(vector36) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 25; EDMA.CIRQR.R = 25;
if (channels[25] != NULL)
channels[25]->dma_func(25, channels[25]->dma_param); channels[25]->dma_func(25, channels[25]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -551,6 +577,7 @@ CH_IRQ_HANDLER(vector37) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 26; EDMA.CIRQR.R = 26;
if (channels[26] != NULL)
channels[26]->dma_func(26, channels[26]->dma_param); channels[26]->dma_func(26, channels[26]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -569,6 +596,7 @@ CH_IRQ_HANDLER(vector38) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 27; EDMA.CIRQR.R = 27;
if (channels[27] != NULL)
channels[27]->dma_func(27, channels[27]->dma_param); channels[27]->dma_func(27, channels[27]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -587,6 +615,7 @@ CH_IRQ_HANDLER(vector39) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 28; EDMA.CIRQR.R = 28;
if (channels[28] != NULL)
channels[28]->dma_func(28, channels[28]->dma_param); channels[28]->dma_func(28, channels[28]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -605,6 +634,7 @@ CH_IRQ_HANDLER(vector40) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 29; EDMA.CIRQR.R = 29;
if (channels[29] != NULL)
channels[29]->dma_func(29, channels[29]->dma_param); channels[29]->dma_func(29, channels[29]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -623,6 +653,7 @@ CH_IRQ_HANDLER(vector41) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 30; EDMA.CIRQR.R = 30;
if (channels[30] != NULL)
channels[30]->dma_func(30, channels[30]->dma_param); channels[30]->dma_func(30, channels[30]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -641,6 +672,7 @@ CH_IRQ_HANDLER(vector42) {
SPC5_EDMA_ERROR_HANDLER(); SPC5_EDMA_ERROR_HANDLER();
} }
EDMA.CIRQR.R = 31; EDMA.CIRQR.R = 31;
if (channels[31] != NULL)
channels[31]->dma_func(31, channels[31]->dma_param); channels[31]->dma_func(31, channels[31]->dma_param);
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -680,7 +712,8 @@ void edmaInit(void) {
edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) { edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
edma_channel_t channel; edma_channel_t channel;
chDbgCheck((ccfg != NULL) && ((ccfg->dma_priority & 15) < 16) && chDbgCheck((ccfg != NULL) && ((ccfg->dma_prio & 15) < 16) &&
(ccfg->dma_irq_prio < 16) &&
(ccfg->dma_func != NULL) && (ccfg->dma_error_func != NULL), (ccfg->dma_func != NULL) && (ccfg->dma_error_func != NULL),
"edmaChannelAllocate"); "edmaChannelAllocate");

4
os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
View File

@ -94,8 +94,10 @@ typedef void (*edma_callback_t)(edma_channel_t channel, void *p);
typedef struct { typedef struct {
uint8_t dma_periph; /**< @brief Peripheral to be uint8_t dma_periph; /**< @brief Peripheral to be
associated to the channel. */ associated to the channel. */
uint8_t dma_priority; /**< @brief Priority register value uint8_t dma_prio; /**< @brief Priority register value
for this channel. */ for this channel. */
uint8_t dma_irq_prio; /**< @brief IRQ priority level for
this channel. */
edma_callback_t dma_func; /**< @brief Channel callback. */ edma_callback_t dma_func; /**< @brief Channel callback. */
edma_callback_t dma_error_func; /**< @brief Channel error callback. */ edma_callback_t dma_error_func; /**< @brief Channel error callback. */
void *dma_param; /**< @brief Channel callback param. */ void *dma_param; /**< @brief Channel callback param. */

125
os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
View File

@ -25,6 +25,11 @@
#if HAL_USE_ADC || defined(__DOXYGEN__) #if HAL_USE_ADC || defined(__DOXYGEN__)
/* Some forward declarations.*/
static void adc_serve_rfifo_irq(edma_channel_t channel, void *p);
static void adc_serve_rfifo_error_irq(edma_channel_t channel, void *p);
static void adc_serve_cfifo_error_irq(edma_channel_t channel, void *p);
/*===========================================================================*/ /*===========================================================================*/
/* Driver local definitions. */ /* Driver local definitions. */
/*===========================================================================*/ /*===========================================================================*/
@ -87,6 +92,42 @@ ADCDriver ADCD6;
static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR; static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR;
#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__)
/**
* @brief DMA configuration for EQADC CFIFO0.
*/
static const edma_channel_config_t adc_cfifo0_dma_config = {
0, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC0_FIFO0_DMA_IRQ_PRIO,
NULL, adc_serve_cfifo_error_irq, NULL
};
/**
* @brief DMA configuration for EQADC RFIFO0.
*/
static const edma_channel_config_t adc_rfifo0_dma_config = {
1, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC0_FIFO0_DMA_IRQ_PRIO,
adc_serve_rfifo_irq, adc_serve_rfifo_error_irq, NULL
};
#endif /* SPC5_ADC_USE_ADC0_Q3 */
#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__)
/**
* @brief DMA configuration for EQADC CFIFO3.
*/
static const edma_channel_config_t adc_cfifo3_dma_config = {
0, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC0_FIFO3_DMA_IRQ_PRIO,
NULL, adc_serve_cfifo_error_irq, NULL
};
/**
* @brief DMA configuration for EQADC RFIFO3.
*/
static const edma_channel_config_t adc_rfifo3_dma_config = {
1, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC0_FIFO3_DMA_IRQ_PRIO,
adc_serve_rfifo_irq, adc_serve_rfifo_error_irq, NULL
};
#endif /* SPC5_ADC_USE_ADC1_Q3 */
/*===========================================================================*/ /*===========================================================================*/
/* Driver local functions and macros. */ /* Driver local functions and macros. */
/*===========================================================================*/ /*===========================================================================*/
@ -267,6 +308,48 @@ static void adc_setup_resistors(uint32_t adc) {
adc_write_register(adc, ADC_REG_PUDCR(i), pudcrs[i]); adc_write_register(adc, ADC_REG_PUDCR(i), pudcrs[i]);
} }
/**
* @brief Shared ISR for RFIFO DMA events.
*
* @param[in] channel the channel number
* @param[in] p parameter for the registered function
*
* @notapi
*/
static void adc_serve_rfifo_irq(edma_channel_t channel, void *p) {
(void)channel;
(void)p;
}
/**
* @brief Shared ISR for RFIFO DMA error events.
*
* @param[in] channel the channel number
* @param[in] p parameter for the registered function
*
* @notapi
*/
static void adc_serve_rfifo_error_irq(edma_channel_t channel, void *p) {
(void)channel;
(void)p;
}
/**
* @brief Shared ISR for CFIFO DMA error events.
*
* @param[in] channel the channel number
* @param[in] p parameter for the registered function
*
* @notapi
*/
static void adc_serve_cfifo_error_irq(edma_channel_t channel, void *p) {
(void)channel;
(void)p;
}
/*===========================================================================*/ /*===========================================================================*/
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
@ -282,11 +365,20 @@ static void adc_setup_resistors(uint32_t adc) {
*/ */
void adc_lld_init(void) { void adc_lld_init(void) {
#if SPC5_ADC_USE_EQADC_Q0 #if SPC5_ADC_USE_ADC0_Q0
/* Driver initialization.*/ /* Driver initialization.*/
adcObjectInit(&ADCD1); adcObjectInit(&ADCD1);
ADCD1.cfifo_channel = EDMA_ERROR;
ADCD1.rfifo_channel = EDMA_ERROR;
#endif /* SPC5_ADC_USE_EQADC_Q0 */ #endif /* SPC5_ADC_USE_EQADC_Q0 */
#if SPC5_ADC_USE_ADC1_Q3
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.cfifo_channel = EDMA_ERROR;
ADCD1.rfifo_channel = EDMA_ERROR;
#endif /* SPC5_ADC_USE_ADC1_Q3 */
/* Temporarily enables CFIFO0 for calibration and initialization.*/ /* Temporarily enables CFIFO0 for calibration and initialization.*/
cfifo_enable(ADC_FIFO_0, EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWCS, 0); cfifo_enable(ADC_FIFO_0, EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWCS, 0);
adc_enable(); adc_enable();
@ -323,12 +415,24 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) { if (adcp->state == ADC_STOP) {
/* Enables the peripheral.*/ /* Enables the peripheral.*/
#if SPC5_ADC_USE_ADC0 #if SPC5_ADC_USE_ADC0_Q0
if (&ADCD1 == adcp) { if (&ADCD1 == adcp) {
adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo0_dma_config);
adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo0_dma_config);
} }
#endif /* SPC5_ADC_USE_EQADC_Q0 */ #endif /* SPC5_ADC_USE_EQADC_Q0 */
#if SPC5_ADC_USE_ADC1_Q3
if (&ADCD4 == adcp) {
adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo3_dma_config);
adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo3_dma_config);
} }
#endif /* SPC5_ADC_USE_ADC1_Q3 */
}
chDbgAssert((adcp->cfifo_channel != EDMA_ERROR) &&
(adcp->rfifo_channel != EDMA_ERROR),
"adc_lld_start(), #1", "channel cannot be allocated");
/* Configures the peripheral.*/ /* Configures the peripheral.*/
} }
@ -345,12 +449,19 @@ void adc_lld_stop(ADCDriver *adcp) {
if (adcp->state == ADC_READY) { if (adcp->state == ADC_READY) {
/* Resets the peripheral.*/ /* Resets the peripheral.*/
/* Disables the peripheral.*/ /* Releases the allocated EDMA channels.*/
#if SPC5_ADC_USE_ADC0 edmaChannelRelease(adcp->cfifo_channel);
if (&ADCD1 == adcp) { edmaChannelRelease(adcp->rfifo_channel);
/* Disables the peripheral.*/
#if SPC5_ADC_USE_ADC0_Q0
if (&ADCD1 == adcp) {
} }
#endif /* SPC5_ADC_USE_EQADC_Q0 */ #endif /* SPC5_ADC_USE_ADC0_Q0 */
#if SPC5_ADC_USE_ADC1_Q3
if (&ADCD1 == adcp) {
}
#endif /* SPC5_ADC_USE_ADC1_Q3 */
} }
} }

93
os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
View File

@ -255,7 +255,90 @@
#endif #endif
/** /**
* * @brief EQADC CFIFO0 and RFIFO0 DMA priority.
*/
#if !defined(SPC5_ADC_FIFO0_DMA_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC_FIFO0_DMA_PRIO 12
#endif
/**
* @brief EQADC CFIFO1 and RFIFO1 DMA priority.
*/
#if !defined(SPC5_ADC_FIFO1_DMA_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC_FIFO1_DMA_PRIO 12
#endif
/**
* @brief EQADC CFIFO2 and RFIFO2 DMA priority.
*/
#if !defined(SPC5_ADC_FIFO2_DMA_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC_FIFO2_DMA_PRIO 12
#endif
/**
* @brief EQADC CFIFO3 and RFIFO3 DMA priority.
*/
#if !defined(SPC5_ADC_FIFO3_DMA_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC_FIFO3_DMA_PRIO 12
#endif
/**
* @brief EQADC CFIFO4 and RFIFO4 DMA priority.
*/
#if !defined(SPC5_ADC_FIFO4_DMA_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC_FIFO4_DMA_PRIO 12
#endif
/**
* @brief EQADC CFIFO5 and RFIFO5 DMA priority.
*/
#if !defined(SPC5_ADC_FIFO5_DMA_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC_FIFO5_DMA_PRIO 12
#endif
/**
* @brief EQADC CFIFO0 and RFIFO0 DMA IRQ priority.
*/
#if !defined(SPC5_ADC0_FIFO0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC0_FIFO0_DMA_IRQ_PRIO 12
#endif
/**
* @brief EQADC CFIFO1 and RFIFO1 DMA IRQ priority.
*/
#if !defined(SPC5_ADC0_FIFO1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC0_FIFO1_DMA_IRQ_PRIO 12
#endif
/**
* @brief EQADC CFIFO2 and RFIFO2 DMA IRQ priority.
*/
#if !defined(SPC5_ADC0_FIFO2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC0_FIFO2_DMA_IRQ_PRIO 12
#endif
/**
* @brief EQADC CFIFO3 and RFIFO3 DMA IRQ priority.
*/
#if !defined(SPC5_ADC0_FIFO3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC0_FIFO3_DMA_IRQ_PRIO 12
#endif
/**
* @brief EQADC CFIFO4 and RFIFO4 DMA IRQ priority.
*/
#if !defined(SPC5_ADC0_FIFO4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC0_FIFO4_DMA_IRQ_PRIO 12
#endif
/**
* @brief EQADC CFIFO5 and RFIFO5 DMA IRQ priority.
*/
#if !defined(SPC5_ADC0_FIFO5_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
#define SPC5_ADC0_FIFO5_DMA_IRQ_PRIO 12
#endif
/**
* @brief EQADC clock prescaler value. * @brief EQADC clock prescaler value.
*/ */
#if !defined(SPC5_ADC_CR_CLK_PS) || defined(__DOXYGEN__) #if !defined(SPC5_ADC_CR_CLK_PS) || defined(__DOXYGEN__)
@ -447,6 +530,14 @@ struct ADCDriver {
ADC_DRIVER_EXT_FIELDS ADC_DRIVER_EXT_FIELDS
#endif #endif
/* End of the mandatory fields.*/ /* End of the mandatory fields.*/
/**
* @brief EDMA channel used for the CFIFO.
*/
edma_channel_t cfifo_channel;
/**
* @brief EDMA channel used for the RFIFO.
*/
edma_channel_t rfifo_channel;
}; };
/*===========================================================================*/ /*===========================================================================*/