mirror of https://github.com/rusefi/ChibiOS.git
Fixed SPI interruption enable, driver restart with different configuration.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10522 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Theodore Ateba
parent
f0dd706419
commit
4658591470
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@ -15,7 +15,7 @@
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*/
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/**
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* @file hal_spi_lld.c
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* @file AVR/hal_spi_lld.c
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* @brief AVR SPI subsystem low level driver source.
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*
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* @addtogroup SPI
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@ -111,8 +111,6 @@ void spi_lld_start(SPIDriver *spip) {
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uint8_t dummy;
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/* Configures the peripheral.*/
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if (spip->state == SPI_STOP) {
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/* Enables the peripheral.*/
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#if AVR_SPI_USE_SPI1
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@ -123,75 +121,29 @@ void spi_lld_start(SPIDriver *spip) {
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#elif defined(PRR)
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PRR &= ~(1 << PRSPI);
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#endif
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/* SPI enable, SPI interrupt enable */
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SPCR |= ((1 << SPE) | (1 << SPIE));
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SPCR |= (1 << MSTR);
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DDR_SPI1 |= ((1 << SPI1_MOSI) | (1 << SPI1_SCK));
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DDR_SPI1 &= ~(1 << SPI1_MISO);
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spip->config->ssport->dir |= (1 << spip->config->sspad);
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switch (spip->config->bitorder) {
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case SPI_LSB_FIRST:
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SPCR |= (1 << DORD);
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break;
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case SPI_MSB_FIRST: /* fallthrough */
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default:
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SPCR &= ~(1 << DORD);
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break;
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}
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SPCR &= ~((1 << CPOL) | (1 << CPHA));
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switch (spip->config->mode) {
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case SPI_MODE_1:
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SPCR |= (1 << CPHA);
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break;
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case SPI_MODE_2:
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SPCR |= (1 << CPOL);
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break;
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case SPI_MODE_3:
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SPCR |= ((1 << CPOL) | (1 << CPHA));
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break;
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case SPI_MODE_0: /* fallthrough */
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default: break;
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}
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SPCR &= ~((1 << SPR1) | (1 << SPR0));
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SPSR &= ~(1 << SPI2X);
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switch (spip->config->clockrate) {
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case SPI_SCK_FOSC_2:
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SPSR |= (1 << SPI2X);
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break;
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case SPI_SCK_FOSC_8:
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SPSR |= (1 << SPI2X);
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SPCR |= (1 << SPR0);
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break;
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case SPI_SCK_FOSC_16:
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SPCR |= (1 << SPR0);
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break;
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case SPI_SCK_FOSC_32:
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SPSR |= (1 << SPI2X);
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SPCR |= (1 << SPR1);
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break;
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case SPI_SCK_FOSC_64:
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SPCR |= (1 << SPR1);
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break;
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case SPI_SCK_FOSC_128:
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SPCR |= ((1 << SPR1) | (1 << SPR0));
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break;
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case SPI_SCK_FOSC_4: /* fallthrough */
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default: break;
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}
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/* dummy reads before enabling interrupt */
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dummy = SPSR;
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dummy = SPDR;
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(void) dummy; /* suppress warning about unused variable */
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SPCR |= (1 << SPIE);
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#endif
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}
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#endif /* AVR_SPI_USE_SPI1 */
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}
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#if AVR_SPI_USE_SPI1
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if (&SPID1 == spip) {
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/* Configures the peripheral.*/
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/* Note that some bits are forced:
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SPI interrupt disabled,
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SPI enabled,
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SPI master enabled */
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SPCR = (spip->config->spcr & ~(SPI_CR_SPIE)) | SPI_CR_MSTR | SPI_CR_SPE;
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SPSR = spip->config->spsr;
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/* dummy reads before enabling interrupt */
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dummy = SPSR;
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dummy = SPDR;
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(void) dummy; /* suppress warning about unused variable */
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/* Enable SPI interrupts */
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SPCR |= SPI_CR_SPIE;
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}
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#endif /* AVR_SPI_USE_SPI1 */
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}
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/**
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@ -209,8 +161,7 @@ void spi_lld_stop(SPIDriver *spip) {
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/* Disables the peripheral.*/
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#if AVR_SPI_USE_SPI1
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if (&SPID1 == spip) {
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SPCR &= ((1 << SPIE) | (1 << SPE));
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spip->config->ssport->dir &= ~(1 << spip->config->sspad);
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SPCR &= (SPI_CR_SPIE | SPI_CR_SPE);
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}
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/* Disable SPI clock using Power Reduction Register */
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#if defined(PRR0)
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@ -298,22 +249,23 @@ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
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uint16_t spdr = 0;
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uint8_t dummy;
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(void)spip;
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/* disable interrupt */
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SPCR &= ~(1 << SPIE);
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SPCR &= ~(SPI_CR_SPIE);
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SPDR = frame >> 8;
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while (!(SPSR & (1 << SPIF))) ;
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while (!(SPSR & SPI_SR_SPIF)) ;
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spdr = SPDR << 8;
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SPDR = frame & 0xFF;
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while (!(SPSR & (1 << SPIF))) ;
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while (!(SPSR & SPI_SR_SPIF)) ;
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spdr |= SPDR;
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dummy = SPSR;
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dummy = SPDR;
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(void) dummy; /* suppress warning about unused variable */
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SPCR |= (1 << SPIE);
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SPCR |= SPI_CR_SPIE;
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return spdr;
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}
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@ -322,18 +274,19 @@ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) {
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uint8_t spdr = 0;
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uint8_t dummy;
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(void)spip;
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/* disable interrupt */
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SPCR &= ~(1 << SPIE);
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SPCR &= ~(SPI_CR_SPIE);
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SPDR = frame;
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while (!(SPSR & (1 << SPIF))) ;
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while (!(SPSR & SPI_SR_SPIF)) ;
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spdr = SPDR;
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dummy = SPSR;
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dummy = SPDR;
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(void) dummy; /* suppress warning about unused variable */
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SPCR |= (1 << SPIE);
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SPCR |= SPI_CR_SPIE;
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return spdr;
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}
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@ -15,7 +15,7 @@
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*/
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/**
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* @file hal_spi_lld.h
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* @file AVR/hal_spi_lld.h
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* @brief AVR SPI subsystem low level driver header.
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*
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* @addtogroup SPI
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@ -31,29 +31,46 @@
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/* Driver constants. */
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/*===========================================================================*/
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/** @brief SPI Mode (Polarity/Phase) */
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#define SPI_CPOL0_CPHA0 0
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#define SPI_CPOL0_CPHA1 1
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#define SPI_CPOL1_CPHA0 2
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#define SPI_CPOL1_CPHA1 3
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/**
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* @name SPI Configuration Register
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* @{
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*/
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#define SPI_CR_SPIE (1 << SPIE)
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#define SPI_MODE_0 SPI_CPOL0_CPHA0
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#define SPI_MODE_1 SPI_CPOL0_CPHA1
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#define SPI_MODE_2 SPI_CPOL1_CPHA0
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#define SPI_MODE_3 SPI_CPOL1_CPHA1
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#define SPI_CR_SPE (1 << SPE)
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/** @brief Bit order */
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#define SPI_LSB_FIRST 0
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#define SPI_MSB_FIRST 1
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#define SPI_CR_DORD_MSB_FIRST (0 << DORD)
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#define SPI_CR_DORD_LSB_FIRST (1 << DORD)
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/** @brief SPI clock rate FOSC/x */
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#define SPI_SCK_FOSC_2 0
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#define SPI_SCK_FOSC_4 1
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#define SPI_SCK_FOSC_8 2
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#define SPI_SCK_FOSC_16 3
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#define SPI_SCK_FOSC_32 4
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#define SPI_SCK_FOSC_64 5
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#define SPI_SCK_FOSC_128 6
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#define SPI_CR_MSTR (1 << MSTR)
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#define SPI_CR_CPOL_CPHA_MODE(n) ((n) << CPHA)
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#define SPI_CR_SCK_FOSC_2 (0 << SPR0)
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#define SPI_CR_SCK_FOSC_4 (0 << SPR0)
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#define SPI_CR_SCK_FOSC_8 (1 << SPR0)
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#define SPI_CR_SCK_FOSC_16 (1 << SPR0)
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#define SPI_CR_SCK_FOSC_32 (2 << SPR0)
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#define SPI_CR_SCK_FOSC_64 (2 << SPR0)
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#define SPI_CR_SCK_FOSC_128 (3 << SPR0)
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/** @} */
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/**
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* @name SPI Status Register
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* {
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*/
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#define SPI_SR_SPIF (1 << SPIF)
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#define SPI_SR_WCOL (1 << WCOL)
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#define SPI_SR_SCK_FOSC_2 (1 << SPI2X)
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#define SPI_SR_SCK_FOSC_4 (0 << SPI2X)
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#define SPI_SR_SCK_FOSC_8 (1 << SPI2X)
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#define SPI_SR_SCK_FOSC_16 (0 << SPI2X)
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#define SPI_SR_SCK_FOSC_32 (1 << SPI2X)
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#define SPI_SR_SCK_FOSC_64 (0 << SPI2X)
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#define SPI_SR_SCK_FOSC_128 (0 << SPI2X)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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@ -68,7 +85,7 @@
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* @details If set to @p TRUE the support for SPI1 is included.
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*/
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#if !defined(AVR_SPI_USE_SPI1) || defined(__DOXYGEN__)
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#define AVR_SPI_USE_SPI1 FALSE
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#define AVR_SPI_USE_SPI1 FALSE
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#endif
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/** @} */
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@ -99,6 +116,11 @@ typedef void (*spicallback_t)(SPIDriver *spip);
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* architecture dependent, fields.
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*/
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typedef struct {
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/**
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* @brief Operation complete callback.
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*/
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spicallback_t end_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief Port used of Slave Select
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*/
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@ -108,22 +130,13 @@ typedef struct {
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*/
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uint8_t sspad;
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/**
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* @brief Polarity/Phase mode
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* @brief SPI Control Register initialization data.
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*/
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uint8_t mode;
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uint8_t spcr;
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/**
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* @brief Use MSB/LSB first?
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* @brief SPI Status Register initialization data.
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*/
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uint8_t bitorder;
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/**
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* @brief Clock rate of the subsystem
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*/
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uint8_t clockrate;
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/**
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* @brief Operation complete callback.
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*/
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spicallback_t end_cb;
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/* End of the mandatory fields.*/
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uint8_t spsr;
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} SPIConfig;
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/**
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