mirror of https://github.com/rusefi/ChibiOS.git
Documentation related changes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2293 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
acbea2f1f3
commit
487a81e297
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@ -19,21 +19,21 @@
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/**
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* @defgroup AT91SAM7 AT91SAM7 Drivers
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* @brief AT91SAM7 specific support.
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* @details This section describes all the supported drivers on the AT91SAM7
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* platform and the implementation details of the single drivers.
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*
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* @ingroup platforms
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*/
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/**
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* @defgroup AT91SAM7_HAL AT91SAM7 HAL Support
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* @brief HAL support.
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* @defgroup AT91SAM7_HAL AT91SAM7 Initialization Support
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* @details The AT91SAM7 HAL support is responsible for system initialization.
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*
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* @section at91sam7_hal_1 Supported HW resources
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* - MC.
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* - PMC.
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* .
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* @section at91sam7_hal_2 STM32 HAL driver implementation features
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* @section at91sam7_hal_2 AT91SAM7 HAL driver implementation features
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* - PLLs startup and stabilization.
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* - Clock source selection.
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* - Flash wait states.
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@ -43,8 +43,7 @@
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/**
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* @defgroup AT91SAM7_MAC AT91SAM7 EMAC Support
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* @brief EMAC+PHY peripheral support.
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* @details This driver supports the AT91SAM7 EMAC peripheral.
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* @details The AT91SAM7 MAC driver supports the EMAC peripheral.
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*
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* @section at91sam7_mac_1 Supported HW resources
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* - EMAC.
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@ -54,17 +53,17 @@
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/**
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* @defgroup AT91SAM7_MII AT91SAM7 MII Support
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* @brief PHY peripheral support.
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* @details This driver supports the AT91SAM7 EMAC peripheral communicating
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* with an external PHY transceiver. The driver currently supports
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* the Micrel KS8721 PHY and the Davicom DV9161 modules.
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* the Micrel KS8721 PHY and the Davicom DV9161 modules. This driver
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* is used internally by the MAC driver.
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*
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* @ingroup AT91SAM7
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*/
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/**
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* @defgroup AT91SAM7_PAL AT91SAM7 PIO Support
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* @brief I/O Ports peripherals support.
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* @details The AT91SAM7 PAL driver supports the PIO peripherals.
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*
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* @section at91sam7_pal_1 Supported HW resources
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* - PIOA.
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@ -91,8 +90,8 @@
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* Any attempt to setup an invalid mode is ignored.
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*
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* @section at91sam7_pal_4 Suboptimal behavior
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* The STM32 PIO is less than optimal in several areas, the limitations should
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* be taken in account while using the PAL driver:
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* The AT91SAM7 PIO is less than optimal in several areas, the limitations
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* should be taken in account while using the PAL driver:
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* - Pad/port toggling operations are not atomic.
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* - Pad/group mode setup is not atomic.
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* .
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@ -101,9 +100,8 @@
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/**
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* @defgroup AT91SAM7_SPI AT91SAM7 SPI Support
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* @brief SPI peripheral support.
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* @details The SPI driver supports the AT91SAM7 SPIs using DMA channels for
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* improved performance.
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* @details The SPI driver supports the AT91SAM7 SPI peripherals using DMA
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* channels for maximum performance.
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*
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* @section at91sam7_spi_1 Supported HW resources
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* - SPI1.
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@ -121,8 +119,8 @@
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/**
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* @defgroup AT91SAM7_SERIAL AT91SAM7 USART Support (buffered)
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* @brief USART peripherals support.
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* @details The serial driver supports the AT91SAM7 USART peripherals.
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* @details The AT91SAM7 Serial driver uses the USART/UART peripherals in a
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* buffered, interrupt driven, implementation.
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*
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* @section at91sam7_serial_1 Supported HW resources
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* The serial driver can support any of the following hardware resources:
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* @file AVR/hal_lld.c
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* @brief AVR HAL subsystem low level driver code.
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*
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* @addtogroup AVR_HAL
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* @addtogroup HAL
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* @{
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*/
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@ -21,7 +21,7 @@
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* @file AVR/hal_lld.h
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* @brief AVR HAL subsystem low level driver header.
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*
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* @addtogroup AVR_HAL
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* @addtogroup HAL
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* @{
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*/
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@ -19,23 +19,34 @@
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/**
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* @defgroup AVR_DRIVERS AVR Drivers
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* @brief AVR specific support.
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* @details This section describes all the supported drivers on the AVR
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* platform and the implementation details of the single drivers.
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*
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* @ingroup platforms
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*/
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/**
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* @defgroup AVR_HAL AVR HAL Support
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* @brief HAL support.
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* @defgroup AVR_HAL AVR Initialization Support
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* @details On the AVR platform the HAL driver is a stub and does not perform
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* any platform-specific initialization, it still performs the
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* initialization of the other drivers.
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*
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* @ingroup AVR_DRIVERS
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*/
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/**
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* @defgroup AVR_SERIAL AVR USART Support
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* @brief USART support.
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* @details The serial driver supports both the AVR USARTs in asynchronous
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* mode.
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* @defgroup AVR_SERIAL AVR USART Support (buffered)
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* @details The AVR Serial driver uses the USART peripherals in a
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* buffered, interrupt driven, implementation.
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*
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* @section avr_serial_1 Supported HW resources
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* The serial driver can support any of the following hardware resources:
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* - USART0.
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* - USART1.
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* .
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* @section avr_serial_2 AVR Serial driver implementation features
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* - Each USART can be independently enabled and programmed.
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* - Fully interrupt driven.
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* .
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* @ingroup AVR_DRIVERS
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*/
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* @file AVR/serial_lld.c
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* @brief AVR low level serial driver code.
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*
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* @addtogroup AVR_SERIAL
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* @addtogroup SERIAL
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* @{
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*/
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* @file AVR/serial_lld.h
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* @brief AVR low level serial driver header.
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*
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* @addtogroup AVR_SERIAL
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* @addtogroup SERIAL
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* @{
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*/
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* @file LPC11xx/hal_lld.c
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* @brief LPC11xx HAL subsystem low level driver source.
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*
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* @addtogroup LPC11xx_HAL
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* @addtogroup HAL
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* @{
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*/
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* @file LPC11xx/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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*
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* @addtogroup LPC11xx_HAL
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* @addtogroup HAL
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* @{
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*/
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* @file LPC11xx/pal_lld.c
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* @brief LPC11xx GPIO low level driver code.
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*
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* @addtogroup LPC11xx_PAL
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* @addtogroup PAL
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* @{
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*/
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* @file LPC11xx/pal_lld.h
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* @brief LPC11xx GPIO low level driver header.
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*
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* @addtogroup LPC11xx_PAL
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* @addtogroup PAL
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* @{
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*/
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/**
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* @defgroup LPC11xx LPC11xx Drivers
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* @brief LPC11xx specific support.
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* @details The LPC11xx support includes:
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* - I/O ports driver.
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* - Buffered, interrupt driven, serial driver.
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* - A demo supporting the kernel test suite.
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* .
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* @details This section describes all the supported drivers on the LPC11xx
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* platform and the implementation details of the single drivers.
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*
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* @ingroup platforms
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*/
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/**
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* @defgroup LPC11xx_HAL LPC11xx HAL Support
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* @brief HAL support.
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* @defgroup LPC11xx_HAL LPC11xx Initialization Support
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* @details The LPC11xx HAL support is responsible for system initialization.
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*
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* @section lpc11xx_hal_1 Supported HW resources
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* - SYSCON.
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* - Flash.
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* .
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* @section lpc11xx_hal_2 LPC11xx HAL driver implementation features
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* - Clock tree initialization.
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* - Clock source selection.
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* - Flash controller initialization.
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* - SYSTICK initialization based on current clock and kernel required rate.
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* .
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* @ingroup LPC11xx
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*/
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/**
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* @defgroup LPC11xx_PAL LPC11xx I/O Ports Support
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* @brief I/O Ports peripherals support.
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* @details This module supports the LPC11xx GPIO controller. The controller
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* supports the following features (see @ref PAL):
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* @defgroup LPC11xx_PAL LPC11xx GPIO Support
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* @details The LPC11xx PAL driver uses the GPIO peripherals.
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*
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* @section lpc11xx_pal_1 Supported HW resources
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* - GPIO0.
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* - GPIO1.
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* - GPIO2.
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* - GPIO3.
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* .
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* @section lpc11xx_pal_2 LPC11xx PAL driver implementation features
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* - 12 bits wide ports.
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* - Atomic set/reset functions.
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* - Atomic set+reset function (atomic bus operations).
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* - Output latched regardless of the pad setting.
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* - Direct read of input pads regardless of the pad setting.
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* .
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* <h2>Supported Setup Modes</h2>
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* @section lpc11xx_pal_3 Supported PAL setup modes
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* - @p PAL_MODE_RESET.
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* - @p PAL_MODE_UNCONNECTED.
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* - @p PAL_MODE_INPUT.
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* .
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* Any attempt to setup an invalid mode is ignored.
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*
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* <h2>Suboptimal Behavior</h2>
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* @section lpc11xx_pal_4 Suboptimal behavior
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* Some GPIO features are less than optimal:
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* - Pad/port toggling operations are not atomic.
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* - Pull-up and Pull-down resistors cannot be programmed through the PAL
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* driver and must be programmed separately.
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* driver and must be programmed separately using the IOCON peripheral.
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* - Reading of the output latch for pads programmed as input is not possible,
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* the input pin value is returned instead.
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* .
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*/
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/**
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* @defgroup LPC11xx_SERIAL LPC11xx UART Support
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* @brief UART peripherals support.
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* @details The serial driver supports the LPC11xx UART taking advantage of
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* its deep hardware buffers.
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* @defgroup LPC11xx_SPI LPC11xx SPI Support
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* @details The SPI driver supports the LPC11xx SSP peripherals in an interrupt
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* driven implementation.
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* @note Being the SPI a fast peripheral, much care must be taken to
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* not saturate the CPU bandwidth with an excessive IRQ rate. The
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* maximum transfer bit rate is likely limited by the IRQ
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* handling.
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*
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* @section lpc11xx_spi_1 Supported HW resources
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* - SSP0.
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* - SSP1 (where present).
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* .
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* @section lpc11xx_spi_2 LPC11xx SPI driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each SSP can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable interrupt priority levels for each SSP.
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* .
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* @ingroup LPC11xx
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*/
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/**
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* @defgroup LPC11xx_SERIAL LPC11xx UART Support (buffered)
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* @details The LPC11xx Serial driver uses the UART peripheral in a
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* buffered, interrupt driven, implementation. The serial driver
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* also takes advantage of the LPC11xx UARTs deep hardware buffers.
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*
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* @section lpc11xx_serial_1 Supported HW resources
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* The serial driver can support any of the following hardware resources:
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* - UART.
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* .
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* @section lpc11xx_serial_2 LPC11xx Serial driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Fully interrupt driven.
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* - Programmable priority level.
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* - Takes advantage of the input and output FIFOs.
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* .
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* @ingroup LPC11xx
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*/
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@ -21,7 +21,7 @@
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* @file LPC11xx/serial_lld.c
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* @brief LPC11xx low level serial driver code.
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*
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* @addtogroup LPC11xx_SERIAL
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* @addtogroup SERIAL
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* @{
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*/
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@ -21,7 +21,7 @@
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* @file LPC11xx/serial_lld.h
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* @brief LPC11xx low level serial driver header.
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*
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* @addtogroup LPC11xx_SERIAL
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* @addtogroup SERIAL
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* @{
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*/
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@ -21,7 +21,7 @@
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* @file LPC11xx/spi_lld.c
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* @brief LPC11xx low level SPI driver code.
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*
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* @addtogroup LPC11xx_SPI
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* @addtogroup SPI
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* @{
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*/
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@ -21,7 +21,7 @@
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* @file LPC11xx/spi_lld.h
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* @brief LPC11xx low level SPI driver header.
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*
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* @addtogroup LPC11xx_SPI
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* @addtogroup SPI
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* @{
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*/
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@ -21,7 +21,7 @@
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* @file LPC13xx/hal_lld.c
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* @brief LPC13xx HAL subsystem low level driver source.
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*
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* @addtogroup LPC13xx_HAL
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* @addtogroup HAL
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* @{
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*/
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|
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@ -21,7 +21,7 @@
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* @file LPC13xx/hal_lld.h
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* @brief HAL subsystem low level driver header template.
|
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*
|
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* @addtogroup LPC13xx_HAL
|
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* @addtogroup HAL
|
||||
* @{
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*/
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|
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@ -21,7 +21,7 @@
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* @file LPC13xx/pal_lld.c
|
||||
* @brief LPC13xx GPIO low level driver code.
|
||||
*
|
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* @addtogroup LPC13xx_PAL
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* @addtogroup PAL
|
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* @{
|
||||
*/
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||||
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||||
|
|
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@ -21,7 +21,7 @@
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|||
* @file LPC13xx/pal_lld.h
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* @brief LPC13xx GPIO low level driver header.
|
||||
*
|
||||
* @addtogroup LPC13xx_PAL
|
||||
* @addtogroup PAL
|
||||
* @{
|
||||
*/
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||||
|
||||
|
|
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@ -19,34 +19,47 @@
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/**
|
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* @defgroup LPC13xx LPC13xx Drivers
|
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* @brief LPC13xx specific support.
|
||||
* @details The LPC13xx support includes:
|
||||
* - I/O ports driver.
|
||||
* - Buffered, interrupt driven, serial driver.
|
||||
* - A demo supporting the kernel test suite.
|
||||
* .
|
||||
* @details This section describes all the supported drivers on the LPC13xx
|
||||
* platform and the implementation details of the single drivers.
|
||||
*
|
||||
* @ingroup platforms
|
||||
*/
|
||||
|
||||
/**
|
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* @defgroup LPC13xx_HAL LPC13xx HAL Support
|
||||
* @brief HAL support.
|
||||
* @defgroup LPC13xx_HAL LPC13xx Initialization Support
|
||||
* @details The LPC13xx HAL support is responsible for system initialization.
|
||||
*
|
||||
* @section lpc13xx_hal_1 Supported HW resources
|
||||
* - SYSCON.
|
||||
* - Flash.
|
||||
* .
|
||||
* @section lpc13xx_hal_2 LPC13xx HAL driver implementation features
|
||||
* - Clock tree initialization.
|
||||
* - Clock source selection.
|
||||
* - Flash controller initialization.
|
||||
* - SYSTICK initialization based on current clock and kernel required rate.
|
||||
* .
|
||||
* @ingroup LPC13xx
|
||||
*/
|
||||
|
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/**
|
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* @defgroup LPC13xx_PAL LPC13xx I/O Ports Support
|
||||
* @brief I/O Ports peripherals support.
|
||||
* @details This module supports the LPC13xx GPIO controller. The controller
|
||||
* supports the following features (see @ref PAL):
|
||||
* @defgroup LPC13xx_PAL LPC13xx GPIO Support
|
||||
* @details The LPC13xx PAL driver uses the GPIO peripherals.
|
||||
*
|
||||
* @section lpc13xx_pal_1 Supported HW resources
|
||||
* - GPIO0.
|
||||
* - GPIO1.
|
||||
* - GPIO2.
|
||||
* - GPIO3.
|
||||
* .
|
||||
* @section lpc13xx_pal_2 LPC13xx PAL driver implementation features
|
||||
* - 12 bits wide ports.
|
||||
* - Atomic set/reset functions.
|
||||
* - Atomic set+reset function (atomic bus operations).
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
* <h2>Supported Setup Modes</h2>
|
||||
* @section lpc13xx_pal_3 Supported PAL setup modes
|
||||
* - @p PAL_MODE_RESET.
|
||||
* - @p PAL_MODE_UNCONNECTED.
|
||||
* - @p PAL_MODE_INPUT.
|
||||
|
|
@ -54,11 +67,11 @@
|
|||
* .
|
||||
* Any attempt to setup an invalid mode is ignored.
|
||||
*
|
||||
* <h2>Suboptimal Behavior</h2>
|
||||
* @section lpc13xx_pal_4 Suboptimal behavior
|
||||
* Some GPIO features are less than optimal:
|
||||
* - Pad/port toggling operations are not atomic.
|
||||
* - Pull-up and Pull-down resistors cannot be programmed through the PAL
|
||||
* driver and must be programmed separately.
|
||||
* driver and must be programmed separately using the IOCON peripheral.
|
||||
* - Reading of the output latch for pads programmed as input is not possible,
|
||||
* the input pin value is returned instead.
|
||||
* .
|
||||
|
|
@ -66,10 +79,42 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC13xx_SERIAL LPC13xx UART Support
|
||||
* @brief UART peripherals support.
|
||||
* @details The serial driver supports the LPC13xx UART taking advantage of
|
||||
* its deep hardware buffers.
|
||||
* @defgroup LPC13xx_SPI LPC13xx SPI Support
|
||||
* @details The SPI driver supports the LPC13xx SSP peripherals in an interrupt
|
||||
* driven implementation.
|
||||
* @note Being the SPI a fast peripheral, much care must be taken to
|
||||
* not saturate the CPU bandwidth with an excessive IRQ rate. The
|
||||
* maximum transfer bit rate is likely limited by the IRQ
|
||||
* handling.
|
||||
*
|
||||
* @section lpc13xx_spi_1 Supported HW resources
|
||||
* - SSP0.
|
||||
* - SSP1 (where present).
|
||||
* .
|
||||
* @section lpc13xx_spi_2 LPC13xx SPI driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Each SSP can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Programmable interrupt priority levels for each SSP.
|
||||
* .
|
||||
* @ingroup LPC13xx
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC13xx_SERIAL LPC13xx UART Support (buffered)
|
||||
* @details The LPC13xx Serial driver uses the UART peripheral in a
|
||||
* buffered, interrupt driven, implementation. The serial driver
|
||||
* also takes advantage of the LPC13xx UARTs deep hardware buffers.
|
||||
*
|
||||
* @section lpc13xx_serial_1 Supported HW resources
|
||||
* The serial driver can support any of the following hardware resources:
|
||||
* - UART.
|
||||
* .
|
||||
* @section lpc13xx_serial_2 LPC13xx Serial driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Fully interrupt driven.
|
||||
* - Programmable priority level.
|
||||
* - Takes advantage of the input and output FIFOs.
|
||||
* .
|
||||
* @ingroup LPC13xx
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC13xx/serial_lld.c
|
||||
* @brief LPC13xx low level serial driver code.
|
||||
*
|
||||
* @addtogroup LPC13xx_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC13xx/serial_lld.h
|
||||
* @brief LPC13xx low level serial driver header.
|
||||
*
|
||||
* @addtogroup LPC13xx_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -109,7 +109,7 @@
|
|||
* @brief UART0 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(LPC13xx_UART0_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define LPC13xx_UART0_PRIORITY 3
|
||||
#define LPC13xx_UART0_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/hal_lld.c
|
||||
* @brief LPC214x HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup LPC214x_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/hal_lld.h
|
||||
* @brief LPC214x HAL subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup LPC214x_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/pal_lld.c
|
||||
* @brief LPC214x FIO low level driver code.
|
||||
*
|
||||
* @addtogroup LPC214x_PAL
|
||||
* @addtogroup PAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/pal_lld.h
|
||||
* @brief LPC214x FIO low level driver header.
|
||||
*
|
||||
* @addtogroup LPC214x_PAL
|
||||
* @addtogroup PAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -19,44 +19,44 @@
|
|||
|
||||
/**
|
||||
* @defgroup LPC214x LPC214x Drivers
|
||||
* @brief LPC214x specific support.
|
||||
* @details The LPC214x support includes:
|
||||
* - VIC support code.
|
||||
* - I/O ports driver.
|
||||
* - Buffered, interrupt driven, serial driver.
|
||||
* - SPI driver.
|
||||
* - A demo supporting the kernel test suite.
|
||||
* - A C++ demo supporting the kernel test suite.
|
||||
* - A demo integrating ChibiOS/RT with FatFS.
|
||||
* .
|
||||
* @details This section describes all the supported drivers on the LPC214x
|
||||
* platform and the implementation details of the single drivers.
|
||||
*
|
||||
* @ingroup platforms
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_VIC VIC Support
|
||||
* @brief VIC peripheral support.
|
||||
* @defgroup LPC214x_HAL LPC214x Initialization Support
|
||||
* @details The LPC214x HAL support is responsible for system initialization.
|
||||
*
|
||||
* @section lpc214x_hal_1 Supported HW resources
|
||||
* - PLL0.
|
||||
* - MAM.
|
||||
* - VPBDIV.
|
||||
* .
|
||||
* @section lpc214x_hal_2 LPC214x HAL driver implementation features
|
||||
* - Clock tree initialization.
|
||||
* - Clock source selection.
|
||||
* - MAM initialization.
|
||||
* .
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_HAL LPC214x HAL Support
|
||||
* @brief HAL support.
|
||||
* @defgroup LPC214x_PAL LPC214x FIO Support
|
||||
* @details The LPC214x PAL driver uses the FIO peripherals.
|
||||
*
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_PAL LPC214x I/O Ports Support
|
||||
* @brief I/O Ports peripherals support.
|
||||
* @details This module supports the LPC214x FIO controller. The controller
|
||||
* supports the following features (see @ref PAL):
|
||||
* @section lpc214x_pal_1 Supported HW resources
|
||||
* - FIO0.
|
||||
* - FIO1.
|
||||
* .
|
||||
* @section lpc214x_pal_2 LPC214x PAL driver implementation features
|
||||
* - 32 bits wide ports.
|
||||
* - Atomic set/reset functions.
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
* <h2>Supported Setup Modes</h2>
|
||||
* @section lpc214x_pal_3 Supported PAL setup modes
|
||||
* - @p PAL_MODE_RESET.
|
||||
* - @p PAL_MODE_UNCONNECTED.
|
||||
* - @p PAL_MODE_INPUT.
|
||||
|
|
@ -65,7 +65,8 @@
|
|||
* .
|
||||
* Any attempt to setup an invalid mode is ignored.
|
||||
*
|
||||
* <h2>Suboptimal Behavior</h2>
|
||||
* @section lpc214x_pal_4 Suboptimal behavior
|
||||
* Some FIO features are less than optimal:
|
||||
* - Pad/port toggling operations are not atomic.
|
||||
* - Pad/group mode setup is not atomic.
|
||||
* .
|
||||
|
|
@ -73,18 +74,48 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_SERIAL LPC214x UART Support
|
||||
* @brief UART peripherals support.
|
||||
* @details The serial driver supports the LPC214x UART peripherals.
|
||||
* @defgroup LPC214x_SPI LPC214x SPI Support
|
||||
* @details The SPI driver supports the LPC214x SSP peripheral in an interrupt
|
||||
* driven implementation.
|
||||
* @note Being the SPI a fast peripheral, much care must be taken to
|
||||
* not saturate the CPU bandwidth with an excessive IRQ rate. The
|
||||
* maximum transfer bit rate is likely limited by the IRQ
|
||||
* handling.
|
||||
*
|
||||
* @section lpc214x_spi_1 Supported HW resources
|
||||
* - SSP (SPI0).
|
||||
* .
|
||||
* @section lpc214x_spi_2 LPC214x SPI driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Programmable interrupt priority level.
|
||||
* .
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_SPI LPC214x SPI Support
|
||||
* @brief SSP peripheral support.
|
||||
* @details The SPI driver supports the LPC214x SSP, the driver works in
|
||||
* polling mode.
|
||||
* @defgroup LPC214x_SERIAL LPC214x UART Support (buffered)
|
||||
* @details The LPC214x Serial driver uses the UART peripherals in a
|
||||
* buffered, interrupt driven, implementation. The serial driver
|
||||
* also takes advantage of the LPC214x UARTs deep hardware buffers.
|
||||
*
|
||||
* @section lpc214x_serial_1 Supported HW resources
|
||||
* The serial driver can support any of the following hardware resources:
|
||||
* - UART0.
|
||||
* - UART1.
|
||||
* .
|
||||
* @section lpc214x_serial_2 LPC214x Serial driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Fully interrupt driven.
|
||||
* - Programmable interrupt priority levels for each UART.
|
||||
* - Takes advantage of the input and output FIFOs.
|
||||
* .
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup LPC214x_VIC LPC214x VIC Support
|
||||
* @details This VIC helper driver is used by the other drivers in order to
|
||||
* access the shared VIC resources in a consistent way.
|
||||
*
|
||||
* @ingroup LPC214x
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/serial_lld.c
|
||||
* @brief LPC214x low level serial driver code.
|
||||
*
|
||||
* @addtogroup LPC214x_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/serial_lld.h
|
||||
* @brief LPC214x low level serial driver header.
|
||||
*
|
||||
* @addtogroup LPC214x_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/spi_lld.c
|
||||
* @brief LPC214x low level SPI driver code.
|
||||
*
|
||||
* @addtogroup LPC214x_SPI
|
||||
* @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file LPC214x/spi_lld.h
|
||||
* @brief LPC214x low level SPI driver header.
|
||||
*
|
||||
* @addtogroup LPC214x_SPI
|
||||
* @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file MSP430/hal_lld.c
|
||||
* @brief MSP430 HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup MSP430_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file MSP430/hal_lld.h
|
||||
* @brief MSP430 HAL subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup MSP430_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file MSP430/pal_lld.c
|
||||
* @brief MSP430 Digital I/O low level driver code.
|
||||
*
|
||||
* @addtogroup MSP430_PAL
|
||||
* @addtogroup PAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file MSP430/pal_lld.h
|
||||
* @brief MSP430 Digital I/O low level driver header.
|
||||
*
|
||||
* @addtogroup MSP430_PAL
|
||||
* @addtogroup PAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -19,29 +19,49 @@
|
|||
|
||||
/**
|
||||
* @defgroup MSP430_DRIVERS MSP430 Drivers
|
||||
* @brief MSP430 specific support.
|
||||
* @details This section describes all the supported drivers on the MSP430
|
||||
* platform and the implementation details of the single drivers.
|
||||
*
|
||||
* @ingroup platforms
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_HAL MSP430 HAL Support
|
||||
* @brief HAL support.
|
||||
* @defgroup MSP430_HAL MSP430 Initialization Support
|
||||
* @details The MSP430 HAL support is responsible for system initialization.
|
||||
*
|
||||
* @section msp430_hal_1 Supported HW resources
|
||||
* - DCOCTL.
|
||||
* - BCSCTL1.
|
||||
* - BCSCTL2.
|
||||
* .
|
||||
* @section msp430_hal_2 MSP430 HAL driver implementation features
|
||||
* - Clock source selection.
|
||||
* .
|
||||
* @ingroup MSP430_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_PAL MSP430 I/O Ports Support
|
||||
* @brief I/O Ports peripherals support.
|
||||
* @details This module supports the MSP430 Digital I/O controller. The
|
||||
* controller supports the following features (see @ref PAL):
|
||||
* @defgroup MSP430_PAL MSP430 PORT Support
|
||||
* @details The MSP430 PAL driver uses the PORT peripherals.
|
||||
*
|
||||
* @section msp430_pal_1 Supported HW resources
|
||||
* - PORT1 (where present).
|
||||
* - PORT2 (where present).
|
||||
* - PORT3 (where present).
|
||||
* - PORT4 (where present).
|
||||
* - PORT5 (where present).
|
||||
* - PORT6 (where present).
|
||||
* .
|
||||
* @section msp430_pal_2 MSP430 PAL driver implementation features
|
||||
* The PAL driver implementation fully supports the following hardware
|
||||
* capabilities:
|
||||
* - 8 bits wide ports.
|
||||
* - Atomic set/reset/toggle functions because special MSP430 instruction set.
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
* <h2>Supported Setup Modes</h2>
|
||||
* @section msp430_pal_3 Supported PAL setup modes
|
||||
* The MSP430 PAL driver supports the following I/O modes:
|
||||
* - @p PAL_MODE_RESET.
|
||||
* - @p PAL_MODE_UNCONNECTED.
|
||||
* - @p PAL_MODE_INPUT.
|
||||
|
|
@ -49,19 +69,28 @@
|
|||
* .
|
||||
* Any attempt to setup an invalid mode is ignored.
|
||||
*
|
||||
* <h2>Suboptimal Behavior</h2>
|
||||
* Some MSP430 I/O ports features are less than optimal:
|
||||
* - Bus/group writing is not atomic.
|
||||
* @section msp430_pal_4 Suboptimal behavior
|
||||
* The MSP430 PORT is less than optimal in several areas, the limitations
|
||||
* should be taken in account while using the PAL driver:
|
||||
* - Bus/group writes is not atomic.
|
||||
* - Pad/group mode setup is not atomic.
|
||||
* .
|
||||
* @ingroup MSP430_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MSP430_SERIAL MSP430 USART Support
|
||||
* @brief USART support.
|
||||
* @details The serial driver supports both the MSP430 USARTs in asynchronous
|
||||
* mode.
|
||||
* @defgroup MSP430_SERIAL MSP430 USART Support (buffered)
|
||||
* @details The MSP430 Serial driver uses the USART peripherals in a
|
||||
* buffered, interrupt driven, implementation.
|
||||
*
|
||||
* @section msp430_serial_1 Supported HW resources
|
||||
* The serial driver can support any of the following hardware resources:
|
||||
* - USART0.
|
||||
* - USART1.
|
||||
* .
|
||||
* @section msp430_serial_2 MSP430 Serial driver implementation features
|
||||
* - Each USART can be independently enabled and programmed.
|
||||
* - Fully interrupt driven.
|
||||
* .
|
||||
* @ingroup MSP430_DRIVERS
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file MSP430/serial_lld.c
|
||||
* @brief MSP430 low level serial driver code.
|
||||
*
|
||||
* @addtogroup MSP430_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file MSP430/serial_lld.h
|
||||
* @brief MSP430 low level serial driver header.
|
||||
*
|
||||
* @addtogroup MSP430_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file SPC56x/hal_lld.c
|
||||
* @brief SPC563 HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup SPC563_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file SPC56x/hal_lld.h
|
||||
* @brief SPC563 HAL subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup SPC563_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -18,24 +18,52 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPC563_DRIVERS SPC563 Drivers
|
||||
* @brief SPC563 specific support.
|
||||
* @defgroup SPC563 SPC563Mx Drivers
|
||||
* @details This section describes all the supported drivers on the
|
||||
* SPC563Mx/MPC563xM platform and the implementation details
|
||||
* of the single drivers.
|
||||
*
|
||||
* @ingroup platforms
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPC563_HAL SPC563 HAL Support
|
||||
* @brief HAL support.
|
||||
* @defgroup SPC563_HAL SPC563Mx Initialization Support
|
||||
* @details The SPC563Mx/MPC563xM HAL support is responsible for system
|
||||
* initialization.
|
||||
*
|
||||
* @ingroup SPC563_DRIVERS
|
||||
* @section spc563_hal_1 Supported HW resources
|
||||
* - FMPLL.
|
||||
* - INTC.
|
||||
* - XBAR.
|
||||
* - CFLASH0.
|
||||
* .
|
||||
* @section spc563_hal_2 SPC563Mx HAL driver implementation features
|
||||
* - FMPLL startup and stabilization.
|
||||
* - Clock tree initialization.
|
||||
* - Clock source selection.
|
||||
* - Flash wait states initialization based on the selected clock options.
|
||||
* - SYSTICK initialization based on current clock and kernel required rate.
|
||||
* - DMA support initialization.
|
||||
* .
|
||||
* @ingroup SPC563
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPC563_SERIAL SPC563 ESCI Support
|
||||
* @brief ESCI support.
|
||||
* @details The serial driver supports both the SPC563 ESCIs in asynchronous
|
||||
* mode.
|
||||
* @defgroup SPC563_SERIAL SPC563Mx ESCI Support (buffered)
|
||||
* @details The SPC563Mx/MPC563xM Serial driver uses the ESCI peripherals
|
||||
* in a buffered, interrupt driven, implementation.
|
||||
*
|
||||
* @ingroup SPC563_DRIVERS
|
||||
* @section spc563_serial_1 Supported HW resources
|
||||
* The serial driver can support any of the following hardware resources:
|
||||
* - ESCIA.
|
||||
* - ESCIB.
|
||||
* .
|
||||
* @section spc563_serial_2 SPC563Mx Serial driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Each ESCI can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Fully interrupt driven.
|
||||
* - Programmable priority levels for each ESCI.
|
||||
* .
|
||||
* @ingroup SPC563
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file SPC56x/serial_lld.c
|
||||
* @brief SPC563 low level serial driver code.
|
||||
*
|
||||
* @addtogroup SPC563_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file SPC56x/serial_lld.h
|
||||
* @brief SPC563 low level serial driver header.
|
||||
*
|
||||
* @addtogroup SPC563_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -18,15 +18,15 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32 STM32 Drivers
|
||||
* @brief STM32 specific support.
|
||||
* @defgroup STM32_DRIVERS STM32 Drivers
|
||||
* @details This section describes all the supported drivers on the STM32
|
||||
* platform and the implementation details of the single drivers.
|
||||
*
|
||||
* @ingroup platforms
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_HAL STM32 HAL Support
|
||||
* @brief HAL support.
|
||||
* @defgroup STM32_HAL STM32 Initialization Support
|
||||
* @details The STM32 HAL support is responsible for system initialization.
|
||||
*
|
||||
* @section stm32_hal_1 Supported HW resources
|
||||
|
|
@ -34,8 +34,6 @@
|
|||
* - PLL2 (where present).
|
||||
* - RCC.
|
||||
* - Flash.
|
||||
* - DMA1.
|
||||
* - DMA2 (where present).
|
||||
* .
|
||||
* @section stm32_hal_2 STM32 HAL driver implementation features
|
||||
* - PLLs startup and stabilization.
|
||||
|
|
@ -45,17 +43,17 @@
|
|||
* - SYSTICK initialization based on current clock and kernel required rate.
|
||||
* - DMA support initialization.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_ADC STM32 ADC Support
|
||||
* @brief ADC peripheral support.
|
||||
* @details The ADC driver supports the STM32 ADCs using DMA channels for
|
||||
* improved performance.
|
||||
* @details The STM32 ADC driver supports the ADC peripherals using DMA
|
||||
* channels for maximum performance.
|
||||
*
|
||||
* @section stm32_adc_1 Supported HW resources
|
||||
* - ADC1.
|
||||
* - DMA1.
|
||||
* .
|
||||
* @section stm32_adc_2 STM32 ADC driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
|
|
@ -65,12 +63,12 @@
|
|||
* - Programmable DMA interrupt priority for each DMA channel.
|
||||
* - Programmable DMA error hook for each DMA channel.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_CAN STM32 CAN Support
|
||||
* @brief CAN peripheral support.
|
||||
* @details The STM32 CAN driver uses the CAN peripherals.
|
||||
*
|
||||
* @section stm32_can_1 Supported HW resources
|
||||
* - bxCAN1.
|
||||
|
|
@ -80,29 +78,30 @@
|
|||
* - Support for bxCAN sleep mode.
|
||||
* - Programmable bxCAN interrupts priority level.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_DMA STM32 DMA Support
|
||||
* @brief DMA helper driver.
|
||||
* @details This DMA helper driver is used by the other drivers in order to
|
||||
* access the shared DMA resources in a consistent way.
|
||||
*
|
||||
* @section stm32_dma_1 Supported HW resources
|
||||
* The DMA driver can support any of the following hardware resources:
|
||||
* - DMA1.
|
||||
* - DMA2.
|
||||
* - DMA2 (where present).
|
||||
* .
|
||||
* @section stm32_dma_2 STM32 DMA driver implementation features
|
||||
* - Automatic DMA clock stop when not in use by other drivers.
|
||||
* - Exports helper functions/macros to the other drivers that share the
|
||||
* DMA resource.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_PAL STM32 GPIO Support
|
||||
* @brief GPIO peripherals support.
|
||||
* @details The STM32 PAL driver uses the GPIO peripherals.
|
||||
*
|
||||
* @section stm32_pal_1 Supported HW resources
|
||||
* - AFIO.
|
||||
|
|
@ -110,9 +109,9 @@
|
|||
* - GPIOB.
|
||||
* - GPIOC.
|
||||
* - GPIOD.
|
||||
* - GPIOE.
|
||||
* - GPIOF.
|
||||
* - GPIOG.
|
||||
* - GPIOE (where present).
|
||||
* - GPIOF (where present).
|
||||
* - GPIOG (where present).
|
||||
* .
|
||||
* @section stm32_pal_2 STM32 PAL driver implementation features
|
||||
* The PAL driver implementation fully supports the following hardware
|
||||
|
|
@ -139,20 +138,20 @@
|
|||
* Any attempt to setup an invalid mode is ignored.
|
||||
*
|
||||
* @section stm32_pal_4 Suboptimal behavior
|
||||
* The STM32 GPIO is less than optimal in several areas, the limitations should
|
||||
* be taken in account while using the PAL driver:
|
||||
* The STM32 GPIO is less than optimal in several areas, the limitations
|
||||
* should be taken in account while using the PAL driver:
|
||||
* - Pad/port toggling operations are not atomic.
|
||||
* - Pad/group mode setup is not atomic.
|
||||
* - Writing on pads/groups/ports programmed as input with pull-up/down
|
||||
* resistor can change the resistor setting because the output latch is
|
||||
* used for resistor selection.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_PWM STM32 PWM Support
|
||||
* @brief TIMx peripherals as PWM generators support.
|
||||
* @details The STM32 PWM driver uses the TIMx peripherals.
|
||||
*
|
||||
* @section stm32_pwm_1 Supported HW resources
|
||||
* - TIM1.
|
||||
|
|
@ -166,19 +165,20 @@
|
|||
* - Four independent PWM channels per timer.
|
||||
* - Programmable TIMx interrupts priority level.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_SPI STM32 SPI Support
|
||||
* @brief SPI peripherals support.
|
||||
* @details The SPI driver supports the STM32 SPIs using DMA channels for
|
||||
* improved performance.
|
||||
* @details The SPI driver supports the STM32 SPI peripherals using DMA
|
||||
* channels for maximum performance.
|
||||
*
|
||||
* @section stm32_spi_1 Supported HW resources
|
||||
* - SPI1.
|
||||
* - SPI2.
|
||||
* - SPI3.
|
||||
* - SPI3 (where present).
|
||||
* - DMA1.
|
||||
* - DMA2 (where present).
|
||||
* .
|
||||
* @section stm32_spi_2 STM32 SPI driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
|
|
@ -190,20 +190,21 @@
|
|||
* - Programmable DMA interrupt priority for each DMA channel.
|
||||
* - Programmable DMA error hook for each DMA channel.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_SERIAL STM32 USART Support (buffered)
|
||||
* @brief UART/USART peripherals support.
|
||||
* @details The STM32 Serial driver uses the USART/UART peripherals in a
|
||||
* buffered, interrupt driven, implementation.
|
||||
*
|
||||
* @section stm32_serial_1 Supported HW resources
|
||||
* The serial driver can support any of the following hardware resources:
|
||||
* - USART1.
|
||||
* - USART2.
|
||||
* - USART3.
|
||||
* - UART4.
|
||||
* - UART5.
|
||||
* - USART3 (where present).
|
||||
* - UART4 (where present).
|
||||
* - UART5 (where present).
|
||||
* .
|
||||
* @section stm32_serial_2 STM32 Serial driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
|
|
@ -212,18 +213,21 @@
|
|||
* - Fully interrupt driven.
|
||||
* - Programmable priority levels for each UART/USART.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32_UART STM32 USART Support (unbuffered)
|
||||
* @brief UART/USART peripherals support.
|
||||
* @details The UART driver supports the STM32 USART peripherals using DMA
|
||||
* channels for maximum performance.
|
||||
*
|
||||
* @section stm32_uart_1 Supported HW resources
|
||||
* The UART driver can support any of the following hardware resources:
|
||||
* - USART1.
|
||||
* - USART2.
|
||||
* - USART3.
|
||||
* - USART3 (where present).
|
||||
* - DMA1.
|
||||
* - DMA2 (where present).
|
||||
* .
|
||||
* @section stm32_uart_2 STM32 UART driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
|
|
@ -235,5 +239,5 @@
|
|||
* - Programmable DMA interrupt priority for each DMA channel.
|
||||
* - Programmable DMA error hook for each DMA channel.
|
||||
* .
|
||||
* @ingroup STM32
|
||||
* @ingroup STM32_DRIVERS
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file STM8/hal_lld.c
|
||||
* @brief STM8 HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup STM8_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file STM8/hal_lld.h
|
||||
* @brief STM8 HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup STM8_HAL
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file STM8/pal_lld.c
|
||||
* @brief STM8 GPIO low level driver code.
|
||||
*
|
||||
* @addtogroup STM8_PAL
|
||||
* @addtogroup PAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file STM8/pal_lld.h
|
||||
* @brief STM8 GPIO low level driver header.
|
||||
*
|
||||
* @addtogroup STM8_PAL
|
||||
* @addtogroup PAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -18,30 +18,54 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM8_DRIVERS STM8 Drivers
|
||||
* @brief STM8 specific support.
|
||||
* @defgroup STM8_DRIVERS STM8x Drivers
|
||||
* @details This section describes all the supported drivers on the STM8S and
|
||||
* STM8A platforms and the implementation details of the single
|
||||
* drivers.
|
||||
*
|
||||
* @ingroup platforms
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM8_HAL STM8 HAL Support
|
||||
* @brief HAL support.
|
||||
* @defgroup STM8_HAL STM8 Initialization Support
|
||||
* @details The STM8 HAL support is responsible for system initialization.
|
||||
*
|
||||
* @section stm8_hal_1 Supported HW resources
|
||||
* - CLK.
|
||||
* .
|
||||
* @section stm8_hal_2 STM8 HAL driver implementation features
|
||||
* - Clock tree initialization.
|
||||
* - Clock source selection.
|
||||
* .
|
||||
* @ingroup STM8_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM8_PAL STM8 I/O Ports Support
|
||||
* @brief I/O Ports peripherals support.
|
||||
* @details This module supports the STM8 GPIO controller. The controller
|
||||
* supports the following features (see @ref PAL):
|
||||
* @defgroup STM8_PAL STM8 GPIO Support
|
||||
* @details The STM8 PAL driver uses the GPIO peripherals.
|
||||
*
|
||||
* @section stm8_pal_1 Supported HW resources
|
||||
* - AFIO.
|
||||
* - GPIOA.
|
||||
* - GPIOB.
|
||||
* - GPIOC.
|
||||
* - GPIOD.
|
||||
* - GPIOE.
|
||||
* - GPIOF.
|
||||
* - GPIOG (where present).
|
||||
* - GPIOH (where present).
|
||||
* - GPIOI (where present).
|
||||
* .
|
||||
* @section stm8_pal_2 STM8 PAL driver implementation features
|
||||
* The PAL driver implementation fully supports the following hardware
|
||||
* capabilities:
|
||||
* - 8 bits wide ports.
|
||||
* - Atomic set/reset/toggle functions because special STM8 instruction set.
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
* <h2>Supported Setup Modes</h2>
|
||||
* @section stm8_pal_3 Supported PAL setup modes
|
||||
* The STM8 PAL driver supports the following I/O modes:
|
||||
* - @p PAL_MODE_RESET.
|
||||
* - @p PAL_MODE_UNCONNECTED.
|
||||
* - @p PAL_MODE_INPUT.
|
||||
|
|
@ -51,8 +75,9 @@
|
|||
* .
|
||||
* Any attempt to setup an invalid mode is ignored.
|
||||
*
|
||||
* <h2>Suboptimal Behavior</h2>
|
||||
* Some STM8 I/O ports features are less than optimal:
|
||||
* @section stm8_pal_4 Suboptimal behavior
|
||||
* The STM8 GPIO is less than optimal in several areas, the limitations
|
||||
* should be taken in account while using the PAL driver:
|
||||
* - Bus/group writing is not atomic.
|
||||
* - Pad/group mode setup is not atomic.
|
||||
* .
|
||||
|
|
@ -60,9 +85,21 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM8_SERIAL STM8 UART Support
|
||||
* @brief USART support.
|
||||
* @details The serial driver supports the STM8 USARTs in asynchronous mode.
|
||||
* @defgroup STM8_SERIAL STM8 UART Support (buffered)
|
||||
* @details The STM8 Serial driver uses the UART peripherals in a
|
||||
* buffered, interrupt driven, implementation.
|
||||
*
|
||||
* @section stm8_serial_1 Supported HW resources
|
||||
* The serial driver can support any of the following hardware resources:
|
||||
* - UART1.
|
||||
* - UART2 (where present).
|
||||
* - UART3 (where present).
|
||||
* .
|
||||
* @section stm8_serial_2 STM8 Serial driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Each UART can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Fully interrupt driven.
|
||||
* .
|
||||
* @ingroup STM8_DRIVERS
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file STM8/serial_lld.c
|
||||
* @brief STM8 low level serial driver code.
|
||||
*
|
||||
* @addtogroup STM8_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @file STM8/serial_lld.h
|
||||
* @brief STM8 low level serial driver header.
|
||||
*
|
||||
* @addtogroup STM8_SERIAL
|
||||
* @addtogroup SERIAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
19
todo.txt
19
todo.txt
|
|
@ -3,6 +3,7 @@ Status:
|
|||
X = In progress, some work done.
|
||||
* = Done.
|
||||
? = Not sure if worth the effort or useful at all.
|
||||
N = Decided against.
|
||||
|
||||
Within 2.1.x
|
||||
* Binary Semaphores on top of Counting Semaphores.
|
||||
|
|
@ -27,18 +28,24 @@ Within 2.1.x
|
|||
* Verify the FatFs demo on both the AT91SAM7X and AT91SAM7S.
|
||||
* Update the LPC214x SPI driver (ISR).
|
||||
* Verify the LPC214x FatFs demo.
|
||||
- Write a new SPI driver for LPC1xxx (ISR)(it should be very close to the
|
||||
X Write a new SPI driver for LPC1xxx (ISR)(it should be very close to the
|
||||
LPC214x one).
|
||||
- Evaluate if to add a synchronous API to the UART driver, eventually do so.
|
||||
- Serial over UART complex driver driver, evaluate from the performance
|
||||
results if to make obsolete the current dedicated Serial driver.
|
||||
N Evaluate if to add a synchronous API to the UART driver, eventually do so.
|
||||
X Global documentation reorganization in order to allow both separate documents
|
||||
and the usual blob document.
|
||||
X PDF generation from the documentation system (only separate documents, not
|
||||
the blob).
|
||||
- Automatic compilation and upload of the various documents on the web site
|
||||
(doxygen + rsync).
|
||||
- STM8L official HAL support, it will have to be separated from the STM8S/STM8A
|
||||
HAL because it is very different, actually it looks much more like a
|
||||
mini STM32, most STM32 drivers will only require few changes it also has
|
||||
a very similar DMA (waiting for the new STM8L-Discovery kit).
|
||||
- Add the STM32VL to the official STM32 HAL support (waiting for the new
|
||||
STM32-Discovery kit).
|
||||
- Evaluate a new API for the SPI driver for quick transfers of few bytes.
|
||||
- New STM8S/A SPI driver.
|
||||
X Evaluate a new API for the SPI driver enabling quick transfers of few bytes
|
||||
in polled mode.
|
||||
X Except for the above, bug fixing only until the 2.2.0 release.
|
||||
|
||||
Within 2.3.x (hopefully)
|
||||
|
|
@ -47,6 +54,8 @@ X File System infrastructure.
|
|||
- Official FatFs wrapper using the new infrastructure, dedicated test suite.
|
||||
X I2C device driver class support and at least one implementation (test
|
||||
hardware missing).
|
||||
- Serial over UART complex driver driver, evaluate from the performance
|
||||
results if to make obsolete the current dedicated Serial driver.
|
||||
- Shared DMA channels support in the STM32/STM8L HALs.
|
||||
- New device driver models: RTC, WDG, DAC, USB, Systick, Battery Monitor.
|
||||
- MAC driver for STM32F107 (hardware missing).
|
||||
|
|
|
|||
Loading…
Reference in New Issue