mirror of https://github.com/rusefi/ChibiOS.git
Created ADUCM UARTv1 unifier header
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13495 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Rocco Marco Guglielmi
parent
f18973f964
commit
5395751f6c
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@ -0,0 +1,210 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file UARTv1/aducm_uart.h
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* @brief ADUCM UART units common header.
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* @note This file requires definitions from the ADI ADUCM header file.
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*
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* @{
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*/
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#ifndef ADUCM_UART_H
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#define ADUCM_UART_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/* Discarded definitions from the ADI headers, the Serial/UART drivers use its
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own definitions in order to have an unified handling for all devices.
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Unfortunately the ADI headers have no uniform definitions for the same
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objects across the various sub-families.*/
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#if !defined(pADI_UART0)
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#define pADI_UART0 pADI_UART
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#endif
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/**
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* @name UART ports definitions
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* @{
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*/
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#define UART0 ((aducm_uart_t *)pADI_UART0)
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#define UART1 ((aducm_uart_t *)pADI_UART1)
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/** @} */
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/**
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* @name UART Data register bits definitions
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* @{
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*/
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#define ADUCM_UART_DATA_MASK 0x00FFU
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/** @} */
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/**
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* @name UART Interrupt Enable register bits definitions
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* @{
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*/
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#define ADUCM_UART_IEN_MASK 0x003FU
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#define ADUCM_UART_IEN_ERBFI (1U << 0)
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#define ADUCM_UART_IEN_ETBEI (1U << 1)
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#define ADUCM_UART_IEN_ELSI (1U << 2)
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#define ADUCM_UART_IEN_EDSSI (1U << 3)
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#define ADUCM_UART_IEN_EDMAT (1U << 4)
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#define ADUCM_UART_IEN_EDMAR (1U << 5)
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/** @} */
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/**
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* @name UART Interrupt Identification register bits definitions
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* @{
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*/
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#define ADUCM_UART_IIR_MASK 0x0007U
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#define ADUCM_UART_IIR_NINT (1U << 0)
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#define ADUCM_UART_IIR_STA_MODEM (0U << 1)
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#define ADUCM_UART_IIR_STA_TX_EMPTY (1U << 1)
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#define ADUCM_UART_IIR_STA_RX_FULL (2U << 1)
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#define ADUCM_UART_IIR_STA_LINE (3U << 1)
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/** @} */
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/**
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* @name UART Line Control register bits definitions
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* @{
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*/
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#define ADUCM_UART_LCR_MASK 0x007FU
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#define ADUCM_UART_LCR_WLS_5_BITS (0U << 0)
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#define ADUCM_UART_LCR_WLS_6_BITS (1U << 0)
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#define ADUCM_UART_LCR_WLS_7_BITS (2U << 0)
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#define ADUCM_UART_LCR_WLS_8_BITS (3U << 0)
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#define ADUCM_UART_LCR_STOP (1U << 2)
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#define ADUCM_UART_LCR_PEN (1U << 3)
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#define ADUCM_UART_LCR_EPS (1U << 4)
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#define ADUCM_UART_LCR_SP (1U << 5)
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#define ADUCM_UART_LCR_BRK (1U << 6)
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/** @} */
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/**
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* @name UART Modem Control register bits definitions
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* @{
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*/
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#define ADUCM_UART_MCR_MASK 0x0013U
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#define ADUCM_UART_MCR_DTR (1U << 0)
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#define ADUCM_UART_MCR_RTS (1U << 1)
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#define ADUCM_UART_MCR_LOOPBACK (1U << 4)
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/** @} */
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/**
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* @name UART Line Status register bits definitions
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* @{
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*/
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#define ADUCM_UART_LSR_MASK 0x007FU
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#define ADUCM_UART_LSR_DR (1U << 0)
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#define ADUCM_UART_LSR_OE (1U << 1)
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#define ADUCM_UART_LSR_PE (1U << 2)
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#define ADUCM_UART_LSR_FE (1U << 3)
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#define ADUCM_UART_LSR_BI (1U << 4)
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#define ADUCM_UART_LSR_THRE (1U << 5)
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#define ADUCM_UART_LSR_TEMT (1U << 6)
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/** @} */
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/**
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* @name UART Modem Status register bits definitions
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* @{
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*/
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#define ADUCM_UART_MSR_MASK 0x00FFU
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#define ADUCM_UART_MSR_DCTS (1U << 0)
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#define ADUCM_UART_MSR_DDSR (1U << 1)
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#define ADUCM_UART_MSR_TERI (1U << 2)
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#define ADUCM_UART_MSR_DDCD (1U << 3)
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#define ADUCM_UART_MSR_CTS (1U << 4)
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#define ADUCM_UART_MSR_DSR (1U << 5)
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#define ADUCM_UART_MSR_RI (1U << 6)
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#define ADUCM_UART_MSR_DCD (1U << 7)
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/** @} */
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/**
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* @name UART Fractional Baud Rate Divider register bits definitions
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* @{
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*/
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#define ADUCM_UART_FBR_MASK 0x9FFFU
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#define ADUCM_UART_FBR_DIVN_MASK 0x07FFU
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#define ADUCM_UART_FBR_DIVN(n) ((n) << 0)
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#define ADUCM_UART_FBR_DIVM_MASK 0x1800U
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#define ADUCM_UART_FBR_DIVM(m) ((m) << 11)
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#define ADUCM_UART_FBR_ENABLE (1U << 15)
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/** @} */
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/**
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* @name UART Divider register bits definitions
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* @{
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*/
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#define ADUCM_UART_DIV_MASK 0xFFFFU
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/** @} */
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/**
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* @name UART Control register bits definitions
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* @{
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*/
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#define ADUCM_UART_CTL_MASK 0x0001U
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#define ADUCM_UART_CTL_DISABLE (1U << 0)
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#define ADUCM_UART_CTL_ENABLE (0U << 0)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ADUCM UARTv1 registers block.
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*/
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typedef struct {
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volatile uint32_t DATA;
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volatile uint32_t IEN;
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volatile uint32_t IIR;
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volatile uint32_t LCR;
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volatile uint32_t MCR;
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volatile uint32_t LSR;
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volatile uint32_t MSR;
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volatile uint32_t SCR;
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volatile uint32_t FCR;
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volatile uint32_t FBR;
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volatile uint32_t DIV;
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volatile uint32_t LCR2;
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volatile uint32_t CTL;
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volatile uint32_t RFC;
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volatile uint32_t TFC;
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volatile uint32_t RSC;
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volatile uint32_t ACR;
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volatile uint32_t ASRL;
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volatile uint32_t ASRH;
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} aducm_uart_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#endif /* ADUCM_UART_H */
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/** @} */
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@ -30,23 +30,20 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @name ADUCM UART Fractional BR Divider register's bitfields.
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* @{
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*/
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#define ADUCM_COMFBR_ENABLE COMFBR_ENABLE_EN
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#define ADUCM_COMFBR_DIVM(m) ((m) << 11U)
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#define ADUCM_COMFBR_DIVN(n) ((n) << 0U)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief USART1 serial driver identifier.*/
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#if (ADUCM_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
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/** @brief UART0 serial driver identifier.*/
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#if ADUCM_SERIAL_USE_UART0 || defined(__DOXYGEN__)
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SerialDriver SD0;
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#endif
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/** @brief UART0 serial driver identifier.*/
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#if ADUCM_SERIAL_USE_UART1 || defined(__DOXYGEN__)
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SerialDriver SD1;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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@ -56,7 +53,7 @@ SerialDriver SD0;
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*/
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static const SerialConfig default_config = {
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SERIAL_DEFAULT_BITRATE,
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COMLCR_WLS_8BITS
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ADUCM_UART_LCR_WLS_8_BITS
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};
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#if ADUCM_SERIAL_USE_UART0 || defined(__DOXYGEN__)
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@ -67,6 +64,14 @@ static uint8_t sd_in_buf0[ADUCM_SERIAL_UART0_IN_BUF_SIZE];
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static uint8_t sd_out_buf0[ADUCM_SERIAL_UART0_OUT_BUF_SIZE];
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#endif
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#if ADUCM_SERIAL_USE_UART1 || defined(__DOXYGEN__)
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/** @brief Input buffer for SD1.*/
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static uint8_t sd_in_buf1[ADUCM_SERIAL_UART1_IN_BUF_SIZE];
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/** @brief Output buffer for SD1.*/
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static uint8_t sd_out_buf1[ADUCM_SERIAL_UART1_OUT_BUF_SIZE];
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#endif
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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@ -83,7 +88,7 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
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uint32_t comdiv, divn, divm;
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/* Resetting the UART state machine. */
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sdp->uart->COMCON = COMCON_DISABLE_EN;
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sdp->uart->CTL = ADUCM_UART_CTL_DISABLE;
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/* Baud rate setting.*/
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osalDbgAssert(((sdp->clock / 32U) > config->speed),
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@ -120,17 +125,17 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
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osalDbgAssert((divn <= 2047), "invalid divn value");
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sdp->uart->COMFBR = ADUCM_COMFBR_ENABLE | ADUCM_COMFBR_DIVM(divm) |
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ADUCM_COMFBR_DIVN(divn);
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sdp->uart->FBR = ADUCM_UART_FBR_ENABLE | ADUCM_UART_FBR_DIVM(divm) |
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ADUCM_UART_FBR_DIVN(divn);
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sdp->uart->COMDIV = comdiv;
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sdp->uart->DIV = comdiv;
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/* Line and modem configurations*/
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sdp->uart->COMLCR = config->lcr;
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sdp->uart->LCR = config->lcr;
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sdp->uart->COMIEN = COMIEN_EDMAR_DIS | COMIEN_EDMAT_DIS | COMIEN_EDSSI_EN |
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COMIEN_ELSI_EN | COMIEN_ETBEI_EN | COMIEN_ERBFI_EN;
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sdp->uart->COMCON = COMCON_DISABLE_DIS;
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sdp->uart->IEN = ADUCM_UART_IEN_EDSSI | ADUCM_UART_IEN_ELSI |
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ADUCM_UART_IEN_ETBEI | ADUCM_UART_IEN_ERBFI;
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sdp->uart->CTL = ADUCM_UART_CTL_ENABLE;
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}
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/**
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@ -141,8 +146,8 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
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*/
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static void uart_deinit(SerialDriver *sdp) {
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sdp->uart->COMIEN = 0;
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sdp->uart->COMCON = COMCON_DISABLE_EN;
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sdp->uart->IEN = 0;
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sdp->uart->CTL = ADUCM_UART_CTL_DISABLE;
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}
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/**
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@ -154,11 +159,11 @@ static void uart_deinit(SerialDriver *sdp) {
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static void set_error(SerialDriver *sdp, uint32_t lsr) {
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eventflags_t sts = 0;
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if (lsr & COMLSR_OE)
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if (lsr & ADUCM_UART_LSR_OE)
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sts |= SD_OVERRUN_ERROR;
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if (lsr & COMLSR_PE)
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if (lsr & ADUCM_UART_LSR_PE)
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sts |= SD_PARITY_ERROR;
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if (lsr & COMLSR_FE)
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if (lsr & ADUCM_UART_LSR_FE)
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sts |= SD_FRAMING_ERROR;
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osalSysLockFromISR();
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chnAddFlagsI(sdp, sts);
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@ -169,7 +174,15 @@ static void set_error(SerialDriver *sdp, uint32_t lsr) {
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static void notify0(io_queue_t *qp) {
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(void)qp;
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pADI_UART->COMIEN |= COMIEN_ETBEI_EN;
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UART0->IEN |= ADUCM_UART_IEN_ETBEI;
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}
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#endif
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#if ADUCM_SERIAL_USE_UART1 || defined(__DOXYGEN__)
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static void notify1(io_queue_t *qp) {
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(void)qp;
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UART1->IEN |= ADUCM_UART_IEN_ETBEI;
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}
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#endif
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@ -196,6 +209,24 @@ OSAL_IRQ_HANDLER(ADUCM_UART0_HANDLER) {
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}
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#endif
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#if ADUCM_SERIAL_USE_UART1 || defined(__DOXYGEN__)
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#if !defined(ADUCM_UART1_HANDLER)
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#error "ADUCM_UART1_HANDLER not defined"
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#endif
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/**
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* @brief UART1 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(ADUCM_UART1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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sd_lld_serve_interrupt(&SD1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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@ -207,15 +238,27 @@ OSAL_IRQ_HANDLER(ADUCM_UART0_HANDLER) {
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*/
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void sd_lld_init(void) {
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#if ADUCM_SERIAL_USE_UART0 == TRUE
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#if ADUCM_SERIAL_USE_UART0
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sdObjectInit(&SD0);
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iqObjectInit(&SD0.iqueue, sd_in_buf0, sizeof sd_in_buf0, NULL, &SD0);
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oqObjectInit(&SD0.oqueue, sd_out_buf0, sizeof sd_out_buf0, notify0, &SD0);
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SD0.uart = pADI_UART;
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SD0.clock = ADUCM_UARTCLK;
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SD0.uart = UART0;
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SD0.clock = ADUCM_UART0CLK;
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#if defined(ADUCM_SERIAL_UART0_PRIORITY)
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nvicEnableVector(ADUCM_UART0_NUMBER, ADUCM_SERIAL_UART0_PRIORITY);
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#endif
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#endif
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#if ADUCM_SERIAL_USE_UART1
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sdObjectInit(&SD1);
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iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1);
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oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1);
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SD1.uart = UART1;
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SD1.clock = ADUCM_UART1CLK;
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#if defined(ADUCM_SERIAL_UART1_PRIORITY)
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nvicEnableVector(ADUCM_UART1_NUMBER, ADUCM_SERIAL_UART1_PRIORITY);
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#endif
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#endif
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}
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/**
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@ -235,11 +278,17 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
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}
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if (sdp->state == SD_STOP) {
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#if ADUCM_SERIAL_USE_UART0 == TRUE
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#if ADUCM_SERIAL_USE_UART0 && !ADUCM_HAS_CLK_AUTOGATE
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if (&SD0 == sdp) {
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ccEnableUART0();
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}
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#endif
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#if ADUCM_SERIAL_USE_UART1 && !ADUCM_HAS_CLK_AUTOGATE
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if (&SD1 == sdp) {
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ccEnableUART1();
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}
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#endif
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}
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uart_init(sdp, config);
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}
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@ -259,12 +308,19 @@ void sd_lld_stop(SerialDriver *sdp) {
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/* UART is de-initialized then clocks are disabled.*/
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uart_deinit(sdp);
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#if ADUCM_SERIAL_USE_UART0 == TRUE
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#if ADUCM_SERIAL_USE_UART0 && !ADUCM_HAS_CLK_AUTOGATE
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if (&SD0 == sdp) {
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ccDisableUART0();
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return;
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}
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#endif
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#if ADUCM_SERIAL_USE_UART1 && !ADUCM_HAS_CLK_AUTOGATE
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if (&SD1 == sdp) {
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ccDisableUART1();
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return;
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}
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#endif
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}
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}
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||||
|
||||
|
|
@ -274,15 +330,15 @@ void sd_lld_stop(SerialDriver *sdp) {
|
|||
* @param[in] sdp communication channel associated to the USART
|
||||
*/
|
||||
void sd_lld_serve_interrupt(SerialDriver *sdp) {
|
||||
uint32_t irr = sdp->uart->COMIIR;
|
||||
uint32_t ien = sdp->uart->COMIEN;
|
||||
uint32_t irr = sdp->uart->IIR;
|
||||
uint32_t ien = sdp->uart->IEN;
|
||||
|
||||
if(!(irr & COMIIR_NINT_MSK)) {
|
||||
if(irr == COMIIR_STA_MODEMSTATUS) {
|
||||
if(!(irr & ADUCM_UART_IIR_NINT)) {
|
||||
if(irr == ADUCM_UART_IIR_STA_MODEM) {
|
||||
volatile uint32_t msr;
|
||||
|
||||
/* Clearing the interrupt. */
|
||||
msr = sdp->uart->COMMSR;
|
||||
msr = sdp->uart->MSR;
|
||||
|
||||
(void) msr;
|
||||
}
|
||||
|
|
@ -292,12 +348,12 @@ void sd_lld_serve_interrupt(SerialDriver *sdp) {
|
|||
an extra interrupt to serve.
|
||||
2) FIFO mode is enabled on devices that support it, we need to empty
|
||||
the FIFO.*/
|
||||
while (irr & COMIIR_STA_RXBUFFULL) {
|
||||
while (irr & ADUCM_UART_IIR_STA_RX_FULL) {
|
||||
osalSysLockFromISR();
|
||||
sdIncomingDataI(sdp, (uint8_t)sdp->uart->COMRX);
|
||||
sdIncomingDataI(sdp, (uint8_t)sdp->uart->DATA);
|
||||
osalSysUnlockFromISR();
|
||||
|
||||
irr = sdp->uart->COMIIR;
|
||||
irr = sdp->uart->IIR;
|
||||
}
|
||||
|
||||
/* Transmission buffer empty, note it is a while in order to handle two
|
||||
|
|
@ -306,43 +362,38 @@ void sd_lld_serve_interrupt(SerialDriver *sdp) {
|
|||
would cause an extra interrupt to serve.
|
||||
2) FIFO mode is enabled on devices that support it, we need to fill
|
||||
the FIFO.*/
|
||||
if (ien & COMIEN_ETBEI) {
|
||||
while (irr & COMIIR_STA_TXBUFEMPTY) {
|
||||
if (ien & ADUCM_UART_IEN_ETBEI) {
|
||||
while (irr & ADUCM_UART_IIR_STA_TX_EMPTY) {
|
||||
msg_t b;
|
||||
|
||||
osalSysLockFromISR();
|
||||
b = oqGetI(&sdp->oqueue);
|
||||
if (b < MSG_OK) {
|
||||
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
|
||||
sdp->uart->COMIEN = ien & ~COMIEN_ETBEI;
|
||||
sdp->uart->IEN = ien & ~ADUCM_UART_IEN_ETBEI;
|
||||
osalSysUnlockFromISR();
|
||||
break;
|
||||
}
|
||||
sdp->uart->COMTX = b;
|
||||
sdp->uart->DATA = b;
|
||||
osalSysUnlockFromISR();
|
||||
|
||||
irr = sdp->uart->COMIIR;
|
||||
irr = sdp->uart->IIR;
|
||||
}
|
||||
}
|
||||
|
||||
if(irr == COMIIR_STA_RXLINESTATUS) {
|
||||
if(irr == ADUCM_UART_IIR_STA_LINE) {
|
||||
uint32_t lsr;
|
||||
|
||||
/* Clearing the interrupt. */
|
||||
lsr = sdp->uart->COMLSR;
|
||||
lsr = sdp->uart->LSR;
|
||||
|
||||
/* Error handling. */
|
||||
if(lsr & 0x0EU) {
|
||||
set_error(sdp, lsr);
|
||||
}
|
||||
|
||||
/* Error handling. */
|
||||
if(lsr & COMLSR_TEMT) {
|
||||
if(lsr & (ADUCM_UART_LSR_FE | ADUCM_UART_LSR_PE | ADUCM_UART_LSR_OE)) {
|
||||
set_error(sdp, lsr);
|
||||
}
|
||||
|
||||
/* Physical transmission end.*/
|
||||
if (lsr & COMLSR_TEMT) {
|
||||
if (lsr & ADUCM_UART_LSR_TEMT) {
|
||||
osalSysLockFromISR();
|
||||
if (oqIsEmptyI(&sdp->oqueue)) {
|
||||
chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@
|
|||
#ifndef HAL_SERIAL_LLD_H
|
||||
#define HAL_SERIAL_LLD_H
|
||||
|
||||
#include "aducm_uart.h"
|
||||
|
||||
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -57,6 +59,15 @@
|
|||
#define ADUCM_SERIAL_USE_UART0 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for UART1 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(ADUCM_SERIAL_USE_UART1) || defined(__DOXYGEN__)
|
||||
#define ADUCM_SERIAL_USE_UART1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART0 interrupt priority level setting.
|
||||
*/
|
||||
|
|
@ -64,6 +75,13 @@
|
|||
#define ADUCM_SERIAL_UART0_PRIORITY 12
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(ADUCM_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define ADUCM_SERIAL_UART1_PRIORITY 12
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Input buffer size for UART0.
|
||||
*/
|
||||
|
|
@ -79,14 +97,47 @@
|
|||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Input buffer size for UART1.
|
||||
*/
|
||||
#if !defined(ADUCM_SERIAL_UART1_IN_BUF_SIZE) || defined(__DOXYGEN__)
|
||||
#define ADUCM_SERIAL_UART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Output buffer size for UART1.
|
||||
*/
|
||||
#if !defined(ADUCM_SERIAL_UART1_OUT_BUF_SIZE) || defined(__DOXYGEN__)
|
||||
#define ADUCM_SERIAL_UART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !ADUCM_SERIAL_USE_UART0
|
||||
#if ADUCM_SERIAL_USE_UART0 && !ADUCM_HAS_UART0
|
||||
#error "UART0 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if ADUCM_SERIAL_USE_UART1 && !ADUCM_HAS_UART1
|
||||
#error "UART1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !ADUCM_SERIAL_USE_UART0 && !ADUCM_SERIAL_USE_UART1
|
||||
#error "SERIAL driver activated but no UART peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if ADUCM_SERIAL_USE_UART0 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(ADUCM_SERIAL_UART0_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to UART0"
|
||||
#endif
|
||||
|
||||
#if ADUCM_SERIAL_USE_UART1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(ADUCM_SERIAL_UART1_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to UART1"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -124,7 +175,7 @@ typedef struct {
|
|||
output_queue_t oqueue; \
|
||||
/* End of the mandatory fields.*/ \
|
||||
/* Pointer to the UART registers block.*/ \
|
||||
ADI_UART_TypeDef *uart; \
|
||||
aducm_uart_t *uart; \
|
||||
/* Clock frequency for the associated UART.*/ \
|
||||
uint32_t clock;
|
||||
|
||||
|
|
@ -136,9 +187,12 @@ typedef struct {
|
|||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (ADUCM_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
|
||||
#if ADUCM_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
|
||||
extern SerialDriver SD0;
|
||||
#endif
|
||||
#if ADUCM_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
|
||||
extern SerialDriver SD1;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
|
|||
Loading…
Reference in New Issue