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Fixed bug #1182. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14689 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-08-20 09:51:17 +00:00
parent 33de459b33
commit 55252838ab
2 changed files with 26 additions and 21 deletions
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45
os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
View File

@ -76,18 +76,21 @@
#define ADC_IER_AWD1IE ADC_IER_AWD1
#endif
#if !defined(ADC_CR_ADVREGEN)
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_0
#endif
#if !defined(ADC_CR_DEEPPWD)
#define ADC_CR_DEEPPWD ADC_CR_ADVREGEN_1
#endif
#if !defined(ADC_ISR_ADRDY)
#define ADC_ISR_ADRDY ADC_ISR_ADRD
#endif
/* The following bits are too different in the various headers, just
redefining those here. Values can be overridden by placing definitions
in hal_lld.h.*/
#if !defined(STM32_ADC_CR_ADVREGEN)
#define STM32_ADC_CR_ADVREGEN (1U << 28)
#endif
#if !defined(STM32_ADC_CR_DEEPPWD)
#define STM32_ADC_CR_DEEPPWD (1U << 29)
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -134,9 +137,9 @@ static uint32_t clkmask;
static void adc_lld_vreg_on(ADCDriver *adcp) {
adcp->adcm->CR = 0; /* See RM.*/
adcp->adcm->CR = ADC_CR_ADVREGEN;
adcp->adcm->CR = STM32_ADC_CR_ADVREGEN;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADVREGEN;
adcp->adcs->CR = STM32_ADC_CR_ADVREGEN;
#endif
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));
}
@ -149,10 +152,10 @@ static void adc_lld_vreg_on(ADCDriver *adcp) {
static void adc_lld_vreg_off(ADCDriver *adcp) {
adcp->adcm->CR = 0; /* See RM.*/
adcp->adcm->CR = ADC_CR_DEEPPWD;
adcp->adcm->CR = STM32_ADC_CR_DEEPPWD;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = 0;
adcp->adcs->CR = ADC_CR_DEEPPWD;
adcp->adcs->CR = STM32_ADC_CR_DEEPPWD;
#endif
}
@ -163,19 +166,19 @@ static void adc_lld_vreg_off(ADCDriver *adcp) {
*/
static void adc_lld_calibrate(ADCDriver *adcp) {
osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state");
osalDbgAssert(adcp->adcm->CR == STM32_ADC_CR_ADVREGEN, "invalid register state");
/* Differential calibration for master ADC.*/
adcp->adcm->CR = ADC_CR_ADVREGEN | ADC_CR_ADCALDIF;
adcp->adcm->CR = ADC_CR_ADVREGEN | ADC_CR_ADCALDIF | ADC_CR_ADCAL;
adcp->adcm->CR = STM32_ADC_CR_ADVREGEN | ADC_CR_ADCALDIF;
adcp->adcm->CR = STM32_ADC_CR_ADVREGEN | ADC_CR_ADCALDIF | ADC_CR_ADCAL;
while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
;
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));
/* Single-ended calibration for master ADC.*/
adcp->adcm->CR = ADC_CR_ADVREGEN;
adcp->adcm->CR = ADC_CR_ADVREGEN | ADC_CR_ADCAL;
adcp->adcm->CR = STM32_ADC_CR_ADVREGEN;
adcp->adcm->CR = STM32_ADC_CR_ADVREGEN | ADC_CR_ADCAL;
while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
;
@ -185,16 +188,16 @@ static void adc_lld_calibrate(ADCDriver *adcp) {
osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN, "invalid register state");
/* Differential calibration for slave ADC.*/
adcp->adcs->CR = ADC_CR_ADVREGEN | ADC_CR_ADCALDIF;
adcp->adcs->CR = ADC_CR_ADVREGEN | ADC_CR_ADCALDIF | ADC_CR_ADCAL;
adcp->adcs->CR = STM32_ADC_CR_ADVREGEN | ADC_CR_ADCALDIF;
adcp->adcs->CR = STM32_ADC_CR_ADVREGEN | ADC_CR_ADCALDIF | ADC_CR_ADCAL;
while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
;
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));
/* Single-ended calibration for slave ADC.*/
adcp->adcs->CR = ADC_CR_ADVREGEN;
adcp->adcs->CR = ADC_CR_ADVREGEN | ADC_CR_ADCAL;
adcp->adcs->CR = STM32_ADC_CR_ADVREGEN;
adcp->adcs->CR = STM32_ADC_CR_ADVREGEN | ADC_CR_ADCAL;
while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
;

2
readme.txt
View File

@ -77,6 +77,8 @@
- NEW: EFL driver and demo for STM32F3xx.
- NEW: New unit test subsystem under /os/test. Now it is officially
ChibiOS/TEST.
- FIX: Fixed STM32 ADCv3 differences in headers (bug #1182)
(TBP)(backported to 20.3.4).
- FIX: Fixed DMAv1 compile fail on STM32L011 (bug #1181)
(TBP)(backported to 20.3.4).
- FIX: Fixed error in STM32_ADCCLK_MIN for STM32F37x/hal_lld.h (bug #1180)