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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5149 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-02-10 16:46:08 +00:00
parent f116535a69
commit 58d24be416
5 changed files with 1671 additions and 0 deletions
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20
os/hal/platforms/STM32F37x/platform.mk Normal file
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# List of all the STM32F37x platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F37x/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F37x/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F37x \
${CHIBIOS}/os/hal/platforms/STM32 \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2 \
${CHIBIOS}/os/hal/platforms/STM32/USBv1

454
os/hal/platforms/STM32F37x/stm32_dma.c Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F37x/stm32_dma.c
* @brief DMA helper driver code.
*
* @addtogroup STM32F37x_DMA
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
* shared resource, this driver allows to allocate and free DMA
* streams at runtime in order to allow all the other device
* drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
* ISRs when allocating streams.
* @{
*/
#include "ch.h"
#include "hal.h"
/* The following macro is only defined if some driver requiring DMA services
has been enabled.*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/
#define STM32_DMA1_STREAMS_MASK 0x0000007F
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
*/
#define STM32_DMA2_STREAMS_MASK 0x00000F80
/**
* @brief Post-reset value of the stream CCR register.
*/
#define STM32_DMA_CCR_RESET_VALUE 0x00000000
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief DMA streams descriptors.
* @details This table keeps the association between an unique stream
* identifier and the involved physical registers.
* @note Don't use this array directly, use the appropriate wrapper macros
* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
{DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
{DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
{DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
{DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
{DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
{DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
{DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
{DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
{DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
{DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
{DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
};
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief DMA ISR redirector type.
*/
typedef struct {
stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
void *dma_param; /**< @brief DMA callback parameter. */
} dma_isr_redir_t;
/**
* @brief Mask of the allocated streams.
*/
static uint32_t dma_streams_mask;
/**
* @brief DMA IRQ redirectors.
*/
static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief DMA1 stream 1 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector6C) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[0].dma_func)
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 stream 2 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector70) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
if (dma_isr_redir[1].dma_func)
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 stream 3 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector74) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
if (dma_isr_redir[2].dma_func)
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 stream 4 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector78) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
if (dma_isr_redir[3].dma_func)
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 stream 5 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector7C) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[4].dma_func)
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 stream 6 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector80) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
if (dma_isr_redir[5].dma_func)
dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 stream 7 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector84) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
if (dma_isr_redir[6].dma_func)
dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA2 stream 1 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector120) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[7].dma_func)
dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA2 stream 2 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector124) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
if (dma_isr_redir[8].dma_func)
dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA2 stream 3 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector128) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
if (dma_isr_redir[9].dma_func)
dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA2 stream 4 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector12C) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
if (dma_isr_redir[10].dma_func)
dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA2 stream 5 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector130) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[11].dma_func)
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief STM32 DMA helper initialization.
*
* @init
*/
void dmaInit(void) {
int i;
dma_streams_mask = 0;
for (i = 0; i < STM32_DMA_STREAMS; i++) {
_stm32_dma_streams[i].channel->CCR = 0;
dma_isr_redir[i].dma_func = NULL;
}
DMA1->IFCR = 0xFFFFFFFF;
#if STM32_HAS_DMA2
DMA2->IFCR = 0xFFFFFFFF;
#endif
}
/**
* @brief Allocates a DMA stream.
* @details The stream is allocated and, if required, the DMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] priority IRQ priority mask for the DMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval FALSE no error, stream taken.
* @retval TRUE error, stream already taken.
*
* @special
*/
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
uint32_t priority,
stm32_dmaisr_t func,
void *param) {
chDbgCheck(dmastp != NULL, "dmaAllocate");
/* Checks if the stream is already taken.*/
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
return TRUE;
/* Marks the stream as allocated.*/
dma_isr_redir[dmastp->selfindex].dma_func = func;
dma_isr_redir[dmastp->selfindex].dma_param = param;
dma_streams_mask |= (1 << dmastp->selfindex);
/* Enabling DMA clocks required by the current streams set.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
rccEnableDMA1(FALSE);
#if STM32_HAS_DMA2
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
rccEnableDMA2(FALSE);
#endif
/* Putting the stream in a safe state.*/
dmaStreamDisable(dmastp);
dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
/* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL)
nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
return FALSE;
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
chDbgCheck(dmastp != NULL, "dmaRelease");
/* Check if the streams is not taken.*/
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
"dmaRelease(), #1", "not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex);
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
rccDisableDMA1(FALSE);
#if STM32_HAS_DMA2
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
rccDisableDMA2(FALSE);
#endif
}
#endif /* STM32_DMA_REQUIRED */
/** @} */

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os/hal/platforms/STM32F37x/stm32_dma.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F37x/stm32_dma.h
* @brief DMA helper driver header.
* @note This file requires definitions from the ST header file stm32f30x.h.
* @note This driver uses the new naming convention used for the STM32F2xx
* so the "DMA channels" are referred as "DMA streams".
*
* @addtogroup STM32F37x_DMA
* @{
*/
#ifndef _STM32_DMA_H_
#define _STM32_DMA_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Total number of DMA streams.
* @note This is the total number of streams among all the DMA units.
*/
#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
#define STM32_DMA_STREAMS 12
#else
#define STM32_DMA_STREAMS 7
#endif
/**
* @brief Mask of the ISR bits passed to the DMA callback functions.
*/
#define STM32_DMA_ISR_MASK 0x0F
/**
* @brief Returns the channel associated to the specified stream.
*
* @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
* @param[in] c a stream/channel association word, one channel per
* nibble, not associated channels must be set to 0xF
* @return Always zero, in this platform there is no dynamic
* association between streams and channels.
*/
#define STM32_DMA_GETCHANNEL(n, c) 0
/**
* @brief Checks if a DMA priority is within the valid range.
* @param[in] prio DMA priority
*
* @retval The check result.
* @retval FALSE invalid DMA priority.
* @retval TRUE correct DMA priority.
*/
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
/**
* @brief Returns an unique numeric identifier for a DMA stream.
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
/**
* @brief Returns a DMA stream identifier mask.
*
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return A DMA stream identifier mask.
*/
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
(1 << STM32_DMA_STREAM_ID(dma, stream))
/**
* @brief Checks if a DMA stream unique identifier belongs to a mask.
* @param[in] id the stream numeric identifier
* @param[in] mask the stream numeric identifiers mask
*
* @retval The check result.
* @retval FALSE id does not belong to the mask.
* @retval TRUE id belongs to the mask.
*/
#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
/**
* @name DMA streams identifiers
* @{
*/
/**
* @brief Returns a pointer to a stm32_dma_stream_t structure.
*
* @param[in] id the stream numeric identifier
* @return A pointer to the stm32_dma_stream_t constant structure
* associated to the DMA stream.
*/
#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7)
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8)
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9)
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10)
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11)
/** @} */
/**
* @name CR register constants common to all DMA types
* @{
*/
#define STM32_DMA_CR_EN DMA_CCR_EN
#define STM32_DMA_CR_TEIE DMA_CCR_TEIE
#define STM32_DMA_CR_HTIE DMA_CCR_HTIE
#define STM32_DMA_CR_TCIE DMA_CCR_TCIE
#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
#define STM32_DMA_CR_DIR_P2M 0
#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR
#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM
#define STM32_DMA_CR_CIRC DMA_CCR_CIRC
#define STM32_DMA_CR_PINC DMA_CCR_PINC
#define STM32_DMA_CR_MINC DMA_CCR_MINC
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE
#define STM32_DMA_CR_PSIZE_BYTE 0
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE
#define STM32_DMA_CR_MSIZE_BYTE 0
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
STM32_DMA_CR_MSIZE_MASK)
#define STM32_DMA_CR_PL_MASK DMA_CCR_PL
#define STM32_DMA_CR_PL(n) ((n) << 12)
/** @} */
/**
* @name CR register constants only found in enhanced DMA
* @{
*/
#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
/** @} */
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
#define STM32_DMA_ISR_FEIF 0
#define STM32_DMA_ISR_DMEIF 0
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief STM32 DMA stream descriptor structure.
*/
typedef struct {
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
uint8_t ishift; /**< @brief Bits offset in xIFCR
register. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_dma_stream_t;
/**
* @brief STM32 DMA ISR function type.
*
* @param[in] p parameter for the registered function
* @param[in] flags pre-shifted content of the ISR register, the bits
* are aligned to bit zero
*/
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Associates a peripheral data register to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] addr value to be written in the CPAR register
*
* @special
*/
#define dmaStreamSetPeripheral(dmastp, addr) { \
(dmastp)->channel->CPAR = (uint32_t)(addr); \
}
/**
* @brief Associates a memory destination to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] addr value to be written in the CMAR register
*
* @special
*/
#define dmaStreamSetMemory0(dmastp, addr) { \
(dmastp)->channel->CMAR = (uint32_t)(addr); \
}
/**
* @brief Sets the number of transfers to be performed.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] size value to be written in the CNDTR register
*
* @special
*/
#define dmaStreamSetTransactionSize(dmastp, size) { \
(dmastp)->channel->CNDTR = (uint32_t)(size); \
}
/**
* @brief Returns the number of transfers to be performed.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @return The number of transfers to be performed.
*
* @special
*/
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
/**
* @brief Programs the stream mode settings.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register
*
* @special
*/
#define dmaStreamSetMode(dmastp, mode) { \
(dmastp)->channel->CCR = (uint32_t)(mode); \
}
/**
* @brief DMA stream enable.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamEnable(dmastp) { \
(dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
}
/**
* @brief DMA stream disable.
* @details The function disables the specified stream and then clears any
* pending interrupt.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamDisable(dmastp) { \
(dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \
dmaStreamClearInterrupt(dmastp); \
}
/**
* @brief DMA stream interrupt sources clear.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
}
/**
* @brief Starts a memory to memory operation using the specified stream.
* @note The default transfer data mode is "byte to byte" but it can be
* changed by specifying extra options in the @p mode parameter.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register, this value
* is implicitly ORed with:
* - @p STM32_DMA_CR_MINC
* - @p STM32_DMA_CR_PINC
* - @p STM32_DMA_CR_DIR_M2M
* - @p STM32_DMA_CR_EN
* .
* @param[in] src source address
* @param[in] dst destination address
* @param[in] n number of data units to copy
*/
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
dmaStreamSetPeripheral(dmastp, src); \
dmaStreamSetMemory0(dmastp, dst); \
dmaStreamSetTransactionSize(dmastp, n); \
dmaStreamSetMode(dmastp, (mode) | \
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
}
/**
* @brief Polled wait for DMA transfer end.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*/
#define dmaWaitCompletion(dmastp) { \
while ((dmastp)->channel->CNDTR > 0) \
; \
dmaStreamDisable(dmastp); \
}
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
#endif
#ifdef __cplusplus
extern "C" {
#endif
void dmaInit(void);
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
uint32_t priority,
stm32_dmaisr_t func,
void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}
#endif
#endif /* _STM32_DMA_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F37x/stm32_isr.h
* @brief ISR remapper driver header.
*
* @addtogroup STM32F37x_ISR
* @{
*/
#ifndef _STM32_ISR_H_
#define _STM32_ISR_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
/*
* CAN units.
*/
#define STM32_CAN1_TX_HANDLER Vector8C
#define STM32_CAN1_RX0_HANDLER Vector90
#define STM32_CAN1_RX1_HANDLER Vector94
#define STM32_CAN1_SCE_HANDLER Vector98
#define STM32_CAN1_TX_NUMBER 19
#define STM32_CAN1_RX0_NUMBER 20
#define STM32_CAN1_RX1_NUMBER 21
#define STM32_CAN1_SCE_NUMBER 22
/*
* TIM units.
*/
#define STM32_TIM2_HANDLER VectorB0
#define STM32_TIM3_HANDLER VectorB4
#define STM32_TIM4_HANDLER VectorB8
#define STM32_TIM5_HANDLER Vector108
#define STM32_TIM2_NUMBER 28
#define STM32_TIM3_NUMBER 29
#define STM32_TIM4_NUMBER 30
#define STM32_TIM5_NUMBER 50
/*
* USART units.
*/
#define STM32_USART1_HANDLER VectorD4
#define STM32_USART2_HANDLER VectorD8
#define STM32_USART3_HANDLER VectorDC
#define STM32_USART1_NUMBER 37
#define STM32_USART2_NUMBER 38
#define STM32_USART3_NUMBER 39
/*
* USB units.
*/
#define STM32_USB1_HP_HANDLER Vector168
#define STM32_USB1_LP_HANDLER Vector16C
#define STM32_USB1_HP_NUMBER 74
#define STM32_USB1_LP_NUMBER 75
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* _STM32_ISR_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F37x/stm32_rcc.h
* @brief RCC helper driver header.
* @note This file requires definitions from the ST header file
* @p stm32f30x.h.
*
* @addtogroup STM32F37x_RCC
* @{
*/
#ifndef _STM32_RCC_
#define _STM32_RCC_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Generic RCC operations
* @{
*/
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB1(mask, lp) { \
RCC->APB1ENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAPB1(mask, lp) { \
RCC->APB1ENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
*
* @api
*/
#define rccResetAPB1(mask) { \
RCC->APB1RSTR |= (mask); \
RCC->APB1RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB2(mask, lp) { \
RCC->APB2ENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAPB2(mask, lp) { \
RCC->APB2ENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccResetAPB2(mask) { \
RCC->APB2RSTR |= (mask); \
RCC->APB2RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAHB(mask, lp) { \
RCC->AHBENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAHB(mask, lp) { \
RCC->AHBENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define rccResetAHB(mask) { \
RCC->AHBRSTR |= (mask); \
RCC->AHBRSTR = 0; \
}
/** @} */
/**
* @name ADC1 peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the ADC peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
* @brief Disables the ADC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
* @brief Resets the ADC1 peripheral.
*
* @api
*/
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */
/**
* @name CAN peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the CAN1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
/**
* @brief Disables the CAN1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
/**
* @brief Resets the CAN1 peripheral.
*
* @api
*/
#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
/** @} */
/**
* @name DMA peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DMA1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
/**
* @brief Disables the DMA1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
/**
* @brief Resets the DMA1 peripheral.
*
* @api
*/
#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
/**
* @brief Enables the DMA2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
/**
* @brief Disables the DMA2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
/**
* @brief Resets the DMA2 peripheral.
*
* @api
*/
#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
/** @} */
/**
* @name PWR interface specific RCC operations
* @{
*/
/**
* @brief Enables the PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Disables PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Resets the PWR interface.
*
* @api
*/
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**
* @name I2C peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the I2C1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
* @brief Disables the I2C1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
* @brief Resets the I2C1 peripheral.
*
* @api
*/
#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
/**
* @brief Enables the I2C2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
* @brief Disables the I2C2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
* @brief Resets the I2C2 peripheral.
*
* @api
*/
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
/** @} */
/**
* @name SPI peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the SPI1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
* @brief Disables the SPI1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
* @brief Resets the SPI1 peripheral.
*
* @api
*/
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
/**
* @brief Enables the SPI2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
* @brief Disables the SPI2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
* @brief Resets the SPI2 peripheral.
*
* @api
*/
#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
/**
* @brief Enables the SPI3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
/**
* @brief Disables the SPI3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
/**
* @brief Resets the SPI3 peripheral.
*
* @api
*/
#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
/** @} */
/**
* @name TIM peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the TIM2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
* @brief Disables the TIM2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
* @brief Resets the TIM2 peripheral.
*
* @api
*/
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
* @brief Enables the TIM3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
* @brief Disables the TIM3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
* @brief Resets the TIM3 peripheral.
*
* @api
*/
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
/**
* @brief Enables the TIM4 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
/**
* @brief Disables the TIM4 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
/**
* @brief Resets the TIM4 peripheral.
*
* @api
*/
#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
/**
* @brief Enables the TIM5 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
/**
* @brief Disables the TIM5 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
/**
* @brief Resets the TIM5 peripheral.
*
* @api
*/
#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
/** @} */
/**
* @name USART/UART peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the USART1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
* @brief Disables the USART1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
* @brief Resets the USART1 peripheral.
*
* @api
*/
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
/**
* @brief Enables the USART2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
* @brief Disables the USART2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
* @brief Resets the USART2 peripheral.
*
* @api
*/
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
/**
* @brief Enables the USART3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
/**
* @brief Disables the USART3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
/**
* @brief Resets the USART3 peripheral.
*
* @api
*/
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
/** @} */
/**
* @name USB peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the USB peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
/**
* @brief Disables the USB peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
/**
* @brief Resets the USB peripheral.
*
* @api
*/
#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _STM32_RCC_ */
/** @} */