mirror of https://github.com/rusefi/ChibiOS.git
Update RTCv3 (handle G4/G0 differences)
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13123 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -257,28 +257,22 @@ struct RTCDriverVMT _rtc_lld_vmt = {
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};
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#endif /* RTC_HAS_STORAGE == TRUE */
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if defined(STM32_RTC_COMMON_HANDLER)
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#if !defined(STM32_RTC_SUPPRESS_COMMON_ISR)
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/**
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* @brief RTC common interrupt handler.
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* @brief RTC ISR service routine.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
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static void rtc_lld_serve_interrupt(void) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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/* Get the interrupt events. */
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/* Get and clear the RTC interrupts. */
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isr = RTCD1.rtc->MISR;
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RTCD1.rtc->SCR = isr;
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extiClearGroup1(EXTI_MASK1(STM32_RTC_EVENT_EXTI) |
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EXTI_MASK1(STM32_TAMP_EVENT_EXTI));
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/* Clear EXTI events. */
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STM32_RTC_CLEAR_ALL_EXTI();
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/* Process call backs if enabled. */
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if (RTCD1.callback != NULL) {
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#if defined(RTC_MISR_WUTMF)
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@ -308,7 +302,7 @@ OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
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}
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#endif
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/* Next handle the tamper interrupts. */
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/* Get and clear the TAMP interrupts. */
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isr = RTCD1.tamp->MISR;
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RTCD1.tamp->SCR = isr;
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#if defined(TAMP_MISR_TAMP1MF)
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@ -321,34 +315,96 @@ OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
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RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2);
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}
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#endif
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#if defined(TAMP_MISR_TAMP3MF)
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if ((isr & TAMP_MISR_TAMP3MF) != 0U) {
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#if defined(TAMP_MISR_ITAMP3MF)
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if ((isr & TAMP_MISR_ITAMP3MF) != 0U) {
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RTCD1.callback(&RTCD1, RTC_EVENT_TAMP3);
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}
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#endif
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#if defined(TAMP_MISR_TAMP4MF)
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if ((isr & TAMP_MISR_TAMP4MF) != 0U) {
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#if defined(TAMP_MISR_ITAMP4MF)
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if ((isr & TAMP_MISR_ITAMP4MF) != 0U) {
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RTCD1.callback(&RTCD1, RTC_EVENT_TAMP4);
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}
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#endif
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#if defined(TAMP_MISR_TAMP5MF)
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if ((isr & TAMP_MISR_TAMP5MF) != 0U) {
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#if defined(TAMP_MISR_ITAMP5MF)
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if ((isr & TAMP_MISR_ITAMP5MF) != 0U) {
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RTCD1.callback(&RTCD1, RTC_EVENT_TAMP5);
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}
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#endif
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#if defined(TAMP_MISR_TAMP6MF)
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if ((isr & TAMP_MISR_TAMP6MF) != 0U) {
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#if defined(TAMP_MISR_ITAMP6MF)
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if ((isr & TAMP_MISR_ITAMP6MF) != 0U) {
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RTCD1.callback(&RTCD1, RTC_EVENT_TAMP6);
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}
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#endif
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if defined(STM32_RTC_COMMON_HANDLER)
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#if !defined(STM32_RTC_SUPPRESS_COMMON_ISR)
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/**
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* @brief RTC common interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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rtc_lld_serve_interrupt();
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(STM32_RTC_SUPPRESS_COMMON_ISR) */
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#elif defined(STM32_RTC_TAMP_STAMP_HANDLER) && \
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defined(STM32_RTC_WKUP_HANDLER) && \
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defined(STM32_RTC_ALARM_HANDLER)
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/**
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* @brief RTC TAMP/STAMP interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_RTC_TAMP_STAMP_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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rtc_lld_serve_interrupt();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief RTC wakeup interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_RTC_WKUP_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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rtc_lld_serve_interrupt();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief RTC alarm interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_RTC_ALARM_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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rtc_lld_serve_interrupt();
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OSAL_IRQ_EPILOGUE();
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}
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#else
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#error "missing required RTC handlers definitions in registry"
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#error "missing required RTC handler definitions in registry"
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#endif
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/*===========================================================================*/
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@ -388,7 +444,6 @@ void rtc_lld_init(void) {
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RTCD1.rtc->ICSR &= ~RTC_ICSR_RSF;
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}
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/* TAMP pointer initialization. */
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RTCD1.tamp = TAMP;
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@ -402,15 +457,10 @@ void rtc_lld_init(void) {
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RTCD1.callback = NULL;
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/* Enabling RTC-related EXTI lines.*/
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extiEnableGroup1(EXTI_MASK1(STM32_RTC_EVENT_EXTI) |
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EXTI_MASK1(STM32_TAMP_EVENT_EXTI),
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EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT);
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/* The EXTI lines are direct. Events enabled by peripheral
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and trigger on their rising edge only */
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STM32_RTC_ENABLE_ALL_EXTI();
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/* IRQ vectors permanently assigned to this driver.*/
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STM32_RTC_AND_TAMP_IRQ_ENABLE();
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STM32_RTC_IRQ_ENABLE();
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}
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/**
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -46,14 +46,27 @@
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#define STM32_RTC_STORAGE_SIZE 20
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#define STM32_RTC_COMMON_HANDLER Vector48
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#define STM32_RTC_COMMON_NUMBER 2
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#define STM32_RTC_EVENT_EXTI 19
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#define STM32_TAMP_EVENT_EXTI 21
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#define STM32_RTC_AND_TAMP_IRQ_ENABLE() do { \
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#define STM32_RTC_EVENT_RTC_EXTI 19
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#define STM32_RTC_EVENT_TAMP_EXTI 21
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#define STM32_RTC_IRQ_ENABLE() do { \
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nvicEnableVector(STM32_RTC_COMMON_NUMBER, \
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STM32_IRQ_EXTI1921_PRIORITY); \
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} while (false)
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/* Masks used to preserve state of reserved bits. */
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/* Enabling RTC-related EXTI lines.*/
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#define STM32_RTC_ENABLE_ALL_EXTI() do { \
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extiEnableGroup1(EXTI_MASK1(STM32_RTC_EVENT_RTC_EXTI) | \
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EXTI_MASK1(STM32_RTC_EVENT_TAMP_EXTI), \
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EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
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} while (false)
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/* Clearing EXTI interrupts. */
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#define STM32_RTC_CLEAR_ALL_EXTI() do { \
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extiClearGroup1(EXTI_MASK1(STM32_RTC_EVENT_RTC_EXTI) | \
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EXTI_MASK1(STM32_RTC_EVENT_TAMP_EXTI)); \
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} while (false)
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/* Masks used to preserve state of RTC and TAMP register reserved bits. */
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#define STM32_RTC_CR_MASK 0xE7FFFF7F
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#define STM32_RTC_PRER_MASK 0x007F7FFF
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#define STM32_TAMP_CR1_MASK 0x003C0003
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -15,8 +15,8 @@
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*/
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/**
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* @file STM32L4xx+/stm32_registry.h
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* @brief STM32L4xx+ capabilities registry.
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* @file STM32G4xx/stm32_registry.h
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* @brief STM32G4xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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@ -30,7 +30,7 @@
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/*===========================================================================*/
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/**
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* @name STM32L4xx+ capabilities
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* @name STM32G4xx capabilities
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* @{
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*/
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nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
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} while (false)
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/* Enabling RTC-related EXTI lines.*/
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#define STM32_RTC_ENABLE_ALL_EXTI() do { \
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extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
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EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
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} while (false)
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/* Clearing EXTI interrupts. */
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#define STM32_RTC_CLEAR_ALL_EXTI() do { \
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extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
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} while (false)
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/* Masks used to preserve state of RTC and TAMP register reserved bits. */
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#define STM32_RTC_CR_MASK 0xE7FFFF7F
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#define STM32_RTC_PRER_MASK 0x007F7FFF
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#define STM32_TAMP_CR1_MASK 0x003C0007
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#define STM32_TAMP_CR2_MASK 0x07070007
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#define STM32_TAMP_FLTCR_MASK 0x000000FF
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#define STM32_TAMP_IER_MASK 0x003C0007
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#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \
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defined(__DOXYGEN__)
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#define STM32_HAS_HASH1 TRUE
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