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Update RTCv3 (handle G4/G0 differences) 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13123 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
cinsights 2019-10-19 14:22:46 +00:00
parent 4df6627866
commit 594259165f
3 changed files with 127 additions and 41 deletions
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114
os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.c
View File

@ -257,28 +257,22 @@ struct RTCDriverVMT _rtc_lld_vmt = {
};
#endif /* RTC_HAS_STORAGE == TRUE */
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_RTC_COMMON_HANDLER)
#if !defined(STM32_RTC_SUPPRESS_COMMON_ISR)
/**
* @brief RTC common interrupt handler.
* @brief RTC ISR service routine.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
static void rtc_lld_serve_interrupt(void) {
uint32_t isr;
OSAL_IRQ_PROLOGUE();
/* Get the interrupt events. */
/* Get and clear the RTC interrupts. */
isr = RTCD1.rtc->MISR;
RTCD1.rtc->SCR = isr;
extiClearGroup1(EXTI_MASK1(STM32_RTC_EVENT_EXTI) |
EXTI_MASK1(STM32_TAMP_EVENT_EXTI));
/* Clear EXTI events. */
STM32_RTC_CLEAR_ALL_EXTI();
/* Process call backs if enabled. */
if (RTCD1.callback != NULL) {
#if defined(RTC_MISR_WUTMF)
@ -308,7 +302,7 @@ OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
}
#endif
/* Next handle the tamper interrupts. */
/* Get and clear the TAMP interrupts. */
isr = RTCD1.tamp->MISR;
RTCD1.tamp->SCR = isr;
#if defined(TAMP_MISR_TAMP1MF)
@ -321,34 +315,96 @@ OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2);
}
#endif
#if defined(TAMP_MISR_TAMP3MF)
if ((isr & TAMP_MISR_TAMP3MF) != 0U) {
#if defined(TAMP_MISR_ITAMP3MF)
if ((isr & TAMP_MISR_ITAMP3MF) != 0U) {
RTCD1.callback(&RTCD1, RTC_EVENT_TAMP3);
}
#endif
#if defined(TAMP_MISR_TAMP4MF)
if ((isr & TAMP_MISR_TAMP4MF) != 0U) {
#if defined(TAMP_MISR_ITAMP4MF)
if ((isr & TAMP_MISR_ITAMP4MF) != 0U) {
RTCD1.callback(&RTCD1, RTC_EVENT_TAMP4);
}
#endif
#if defined(TAMP_MISR_TAMP5MF)
if ((isr & TAMP_MISR_TAMP5MF) != 0U) {
#if defined(TAMP_MISR_ITAMP5MF)
if ((isr & TAMP_MISR_ITAMP5MF) != 0U) {
RTCD1.callback(&RTCD1, RTC_EVENT_TAMP5);
}
#endif
#if defined(TAMP_MISR_TAMP6MF)
if ((isr & TAMP_MISR_TAMP6MF) != 0U) {
#if defined(TAMP_MISR_ITAMP6MF)
if ((isr & TAMP_MISR_ITAMP6MF) != 0U) {
RTCD1.callback(&RTCD1, RTC_EVENT_TAMP6);
}
#endif
}
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_RTC_COMMON_HANDLER)
#if !defined(STM32_RTC_SUPPRESS_COMMON_ISR)
/**
* @brief RTC common interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_RTC_COMMON_HANDLER) {
OSAL_IRQ_PROLOGUE();
rtc_lld_serve_interrupt();
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(STM32_RTC_SUPPRESS_COMMON_ISR) */
#elif defined(STM32_RTC_TAMP_STAMP_HANDLER) && \
defined(STM32_RTC_WKUP_HANDLER) && \
defined(STM32_RTC_ALARM_HANDLER)
/**
* @brief RTC TAMP/STAMP interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_RTC_TAMP_STAMP_HANDLER) {
OSAL_IRQ_PROLOGUE();
rtc_lld_serve_interrupt();
OSAL_IRQ_EPILOGUE();
}
/**
* @brief RTC wakeup interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_RTC_WKUP_HANDLER) {
OSAL_IRQ_PROLOGUE();
rtc_lld_serve_interrupt();
OSAL_IRQ_EPILOGUE();
}
/**
* @brief RTC alarm interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_RTC_ALARM_HANDLER) {
OSAL_IRQ_PROLOGUE();
rtc_lld_serve_interrupt();
OSAL_IRQ_EPILOGUE();
}
#else
#error "missing required RTC handlers definitions in registry"
#error "missing required RTC handler definitions in registry"
#endif
/*===========================================================================*/
@ -388,7 +444,6 @@ void rtc_lld_init(void) {
RTCD1.rtc->ICSR &= ~RTC_ICSR_RSF;
}
/* TAMP pointer initialization. */
RTCD1.tamp = TAMP;
@ -402,15 +457,10 @@ void rtc_lld_init(void) {
RTCD1.callback = NULL;
/* Enabling RTC-related EXTI lines.*/
extiEnableGroup1(EXTI_MASK1(STM32_RTC_EVENT_EXTI) |
EXTI_MASK1(STM32_TAMP_EVENT_EXTI),
EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT);
/* The EXTI lines are direct. Events enabled by peripheral
and trigger on their rising edge only */
STM32_RTC_ENABLE_ALL_EXTI();
/* IRQ vectors permanently assigned to this driver.*/
STM32_RTC_AND_TAMP_IRQ_ENABLE();
STM32_RTC_IRQ_ENABLE();
}
/**

23
os/hal/ports/STM32/STM32G0xx/stm32_registry.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -46,14 +46,27 @@
#define STM32_RTC_STORAGE_SIZE 20
#define STM32_RTC_COMMON_HANDLER Vector48
#define STM32_RTC_COMMON_NUMBER 2
#define STM32_RTC_EVENT_EXTI 19
#define STM32_TAMP_EVENT_EXTI 21
#define STM32_RTC_AND_TAMP_IRQ_ENABLE() do { \
#define STM32_RTC_EVENT_RTC_EXTI 19
#define STM32_RTC_EVENT_TAMP_EXTI 21
#define STM32_RTC_IRQ_ENABLE() do { \
nvicEnableVector(STM32_RTC_COMMON_NUMBER, \
STM32_IRQ_EXTI1921_PRIORITY); \
} while (false)
/* Masks used to preserve state of reserved bits. */
/* Enabling RTC-related EXTI lines.*/
#define STM32_RTC_ENABLE_ALL_EXTI() do { \
extiEnableGroup1(EXTI_MASK1(STM32_RTC_EVENT_RTC_EXTI) | \
EXTI_MASK1(STM32_RTC_EVENT_TAMP_EXTI), \
EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
} while (false)
/* Clearing EXTI interrupts. */
#define STM32_RTC_CLEAR_ALL_EXTI() do { \
extiClearGroup1(EXTI_MASK1(STM32_RTC_EVENT_RTC_EXTI) | \
EXTI_MASK1(STM32_RTC_EVENT_TAMP_EXTI)); \
} while (false)
/* Masks used to preserve state of RTC and TAMP register reserved bits. */
#define STM32_RTC_CR_MASK 0xE7FFFF7F
#define STM32_RTC_PRER_MASK 0x007F7FFF
#define STM32_TAMP_CR1_MASK 0x003C0003

31
os/hal/ports/STM32/STM32G4xx/stm32_registry.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -15,8 +15,8 @@
*/
/**
* @file STM32L4xx+/stm32_registry.h
* @brief STM32L4xx+ capabilities registry.
* @file STM32G4xx/stm32_registry.h
* @brief STM32G4xx capabilities registry.
*
* @addtogroup HAL
* @{
@ -30,7 +30,7 @@
/*===========================================================================*/
/**
* @name STM32L4xx+ capabilities
* @name STM32G4xx capabilities
* @{
*/
@ -62,6 +62,29 @@
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
} while (false)
/* Enabling RTC-related EXTI lines.*/
#define STM32_RTC_ENABLE_ALL_EXTI() do { \
extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
} while (false)
/* Clearing EXTI interrupts. */
#define STM32_RTC_CLEAR_ALL_EXTI() do { \
extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
} while (false)
/* Masks used to preserve state of RTC and TAMP register reserved bits. */
#define STM32_RTC_CR_MASK 0xE7FFFF7F
#define STM32_RTC_PRER_MASK 0x007F7FFF
#define STM32_TAMP_CR1_MASK 0x003C0007
#define STM32_TAMP_CR2_MASK 0x07070007
#define STM32_TAMP_FLTCR_MASK 0x000000FF
#define STM32_TAMP_IER_MASK 0x003C0007
#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \
defined(__DOXYGEN__)
#define STM32_HAS_HASH1 TRUE