From 5a80fa2049c7dc2590208e7dd0614573236ad716 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 19 Sep 2020 10:23:08 +0000
Subject: [PATCH] Fixed BD initialization.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13859 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 .../RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h     |  2 +-
 os/hal/ports/STM32/STM32G4xx/hal_lld.c        | 26 +++++++++++------
 os/hal/ports/STM32/STM32L5xx/hal_lld.c        | 29 ++++++++++++++-----
 3 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
index 761b7b7bf..0c7c09845 100644
--- a/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
@@ -86,7 +86,7 @@
 #define STM32_ADC12SEL                      STM32_ADC12SEL_PLLPCLK
 #define STM32_ADC345SEL                     STM32_ADC345SEL_PLLPCLK
 #define STM32_QSPISEL                       STM32_QSPISEL_SYSCLK
-#define STM32_RTCSEL                        STM32_RTCSEL_NOCLOCK
+#define STM32_RTCSEL                        STM32_RTCSEL_LSE
 
 /*
  * IRQ system settings.
diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
index d5ea1baeb..5980ccdfe 100644
--- a/os/hal/ports/STM32/STM32G4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
@@ -46,9 +46,22 @@ uint32_t SystemCoreClock = STM32_HCLK;
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
+/**
+ * @brief   Resets the backup domain.
+ */
+__STATIC_INLINE void bd_reset(void) {
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0U;
+  }
+}
+
 /**
  * @brief   Initializes the backup domain.
- * @note    WARNING! Changing RTC clock source impossible without resetting
+ * @note    WARNING! Changing RTC clock source impossible without reset
  *          of the whole BKP domain.
  */
 __STATIC_INLINE void bd_init(void) {
@@ -57,14 +70,6 @@ __STATIC_INLINE void bd_init(void) {
   /* Current settings.*/
   bdcr = RCC->BDCR;
 
-  /* Reset BKP domain if different clock source selected.*/
-  if ((bdcr & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0U;
-    bdcr = 0U;
-  }
-
 #if HAL_USE_RTC
   /* RTC clock enabled.*/
   if ((bdcr & RCC_BDCR_RTCEN) == 0) {
@@ -146,6 +151,9 @@ void stm32_clock_init(void) {
   PWR->CR4 = STM32_PWR_CR4;
   PWR->CR5 = STM32_CR5BITS;
 
+  /* Backup domain reset.*/
+  bd_reset();
+
   /* Clocks setup.*/
   lse_init();
   lsi_init();
diff --git a/os/hal/ports/STM32/STM32L5xx/hal_lld.c b/os/hal/ports/STM32/STM32L5xx/hal_lld.c
index 64b49bef4..4a5e22ec0 100644
--- a/os/hal/ports/STM32/STM32L5xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L5xx/hal_lld.c
@@ -52,20 +52,30 @@ uint32_t SystemCoreClock = STM32_HCLK;
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
+/**
+ * @brief   Resets the backup domain.
+ */
+__STATIC_INLINE void bd_reset(void) {
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0U;
+  }
+}
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing RTC clock source impossible without reset
+ *          of the whole BKP domain.
+ */
 __STATIC_INLINE void bd_init(void) {
   uint32_t bdcr;
 
   /* Current settings.*/
   bdcr = RCC->BDCR;
 
-  /* Reset BKP domain if different clock source selected.*/
-  if ((bdcr & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0U;
-    bdcr = 0U;
-  }
-
 #if HAL_USE_RTC
   /* RTC enable.*/
   if ((bdcr & RCC_BDCR_RTCEN) == 0U) {
@@ -165,6 +175,9 @@ void stm32_clock_init(void) {
   PWR->CR3 = STM32_PWR_CR3;
   PWR->CR4 = STM32_PWR_CR4;
 
+  /* Backup domain reset.*/
+  bd_reset();
+
   /* Setting the wait states required by MSI clock.*/
   flash_ws_init(STM32_MSI_FLASHBITS);