mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2092 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -101,6 +101,38 @@ typedef struct {
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#define STM32_DMA2_CH5 (STM32_DMA2->channels[4])
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#define STM32_DMA2_CH5 (STM32_DMA2->channels[4])
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#endif
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#endif
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#define STM32_DMA_CHANNEL_1 0
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#define STM32_DMA_CHANNEL_2 1
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#define STM32_DMA_CHANNEL_3 2
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#define STM32_DMA_CHANNEL_4 3
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#define STM32_DMA_CHANNEL_5 4
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#define STM32_DMA_CHANNEL_6 5
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#define STM32_DMA_CHANNEL_7 6
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/**
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* @brief DMA channel setup.
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* @note This macro does not change the CPAR register because that register
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* value does not change frequently, it usually points to a peripheral
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* data register.
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* @note Channels are numbered from 0 to 6, use the appropriate macro
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* as parameter.
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*/
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#define dmaSetupChannel(dmap, ch, cndtr, cmar, ccr) { \
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stm32_dma_channel_t *dmachp = &dmap->channels[ch]; \
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(dmachp)->CNDTR = (uint32_t)(cndtr); \
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(dmachp)->CMAR = (uint32_t)(cmar); \
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(dmachp)->CCR = (uint32_t)(ccr); \
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}
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/**
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* @brief DMA channel disable.
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* @note Channel's pending interrupt are cleared.
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*/
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#define dmaDisableChannel(dmap, ch) { \
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(dmap)->channels[ch].CCR = 0; \
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(dmap)->IFCR = 0xF << (ch); \
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}
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/* External declarations. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -54,7 +54,7 @@ UARTDriver UARTD1;
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}
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}
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#define dma_disable(dmap) { \
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#define dma_disable(dmap) { \
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(dmap)->CCR = 0; \
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(dmap)->CCR = 0; \
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}
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}
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#define dma_rx_setup(uartp, cndtr, cmar, ccr) \
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#define dma_rx_setup(uartp, cndtr, cmar, ccr) \
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@ -84,16 +84,18 @@ static void usart_start(UARTDriver *uartp) {
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USART_CR1_TE | USART_CR1_RE;
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USART_CR1_TE | USART_CR1_RE;
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u->CR2 = uartp->ud_config->uc_cr2 | USART_CR2_LBDIE;
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u->CR2 = uartp->ud_config->uc_cr2 | USART_CR2_LBDIE;
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u->CR3 = uartp->ud_config->uc_cr3 | USART_CR3_EIE;
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u->CR3 = uartp->ud_config->uc_cr3 | USART_CR3_EIE;
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/* Resetting eventual pending status flags.*/
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(void)u->SR; /* SR reset step 1.*/
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(void)u->SR; /* SR reset step 1.*/
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(void)u->DR; /* SR reset step 2.*/
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(void)u->DR; /* SR reset step 2.*/
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/* RX DMA channel preparation, circular 1 frame transfers, an interrupt is
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/* RX DMA channel preparation, circular 1 frame transfers, an interrupt is
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generated for each received character.*/
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generated for each received character.*/
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dma_rx_setup(uartp, 1, &uartp->ud_rxbuf,
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dmaSetupChannel(uartp->ud_dmap, uartp->ud_dmarx, 1, &uartp->ud_rxbuf,
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DMA_CCR1_TCIE | DMA_CCR1_TEIE | DMA_CCR1_CIRC | DMA_CCR1_EN);
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DMA_CCR1_TCIE | DMA_CCR1_TEIE | DMA_CCR1_CIRC | DMA_CCR1_EN);
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/* TX DMA channel preparation, simply disabled.*/
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/* TX DMA channel preparation, simply disabled.*/
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dma_disable(uartp->ud_dmatx);
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dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmatx);
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}
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}
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/**
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/**
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@ -105,8 +107,8 @@ static void usart_start(UARTDriver *uartp) {
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static void usart_stop(UARTDriver *uartp) {
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static void usart_stop(UARTDriver *uartp) {
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/* Stops RX and TX DMA channels.*/
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/* Stops RX and TX DMA channels.*/
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dma_disable(uartp->ud_dmarx);
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dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmarx);
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dma_disable(uartp->ud_dmatx);
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dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmatx);
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/* Stops USART operations.*/
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/* Stops USART operations.*/
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uartp->ud_usart->CR1 = 0;
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uartp->ud_usart->CR1 = 0;
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@ -132,11 +134,9 @@ void uart_lld_init(void) {
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RCC->APB2RSTR = 0;
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RCC->APB2RSTR = 0;
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uartObjectInit(&UARTD1);
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uartObjectInit(&UARTD1);
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UARTD1.ud_usart = USART1;
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UARTD1.ud_usart = USART1;
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UARTD1.ud_dmarx = DMA1_Channel4;
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UARTD1.ud_dmarx = STM32_DMA_CHANNEL_4;
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UARTD1.ud_dmatx = DMA1_Channel5;
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UARTD1.ud_dmatx = STM32_DMA_CHANNEL_5;
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UARTD1.ud_dmaccr = 0;
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UARTD1.ud_dmaccr = 0;
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UARTD1.ud_dmarmsk = 0xF << (4 - 1);
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UARTD1.ud_dmatmsk = 0xF << (5 - 1);
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#endif
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#endif
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}
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}
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@ -166,8 +166,8 @@ void uart_lld_start(UARTDriver *uartp) {
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uartp->ud_dmaccr = STM32_UART_USART1_DMA_PRIORITY << 12;
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uartp->ud_dmaccr = STM32_UART_USART1_DMA_PRIORITY << 12;
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if ((uartp->ud_config->uc_cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
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if ((uartp->ud_config->uc_cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
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uartp->ud_dmaccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0;
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uartp->ud_dmaccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0;
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uartp->ud_dmarx->CPAR = (uint32_t)&uartp->ud_usart->DR;
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uartp->ud_dmap->channels[uartp->ud_dmarx].CPAR = (uint32_t)&uartp->ud_usart->DR;
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uartp->ud_dmatx->CPAR = (uint32_t)&uartp->ud_usart->DR;
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uartp->ud_dmap->channels[uartp->ud_dmatx].CPAR = (uint32_t)&uartp->ud_usart->DR;
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}
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}
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uartp->ud_txstate = UART_TX_IDLE;
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uartp->ud_txstate = UART_TX_IDLE;
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uartp->ud_rxstate = UART_RX_IDLE;
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uartp->ud_rxstate = UART_RX_IDLE;
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@ -181,7 +181,7 @@ void uart_lld_start(UARTDriver *uartp) {
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*/
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*/
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void uart_lld_stop(UARTDriver *uartp) {
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void uart_lld_stop(UARTDriver *uartp) {
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if (uartp->ud_state == SD_READY) {
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if (uartp->ud_state == UART_READY) {
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usart_stop(uartp);
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usart_stop(uartp);
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#if STM32_UART_USE_USART1
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#if STM32_UART_USE_USART1
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@ -118,20 +118,18 @@ typedef struct {
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/** @brief UART driver status flags.*/
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/** @brief UART driver status flags.*/
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uartflags_t ud_flags;
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uartflags_t ud_flags;
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/* End of the mandatory fields.*/
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/* End of the mandatory fields.*/
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/** @brief Default receive buffer while into @p UART_RX_IDLE state.*/
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uint16_t ud_rxbuf;
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/** @brief Pointer to the USART registers block.*/
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/** @brief Pointer to the USART registers block.*/
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USART_TypeDef *ud_usart;
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USART_TypeDef *ud_usart;
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/** @brief Pointer to the receive DMA channel registers block.*/
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/** @brief Pointer to the DMA registers block.*/
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DMA_Channel_TypeDef *ud_dmarx;
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stm32_dma_t *ud_dmap;
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/** @brief Receive DMA flags mask*/
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uint32_t ud_dmarmsk;
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/** @brief Pointer to the transmit DMA channel registers block.*/
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DMA_Channel_TypeDef *ud_dmatx;
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/** @brief Transmit DMA flags mask*/
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uint32_t ud_dmatmsk;
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/** @brief DMA priority bit mask.*/
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/** @brief DMA priority bit mask.*/
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uint32_t ud_dmaccr;
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uint32_t ud_dmaccr;
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/** @brief Receive DMA channel.*/
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uint8_t ud_dmarx;
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/** @brief Transmit DMA channel.*/
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uint8_t ud_dmatx;
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/** @brief Default receive buffer while into @p UART_RX_IDLE state.*/
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uint16_t ud_rxbuf;
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} UARTDriver;
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} UARTDriver;
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/*===========================================================================*/
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/*===========================================================================*/
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