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Workaround for different ADC3 type: no ADC3 support. Good job to the decision makers. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15571 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2022-04-03 10:28:39 +00:00
parent 0070aac920
commit 5f825b3aa6
8 changed files with 47 additions and 56 deletions
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5
demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h
View File

@ -225,15 +225,10 @@
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_SAMPLES_SIZE 16
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
/*
* CAN driver system settings.

7
demos/STM32/RT-STM32H735IG-DISCOVERY/cfg/mcuconf.h
View File

@ -224,16 +224,11 @@
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_SAMPLES_SIZE 16
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_USE_ADC12 TRUE
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
/*
* CAN driver system settings.

5
demos/STM32/RT-VFS-FATFS/cfg/stm32h735ig_discovery/mcuconf.h
View File

@ -225,15 +225,10 @@
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_SAMPLES_SIZE 16
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
/*
* CAN driver system settings.

69
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
View File

@ -64,6 +64,19 @@
#endif /* STM32_ADC_SAMPLES_SIZE == 8 */
#endif /* STM32_ADC_DUAL_MODE == FALSE */
/* I guess somewhere there is somebody proud of this, innovation at its
finest...*/
#if STM32_ADC_RENAMED_REGS
#define PCSEL PCSEL_RES0
#define DIFSEL DIFSEL_RES12
#define LTR1 LTR1_TR1
#define HTR1 HTR1_TR2
#define LTR2 LTR2_DIFSEL
#define HTR2 HTR2_CALFACT
#define LTR3 LTR3_RES10
#define HTR3 HTR3_RES11
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -675,24 +688,24 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcc->CCR = (adcp->adcc->CCR &
(ADC_CCR_CKMODE_MASK | ADC_CCR_DAMDF_MASK | ADC_CCR_DUAL_MASK)) | ccr;
adcp->adcm->CFGR2 = grpp->cfgr2;
adcp->adcm->PCSEL = grpp->pcsel;
adcp->adcm->LTR1 = grpp->ltr1;
adcp->adcm->HTR1 = grpp->htr1;
adcp->adcm->CFGR2 = grpp->cfgr2;
adcp->adcm->PCSEL = grpp->pcsel;
adcp->adcm->LTR1 = grpp->ltr1;
adcp->adcm->HTR1 = grpp->htr1;
adcp->adcm->LTR2 = grpp->ltr2;
adcp->adcm->HTR2 = grpp->htr2;
adcp->adcm->LTR3 = grpp->ltr3;
adcp->adcm->HTR3 = grpp->htr3;
adcp->adcm->AWD2CR = grpp->awd2cr;
adcp->adcm->AWD3CR = grpp->awd3cr;
adcp->adcm->SMPR1 = grpp->smpr[0];
adcp->adcm->SMPR2 = grpp->smpr[1];
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
adcp->adcm->SQR2 = grpp->sqr[1];
adcp->adcm->SQR3 = grpp->sqr[2];
adcp->adcm->SQR4 = grpp->sqr[3];
adcp->adcs->CFGR2 = grpp->cfgr2;
adcp->adcs->PCSEL = grpp->pcsel;
adcp->adcm->SMPR1 = grpp->smpr[0];
adcp->adcm->SMPR2 = grpp->smpr[1];
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
adcp->adcm->SQR2 = grpp->sqr[1];
adcp->adcm->SQR3 = grpp->sqr[2];
adcp->adcm->SQR4 = grpp->sqr[3];
adcp->adcs->CFGR2 = grpp->cfgr2;
adcp->adcs->PCSEL = grpp->pcsel;
adcp->adcs->LTR1 = grpp->sltr1;
adcp->adcs->HTR1 = grpp->shtr1;
adcp->adcs->LTR2 = grpp->sltr2;
@ -701,12 +714,12 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcs->HTR3 = grpp->shtr3;
adcp->adcs->AWD2CR = grpp->sawd2cr;
adcp->adcs->AWD3CR = grpp->sawd3cr;
adcp->adcs->SMPR1 = grpp->ssmpr[0];
adcp->adcs->SMPR2 = grpp->ssmpr[1];
adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
adcp->adcs->SQR2 = grpp->ssqr[1];
adcp->adcs->SQR3 = grpp->ssqr[2];
adcp->adcs->SQR4 = grpp->ssqr[3];
adcp->adcs->SMPR1 = grpp->ssmpr[0];
adcp->adcs->SMPR2 = grpp->ssmpr[1];
adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
adcp->adcs->SQR2 = grpp->ssqr[1];
adcp->adcs->SQR3 = grpp->ssqr[2];
adcp->adcs->SQR4 = grpp->ssqr[3];
/* ADC configuration.*/
adcp->adcm->CFGR = cfgr;
@ -718,22 +731,22 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
#if STM32_ADC_DUAL_MODE == FALSE || STM32_ADC_USE_ADC3 == TRUE
/* Configuration for ADC3 and single mode ADC1 */
adcp->adcm->CFGR2 = grpp->cfgr2;
adcp->adcm->PCSEL = grpp->pcsel;
adcp->adcm->LTR1 = grpp->ltr1;
adcp->adcm->HTR1 = grpp->htr1;
adcp->adcm->CFGR2 = grpp->cfgr2;
adcp->adcm->PCSEL = grpp->pcsel;
adcp->adcm->LTR1 = grpp->ltr1;
adcp->adcm->HTR1 = grpp->htr1;
adcp->adcm->LTR2 = grpp->ltr2;
adcp->adcm->HTR2 = grpp->htr2;
adcp->adcm->LTR3 = grpp->ltr3;
adcp->adcm->HTR3 = grpp->htr3;
adcp->adcm->AWD2CR = grpp->awd2cr;
adcp->adcm->AWD3CR = grpp->awd3cr;
adcp->adcm->SMPR1 = grpp->smpr[0];
adcp->adcm->SMPR2 = grpp->smpr[1];
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
adcp->adcm->SQR2 = grpp->sqr[1];
adcp->adcm->SQR3 = grpp->sqr[2];
adcp->adcm->SQR4 = grpp->sqr[3];
adcp->adcm->SMPR1 = grpp->smpr[0];
adcp->adcm->SMPR2 = grpp->smpr[1];
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
adcp->adcm->SQR2 = grpp->sqr[1];
adcp->adcm->SQR3 = grpp->sqr[2];
adcp->adcm->SQR4 = grpp->sqr[3];
/* ADC configuration.*/
adcp->adcm->CFGR = cfgr;

2
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
View File

@ -383,7 +383,7 @@
#endif
#if (STM32_ADC_SAMPLES_SIZE != 32) && STM32_ADC_DUAL_MODE
#error "STM32_ADC_SAMPLES_SIZE = 32 not compatible with STM32_ADC_DUAL_MODE"
#error "STM32_ADC_SAMPLES_SIZE != 32 not compatible with STM32_ADC_DUAL_MODE"
#endif
#if !defined(STM32_ENFORCE_H7_REV_XY)

5
os/hal/ports/STM32/STM32H7xx/stm32_registry.h
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@ -110,6 +110,7 @@
defined(__DOXYGEN__)
/* ADC attributes.*/
#define STM32_ADC_RENAMED_REGS FALSE
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
#define STM32_HAS_ADC3 TRUE
@ -345,9 +346,10 @@
defined(__DOXYGEN__)
/* ADC attributes.*/
#define STM32_ADC_RENAMED_REGS TRUE
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
#define STM32_HAS_ADC3 TRUE
#define STM32_HAS_ADC3 FALSE /* NOT an error, it is a different ADC type.*/
#define STM32_HAS_ADC4 FALSE
#define STM32_HAS_SDADC1 FALSE
@ -578,6 +580,7 @@
defined(__DOXYGEN__)
/* ADC attributes.*/
#define STM32_ADC_RENAMED_REGS FALSE
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
#define STM32_HAS_ADC3 FALSE

5
testhal/STM32/multi/WSPI-MFS/cfg/stm32h735ig_discovery/mcuconf.h
View File

@ -225,15 +225,10 @@
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_SAMPLES_SIZE 16
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
/*
* CAN driver system settings.

5
tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl
View File

@ -236,15 +236,10 @@
#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"}
#define STM32_ADC_SAMPLES_SIZE ${doc.STM32_ADC_SAMPLES_SIZE!"16"}
#define STM32_ADC_USE_ADC12 ${doc.STM32_ADC_USE_ADC12!"TRUE"}
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
#define STM32_ADC_ADC12_DMA_STREAM ${doc.STM32_ADC_ADC12_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_ADC_ADC3_BDMA_STREAM ${doc.STM32_ADC_ADC3_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_ADC_ADC12_DMA_PRIORITY ${doc.STM32_ADC_ADC12_DMA_PRIORITY!"2"}
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"}
#define STM32_ADC_ADC12_CLOCK_MODE ${doc.STM32_ADC_ADC12_CLOCK_MODE!"ADC_CCR_CKMODE_ADCCK"}
#define STM32_ADC_ADC3_CLOCK_MODE ${doc.STM32_ADC_ADC3_CLOCK_MODE!"ADC_CCR_CKMODE_ADCCK"}
/*
* CAN driver system settings.