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[FSMC NAND] Minor changes in testhal application. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7197 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2014-08-26 08:23:57 +00:00
parent e00a505b1c
commit 6220df1090
4 changed files with 690 additions and 728 deletions
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1403
os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
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File diff suppressed because it is too large Load Diff

5
testhal/STM32/STM32F4xx/FSMC_NAND/.project
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@ -24,11 +24,6 @@
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F4_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>
<type>2</type>

2
testhal/STM32/STM32F4xx/FSMC_NAND/Makefile
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@ -102,10 +102,10 @@ CSRC = $(PORTSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(CHIBIOS)/os/various/chprintf.c \
main.c \
dma_storm_adc.c \
dma_storm_spi.c \
dma_storm_uart.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.

8
testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf.h
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@ -41,7 +41,7 @@
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLM_VALUE 12
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
@ -314,3 +314,9 @@
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
/*
* FSMC SRAM driver system settings.
*/
#define STM32_USE_FSMC_SRAM FALSE
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE