mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9480 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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@ -69,11 +69,6 @@
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#define QSPI_CFG_DATA_MODE_ONE_LINE (1U << 24U)
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#define QSPI_CFG_DATA_MODE_ONE_LINE (1U << 24U)
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#define QSPI_CFG_DATA_MODE_TWO_LINES (2U << 24U)
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#define QSPI_CFG_DATA_MODE_TWO_LINES (2U << 24U)
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#define QSPI_CFG_DATA_MODE_FOUR_LINES (3U << 24U)
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#define QSPI_CFG_DATA_MODE_FOUR_LINES (3U << 24U)
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#define QSPI_CFG_F_MODE_MASK (3U << 26U)
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#define QSPI_CFG_F_MODE_INDIRECT_WRITE (0U << 26U)
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#define QSPI_CFG_F_MODE_INDIRECT_READ (1U << 26U)
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#define QSPI_CFG_F_MODE_MEMORY_MAPPED (2U << 26U)
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#define QSPI_CFG_F_MODE_FOUR_LINES (3U << 26U)
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#define QSPI_CFG_SIOO (1U << 28U)
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#define QSPI_CFG_SIOO (1U << 28U)
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#define QSPI_CFG_DDRM (1U << 31U)
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#define QSPI_CFG_DDRM (1U << 31U)
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/** @} */
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/** @} */
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@ -141,6 +136,23 @@ typedef struct {
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* @name Macro Functions
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* @name Macro Functions
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* @{
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* @{
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*/
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*/
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/**
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* @brief Sends a command without data phase.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] cmd pointer to the command descriptor
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*
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* @iclass
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*/
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#define qspiCommandI(qspip, cmd) { \
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osalDbgAssert(((cmd)->cfg & QSPI_CFG_DATA_MODE_MASK) == \
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QSPI_CFG_DATA_MODE_NONE, \
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"data mode specified"); \
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(qspip)->state = QSPI_ACTIVE; \
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qspi_lld_command(qspip, cmd, n, txbuf); \
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}
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/**
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/**
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* @brief Sends data over the QSPI bus.
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* @brief Sends data over the QSPI bus.
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* @details This asynchronous function starts a transmit operation.
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* @details This asynchronous function starts a transmit operation.
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@ -154,6 +166,9 @@ typedef struct {
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* @iclass
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* @iclass
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*/
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*/
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#define qspiStartSendI(qspip, cmd, n, txbuf) { \
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#define qspiStartSendI(qspip, cmd, n, txbuf) { \
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osalDbgAssert(((cmd)->cfg & QSPI_CFG_DATA_MODE_MASK) != \
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QSPI_CFG_DATA_MODE_NONE, \
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"data mode required"); \
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(qspip)->state = QSPI_ACTIVE; \
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(qspip)->state = QSPI_ACTIVE; \
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qspi_lld_send(qspip, cmd, n, txbuf); \
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qspi_lld_send(qspip, cmd, n, txbuf); \
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}
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}
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@ -171,6 +186,9 @@ typedef struct {
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* @iclass
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* @iclass
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*/
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*/
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#define qspiStartReceiveI(qspip, cmd, n, rxbuf) { \
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#define qspiStartReceiveI(qspip, cmd, n, rxbuf) { \
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osalDbgAssert(((cmd)->cfg & QSPI_CFG_DATA_MODE_MASK) != \
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QSPI_CFG_DATA_MODE_NONE, \
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"data mode required"); \
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(qspip)->state = QSPI_ACTIVE; \
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(qspip)->state = QSPI_ACTIVE; \
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qspi_lld_receive(qspip, cmd, n, rxbuf); \
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qspi_lld_receive(qspip, cmd, n, rxbuf); \
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}
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}
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@ -235,11 +253,13 @@ extern "C" {
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void qspiObjectInit(QSPIDriver *qspip);
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void qspiObjectInit(QSPIDriver *qspip);
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void qspiStart(QSPIDriver *qspip, const QSPIConfig *config);
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void qspiStart(QSPIDriver *qspip, const QSPIConfig *config);
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void qspiStop(QSPIDriver *qspip);
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void qspiStop(QSPIDriver *qspip);
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void qspiStartCommand(QSPIDriver *qspip, const qspi_command_t *cmdp);
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void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf);
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size_t n, const uint8_t *txbuf);
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void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, uint8_t *rxbuf);
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size_t n, uint8_t *rxbuf);
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#if QSPI_USE_WAIT == TRUE
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#if QSPI_USE_WAIT == TRUE
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void qspiCommand(QSPIDriver *qspip, const qspi_command_t *cmdp);
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void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf);
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size_t n, const uint8_t *txbuf);
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void qspiReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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void qspiReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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@ -123,21 +123,29 @@ void qspi_lld_init(void) {
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*/
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*/
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void qspi_lld_start(QSPIDriver *qspip) {
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void qspi_lld_start(QSPIDriver *qspip) {
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/* If in stopped state then enables the QUADSPI and DMA clocks.*/
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/* If in stopped state then full initialization.*/
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if (qspip->state == QSPI_STOP) {
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if (qspip->state == QSPI_STOP) {
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#if STM32_QSPI_USE_QUADSPI1
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#if STM32_QSPI_USE_QUADSPI1
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if (&QSPID1 == qspip) {
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if (&QSPID1 == qspip) {
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rccEnableQUADSPI1(FALSE);
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bool b = dmaStreamAllocate(qspip->dma,
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STM32_QSPI_QUADSPI1_IRQ_PRIORITY,
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(stm32_dmaisr_t)qspi_lld_serve_dma_interrupt,
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(void *)qspip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableQUADSPI1(false);
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}
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}
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#endif
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#endif
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/* Common initializations.*/
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dmaStreamSetPeripheral(qspip->dma, &qspip->qspi->DR);
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}
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}
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/* QSPI setup and enable.*/
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/* QSPI setup and enable.*/
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// spip->spi->CR1 = 0;
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qspip->qspi->CR = ((STM32_QSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
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// spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR;
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QUADSPI_CR_TCIE | QUADSPI_CR_TEIE | QUADSPI_CR_DMAEN |
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// spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |
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QUADSPI_CR_EN;
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// SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
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qspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
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// spip->spi->CR1 |= SPI_CR1_SPE;
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QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
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}
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}
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/**
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/**
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@ -153,10 +161,12 @@ void qspi_lld_stop(QSPIDriver *qspip) {
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if (qspip->state == QSPI_READY) {
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if (qspip->state == QSPI_READY) {
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/* QSPI disable.*/
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/* QSPI disable.*/
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// spip->spi->CR1 = 0;
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qspip->qspi->CR = 0U;
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// spip->spi->CR2 = 0;
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/* Releasing the DMA.*/
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dmaStreamRelease(qspip->dma);
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dmaStreamRelease(qspip->dma);
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/* Stopping involved clocks.*/
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#if STM32_QSPI_USE_QUADSPI1
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#if STM32_QSPI_USE_QUADSPI1
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if (&QSPID1 == qspip) {
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if (&QSPID1 == qspip) {
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rccDisableQUADSPI1(FALSE);
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rccDisableQUADSPI1(FALSE);
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@ -166,13 +176,32 @@ void qspi_lld_stop(QSPIDriver *qspip) {
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}
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}
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/**
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/**
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* @brief Sends data over the QSPI bus.
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* @brief Sends a command without data phase.
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* @details This asynchronous function starts a transmit operation.
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* @post At the end of the operation the configured callback is invoked.
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* @post At the end of the operation the configured callback is invoked.
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*
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] cmd pointer to the command descriptor
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of words to send
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*
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* @notapi
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*/
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void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp) {
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qspip->qspi->CCR = cmdp->cfg;
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if ((cmdp->cfg & QSPI_CFG_ALT_MODE_MASK) != QSPI_CFG_ALT_MODE_NONE) {
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qspip->qspi->ABR = cmdp->alt;
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}
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if ((cmdp->cfg & QSPI_CFG_ADDR_MODE_MASK) != QSPI_CFG_ADDR_MODE_NONE) {
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qspip->qspi->AR = cmdp->addr;
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}
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}
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/**
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* @brief Sends a command with data over the QSPI bus.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of bytes to send
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* @param[in] txbuf the pointer to the transmit buffer
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* @param[in] txbuf the pointer to the transmit buffer
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*
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*
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* @notapi
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* @notapi
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@ -184,17 +213,21 @@ void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
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dmaStreamSetTransactionSize(qspip->dma, n);
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dmaStreamSetTransactionSize(qspip->dma, n);
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dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_M2P);
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dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_M2P);
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qspip->qspi->DLR = n - 1;
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qspip->qspi->ABR = cmdp->alt;
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qspip->qspi->CCR = cmdp->cfg;
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qspip->qspi->AR = cmdp->addr;
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dmaStreamEnable(qspip->dma);
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dmaStreamEnable(qspip->dma);
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}
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}
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/**
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/**
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* @brief Receives data from the QSPI bus.
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* @brief Sends a command then receives data over the QSPI bus.
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* @details This asynchronous function starts a receive operation.
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* @post At the end of the operation the configured callback is invoked.
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* @post At the end of the operation the configured callback is invoked.
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*
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] cmd pointer to the command descriptor
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of words to receive
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* @param[in] n number of bytes to send
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* @param[out] rxbuf the pointer to the receive buffer
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* @param[out] rxbuf the pointer to the receive buffer
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*
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*
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* @notapi
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* @notapi
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@ -206,6 +239,11 @@ void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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dmaStreamSetTransactionSize(qspip->dma, n);
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dmaStreamSetTransactionSize(qspip->dma, n);
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dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_P2M);
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dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_P2M);
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qspip->qspi->DLR = n - 1;
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qspip->qspi->ABR = cmdp->alt;
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qspip->qspi->CCR = cmdp->cfg | QUADSPI_CCR_FMODE_0;
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qspip->qspi->AR = cmdp->addr;
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dmaStreamEnable(qspip->dma);
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dmaStreamEnable(qspip->dma);
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}
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}
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@ -48,6 +48,16 @@
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#define STM32_QSPI_USE_QUADSPI1 FALSE
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#define STM32_QSPI_USE_QUADSPI1 FALSE
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#endif
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#endif
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/**
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* @brief QUADSPI1 prescaler setting.
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* @note This is the prescaler divider value 1..256. The maximum frequency
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* varies depending on the STM32 model and operating conditions,
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* find the details in the data sheet.
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*/
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#if !defined(STM32_QSPI_QUADSPI1_PRESCALER_VALUE) || defined(__DOXYGEN__)
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#define STM32_QSPI_QUADSPI1_PRESCALER_VALUE 4
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#endif
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/**
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/**
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* @brief QUADSPI1 interrupt priority level setting.
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* @brief QUADSPI1 interrupt priority level setting.
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*/
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*/
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@ -199,6 +209,7 @@ extern "C" {
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void qspi_lld_init(void);
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void qspi_lld_init(void);
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void qspi_lld_start(QSPIDriver *qspip);
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void qspi_lld_start(QSPIDriver *qspip);
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void qspi_lld_stop(QSPIDriver *qspip);
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void qspi_lld_stop(QSPIDriver *qspip);
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void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp);
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void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
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void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf);
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size_t n, const uint8_t *txbuf);
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void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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@ -211,7 +211,8 @@
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/* QUADSPI attributes.*/
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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#define STM32_HAS_QUADSPI1 TRUE
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#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_QUADSPI1_DMA_CHN 0x03000000
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#define STM32_QUADSPI1_DMA_CHN 0x03000000
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/* RTC attributes.*/
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/* RTC attributes.*/
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@ -123,13 +123,31 @@ void qspiStop(QSPIDriver *qspip) {
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}
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}
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/**
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/**
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* @brief Sends data over the QSPI bus.
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* @brief Sends a command without data phase.
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* @details This asynchronous function starts a transmit operation.
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* @post At the end of the operation the configured callback is invoked.
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* @post At the end of the operation the configured callback is invoked.
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*
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] cmd pointer to the command descriptor
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of words to send or zero if no data phase
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*
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* @api
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*/
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void qspiStartCommand(QSPIDriver *qspip, const qspi_command_t *cmdp) {
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osalDbgCheck((qspip != NULL) && (cmdp != NULL));
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osalSysLock();
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osalDbgAssert(qspip->state == QSPI_READY, "not ready");
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qspiStartCommandI(qspip, cmd);
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osalSysUnlock();
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}
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/**
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* @brief Sends a command with data over the QSPI bus.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of bytes to send
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* @param[in] txbuf the pointer to the transmit buffer
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* @param[in] txbuf the pointer to the transmit buffer
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*
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*
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* @api
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* @api
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@ -138,7 +156,7 @@ void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf) {
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size_t n, const uint8_t *txbuf) {
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osalDbgCheck((qspip != NULL) && (cmdp != NULL));
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osalDbgCheck((qspip != NULL) && (cmdp != NULL));
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osalDbgCheck((n == 0U) || ((n > 0U) && (txbuf != NULL)));
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osalDbgCheck((n > 0U) && (txbuf != NULL));
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osalSysLock();
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osalSysLock();
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osalDbgAssert(qspip->state == QSPI_READY, "not ready");
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osalDbgAssert(qspip->state == QSPI_READY, "not ready");
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@ -147,13 +165,12 @@ void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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}
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}
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/**
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/**
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* @brief Receives data from the QSPI bus.
|
* @brief Sends a command then receives data over the QSPI bus.
|
||||||
* @details This asynchronous function starts a receive operation.
|
|
||||||
* @post At the end of the operation the configured callback is invoked.
|
* @post At the end of the operation the configured callback is invoked.
|
||||||
*
|
*
|
||||||
* @param[in] qspip pointer to the @p QSPIDriver object
|
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||||
* @param[in] cmd pointer to the command descriptor
|
* @param[in] cmd pointer to the command descriptor
|
||||||
* @param[in] n number of words to receive or zero if no data phase
|
* @param[in] n number of bytes to send
|
||||||
* @param[out] rxbuf the pointer to the receive buffer
|
* @param[out] rxbuf the pointer to the receive buffer
|
||||||
*
|
*
|
||||||
* @api
|
* @api
|
||||||
|
@ -162,7 +179,7 @@ void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||||
size_t n, uint8_t *rxbuf) {
|
size_t n, uint8_t *rxbuf) {
|
||||||
|
|
||||||
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||||
osalDbgCheck((n == 0U) || ((n > 0U) && (rxbuf != NULL)));
|
osalDbgCheck((n > 0U) && (rxbuf != NULL));
|
||||||
|
|
||||||
osalSysLock();
|
osalSysLock();
|
||||||
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||||
|
@ -172,8 +189,7 @@ void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||||
|
|
||||||
#if (QSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
|
#if (QSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief Sends data over the QSPI bus.
|
* @brief Sends a command without data phase.
|
||||||
* @details This synchronous function performs a transmit operation.
|
|
||||||
* @pre In order to use this function the option @p QSPI_USE_WAIT must be
|
* @pre In order to use this function the option @p QSPI_USE_WAIT must be
|
||||||
* enabled.
|
* enabled.
|
||||||
* @pre In order to use this function the driver must have been configured
|
* @pre In order to use this function the driver must have been configured
|
||||||
|
@ -181,7 +197,31 @@ void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||||
*
|
*
|
||||||
* @param[in] qspip pointer to the @p QSPIDriver object
|
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||||
* @param[in] cmd pointer to the command descriptor
|
* @param[in] cmd pointer to the command descriptor
|
||||||
* @param[in] n number of words to send or zero if no data phase
|
*
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
void qspiCommand(QSPIDriver *qspip, const qspi_command_t *cmdp) {
|
||||||
|
|
||||||
|
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||||
|
|
||||||
|
osalSysLock();
|
||||||
|
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||||
|
osalDbgAssert(qspip->config->end_cb == NULL, "has callback");
|
||||||
|
qspiStartCommandI(qspip, cmd, n, txbuf);
|
||||||
|
(void) osalThreadSuspendS(&qspip->thread);
|
||||||
|
osalSysUnlock();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sends a command with data over the QSPI bus.
|
||||||
|
* @pre In order to use this function the option @p QSPI_USE_WAIT must be
|
||||||
|
* enabled.
|
||||||
|
* @pre In order to use this function the driver must have been configured
|
||||||
|
* without callbacks (@p end_cb = @p NULL).
|
||||||
|
*
|
||||||
|
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||||
|
* @param[in] cmd pointer to the command descriptor
|
||||||
|
* @param[in] n number of bytes to send
|
||||||
* @param[in] txbuf the pointer to the transmit buffer
|
* @param[in] txbuf the pointer to the transmit buffer
|
||||||
*
|
*
|
||||||
* @api
|
* @api
|
||||||
|
@ -190,7 +230,7 @@ void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||||
size_t n, const uint8_t *txbuf) {
|
size_t n, const uint8_t *txbuf) {
|
||||||
|
|
||||||
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||||
osalDbgCheck((n == 0U) || ((n > 0U) && (txbuf != NULL)));
|
osalDbgCheck((n > 0U) && (txbuf != NULL));
|
||||||
|
|
||||||
osalSysLock();
|
osalSysLock();
|
||||||
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||||
|
@ -201,8 +241,7 @@ void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Receives data from the QSPI bus.
|
* @brief Sends a command then receives data over the QSPI bus.
|
||||||
* @details This synchronous function performs a receive operation.
|
|
||||||
* @pre In order to use this function the option @p QSPI_USE_WAIT must be
|
* @pre In order to use this function the option @p QSPI_USE_WAIT must be
|
||||||
* enabled.
|
* enabled.
|
||||||
* @pre In order to use this function the driver must have been configured
|
* @pre In order to use this function the driver must have been configured
|
||||||
|
@ -210,7 +249,7 @@ void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||||
*
|
*
|
||||||
* @param[in] qspip pointer to the @p QSPIDriver object
|
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||||
* @param[in] cmd pointer to the command descriptor
|
* @param[in] cmd pointer to the command descriptor
|
||||||
* @param[in] n number of words to receive or zero if no data phase
|
* @param[in] n number of bytes to send
|
||||||
* @param[out] rxbuf the pointer to the receive buffer
|
* @param[out] rxbuf the pointer to the receive buffer
|
||||||
*
|
*
|
||||||
* @api
|
* @api
|
||||||
|
@ -219,7 +258,7 @@ void qspiReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||||
size_t n, uint8_t *rxbuf) {
|
size_t n, uint8_t *rxbuf) {
|
||||||
|
|
||||||
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||||
osalDbgCheck((n == 0U) || ((n > 0U) && (rxbuf != NULL)));
|
osalDbgCheck((n > 0U) && (rxbuf != NULL));
|
||||||
|
|
||||||
osalSysLock();
|
osalSysLock();
|
||||||
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||||
|
|
Loading…
Reference in New Issue