From 64c0f991ec737f08e82dfe9d74dd7ce560d2aa93 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 12 Feb 2013 13:04:47 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5158
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC56ELxx/hal_lld.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c
index e8e3c8a17..5e82db019 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.c
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.c
@@ -176,7 +176,10 @@ void spc_early_init(void) {
                       (SPC5_FMPLL1_NDIV_VALUE << 16);
   CGM.FMPLL[1].MR.R = 0;                        /* TODO: Add a setting.     */
 
-  /* Run modes initialization.*/
+  /* Run modes initialization, note writes to the MC registers are verified
+     by a protection mechanism, the operation success is verified at the
+     end of the sequence.*/
+  ME.IS.R           = 8;                        /* Resetting I_ICONF status.*/
   ME.MER.R          = SPC5_ME_ME_BITS;          /* Enabled run modes.       */
   ME.SAFE.R         = SPC5_ME_SAFE_MC_BITS;     /* SAFE run mode.           */
   ME.DRUN.R         = SPC5_ME_DRUN_MC_BITS;     /* DRUN run mode.           */
@@ -186,6 +189,10 @@ void spc_early_init(void) {
   ME.RUN[3].R       = SPC5_ME_RUN3_MC_BITS;     /* RUN0 run mode.           */
   ME.HALT0.R        = SPC5_ME_HALT0_MC_BITS;    /* HALT0 run mode.          */
   ME.STOP0.R        = SPC5_ME_STOP0_MC_BITS;    /* STOP0 run mode.          */
+  if (ME.IS.B.I_ICONF) {
+    /* Configuration rejected.*/
+    SPC5_CLOCK_FAILURE_HOOK();
+  }
 
   /* Peripherals run and low power modes initialization.*/
   ME.RUNPC[0].R     = SPC5_ME_RUN_PC0_BITS;