mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@348 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -31,7 +31,7 @@
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/*
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/*
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* Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
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* Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
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*/
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*/
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//#define SYSCLK_48
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#define SYSCLK_48
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/*
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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@ -132,18 +132,19 @@ void PendSVVector(void) {
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chSysUnlock();
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chSysUnlock();
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asm volatile ("pop {pc}");
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asm volatile ("pop {pc}");
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}
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}
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asm volatile ("pop {lr}");
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asm volatile ("pop {lr} \n\t" \
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register uint32_t tmp asm ("r3") = BASEPRI_USER;
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"movs r3, #0 \n\t" \
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"mrs %0, PSP" : "=r" (sp_thd) : );
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#ifdef CH_CURRP_REGISTER_CACHE
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#ifdef CH_CURRP_REGISTER_CACHE
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asm volatile ("stmdb %0!, {r3-r6,r8-r11, lr}" :
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asm volatile ("mrs %0, PSP \n\t" \
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"stmdb %0!, {r3-r6,r8-r11, lr}" :
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"=r" (sp_thd) :
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"=r" (sp_thd) :
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"r" (sp_thd));
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"r" (sp_thd), "r" (tmp));
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#else
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#else
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asm volatile ("stmdb %0!, {r3-r11,lr}" :
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asm volatile ("mrs %0, PSP \n\t" \
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"stmdb %0!, {r3-r11,lr}" :
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"=r" (sp_thd) :
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"=r" (sp_thd) :
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"r" (sp_thd));
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"r" (sp_thd), "r" (tmp));
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#endif
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#endif
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(otp = currp)->p_ctx.r13 = sp_thd;
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(otp = currp)->p_ctx.r13 = sp_thd;
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@ -24,6 +24,12 @@
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typedef void *regarm;
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typedef void *regarm;
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/*
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* Port-related configuration parameters.
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*/
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#define BASEPRI_USER 0 /* User level BASEPRI, 0 = disabled. */
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#define BASEPRI_KERNEL 0x10 /* BASEPRI level within kernel lock. */
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/*
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/*
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* Interrupt saved context, empty in this architecture.
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* Interrupt saved context, empty in this architecture.
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*/
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*/
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@ -83,13 +89,11 @@ typedef struct {
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}
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}
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#define chSysLock() { \
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#define chSysLock() { \
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register uint32_t tmp asm ("r3"); \
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register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
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asm volatile ("movs %0, #0x10" : "=r" (tmp): ); \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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}
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#define chSysUnlock() { \
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#define chSysUnlock() { \
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register uint32_t tmp asm ("r3"); \
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register uint32_t tmp asm ("r3") = BASEPRI_USER; \
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asm volatile ("movs %0, #0" : "=r" (tmp): ); \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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}
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#define chSysSwitchI(otp, ntp) { \
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#define chSysSwitchI(otp, ntp) { \
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@ -79,6 +79,7 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
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problems when the CH_USE_MESSAGES_PRIORITY was enabled, this option is
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problems when the CH_USE_MESSAGES_PRIORITY was enabled, this option is
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disabled by default in ChibiOS/RT so it should not affect any user.
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disabled by default in ChibiOS/RT so it should not affect any user.
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- Merged the documentation fixes submitted by Leon Woestenberg (thank you).
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- Merged the documentation fixes submitted by Leon Woestenberg (thank you).
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- Made the default BASEPRI levels (CM3 port) configurable into chcore.h.
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*** 0.6.7 ***
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*** 0.6.7 ***
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- NEW: New chThdCreateFast() API, it is a simplified form of chThdCreate()
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- NEW: New chThdCreateFast() API, it is a simplified form of chThdCreate()
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