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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15867 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2022-12-08 17:02:40 +00:00
parent ffc86d58d8
commit 6917eedc3f
5 changed files with 8 additions and 10 deletions
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4
testhal/STM32/STM32WLxx/I2S/cfg/mcuconf.h
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@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE #define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV #define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE #define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE #define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M #define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/ */
#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK #define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/STM32WLxx/SPI/cfg/mcuconf.h
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@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE #define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV #define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE #define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE #define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M #define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/ */
#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK #define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/STM32WLxx/SYSTICKv2/cfg/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE #define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV #define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE #define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE #define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M #define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/ */
#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK #define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/STM32WLxx/WDG/cfg/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
#define STM32_LSIPRE STM32_LSIPRE_NODIV #define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE #define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE #define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE #define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M #define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/ */
#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK #define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

2
testhal/STM32/multi/ADC/cfg/stm32wl55jc_nucleo64/portab.c
View File

@ -66,7 +66,6 @@ const ADCConversionGroup portab_adcgrpcfg1 = {
.end_cb = NULL, .end_cb = NULL,
.error_cb = adcerrorcallback, .error_cb = adcerrorcallback,
.cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, .cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT,
.cfgr2 = 0,
.tr1 = ADC_TR_DISABLED, .tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED, .tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED, .tr3 = ADC_TR_DISABLED,
@ -90,7 +89,6 @@ const ADCConversionGroup portab_adcgrpcfg2 = {
ADC_CFGR1_RES_12BIT | ADC_CFGR1_RES_12BIT |
ADC_CFGR1_EXTEN_RISING | ADC_CFGR1_EXTEN_RISING |
ADC_CFGR1_EXTSEL_SRC(0), ADC_CFGR1_EXTSEL_SRC(0),
.cfgr2 = 0,
.tr1 = ADC_TR_DISABLED, .tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED, .tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED, .tr3 = ADC_TR_DISABLED,