mirror of https://github.com/rusefi/ChibiOS.git
Added more clock points.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11195 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
dc94818e88
commit
6a7ef4a439
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@ -428,12 +428,12 @@
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#define STM32_SAI1SEL_I2S_CKIN RCC_D2CCIP1R_SAI1SEL_VALUE(3U)
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#define STM32_SAI1SEL_PER_CK RCC_D2CCIP1R_SAI1SEL_VALUE(4U)
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#define STM32_LPTIM1_PCLK1 RCC_D2CCIP2R_LPTIM1SEL_VALUE(0U)
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#define STM32_LPTIM1_PLL2_P_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(1U)
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#define STM32_LPTIM1_PLL3_R_CJ RCC_D2CCIP2R_LPTIM1SEL_VALUE(2U)
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#define STM32_LPTIM1_LSE_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(3U)
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#define STM32_LPTIM1_LSI_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(4U)
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#define STM32_LPTIM1_PER_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(5U)
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#define STM32_LPTIM1SEL_PCLK1 RCC_D2CCIP2R_LPTIM1SEL_VALUE(0U)
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#define STM32_LPTIM1SEL_PLL2_P_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(1U)
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#define STM32_LPTIM1SEL_PLL3_R_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(2U)
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#define STM32_LPTIM1SEL_LSE_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(3U)
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#define STM32_LPTIM1SEL_LSI_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(4U)
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#define STM32_LPTIM1SEL_PER_CK RCC_D2CCIP2R_LPTIM1SEL_VALUE(5U)
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#define STM32_CECSEL_LSE_CK RCC_D2CCIP2R_CECSEL_VALUE(0U)
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#define STM32_CECSEL_LSI_CK RCC_D2CCIP2R_CECSEL_VALUE(1U)
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@ -2251,10 +2251,10 @@
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#define STM32_FLASHBITS 0x00000007
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#endif
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#if (STM32_D2PPRE1 == STM32_D2PPRE1_DIV1) || defined(__DOXYGEN__)
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/**
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* @brief Clock of timers connected to APB1
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*/
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#if (STM32_D2PPRE1 == STM32_D2PPRE1_DIV1) || defined(__DOXYGEN__)
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#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
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#else
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#if (STM32_TIMPRE_ENABLE == FALSE) || (STM32_D2PPRE1 == STM32_D2PPRE1_DIV2)
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@ -2264,10 +2264,10 @@
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#endif
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#endif
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#if (STM32_D2PPRE2 == STM32_D2PPRE2_DIV1) || defined(__DOXYGEN__)
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/**
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* @brief Clock of timers connected to APB2.
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*/
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#if (STM32_D2PPRE2 == STM32_D2PPRE2_DIV1) || defined(__DOXYGEN__)
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#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
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#else
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#if (STM32_TIMPRE_ENABLE == FALSE) || (STM32_D2PPRE2 == STM32_D2PPRE2_DIV2)
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@ -2277,6 +2277,86 @@
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#endif
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#endif
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#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
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/**
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* @brief LPTIM1 clock.
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*/
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#define STM32_LPTIM1CLK STM32_PCLK1
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#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_PLL2_P_CK
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#define STM32_LPTIM1CLK STM32_PLL2_P_CK
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#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_PLL3_R_CK
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#define STM32_LPTIM1CLK STM32_PLL3_R_CK
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#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE_CK
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#define STM32_LPTIM1CLK STM32_LSECLK
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#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI_CK
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#define STM32_LPTIM1CLK STM32_LSICLK
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#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_PER_CK
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#define STM32_LPTIM1CLK STM32_PER_CK
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#else
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#error "invalid source selected for STM32_LPTIM1SEL clock"
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#endif
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#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK4) || defined(__DOXYGEN__)
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/**
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* @brief LPTIM2 clock.
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*/
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#define STM32_LPTIM2CLK STM32_PCLK4
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#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_PLL2_P_CK
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#define STM32_LPTIM2CLK STM32_PLL2_P_CK
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#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_PLL3_P_CK
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#define STM32_LPTIM2CLK STM32_PLL3_P_CK
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#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE_CK
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#define STM32_LPTIM2CLK STM32_LSECLK
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#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI_CK
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#define STM32_LPTIM2CLK STM32_LSICLK
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#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_PER_CK
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#define STM32_LPTIM2CLK STM32_PER_CK
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#else
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#error "invalid source selected for STM32_LPTIM2SEL clock"
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#endif
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#if (STM32_LPTIM345SEL == STM32_LPTIM345SEL_PCLK4) || defined(__DOXYGEN__)
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/**
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* @brief LPTIM3 clock.
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*/
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#define STM32_LPTIM3CLK STM32_PCLK4
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/**
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* @brief LPTIM4 clock.
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*/
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#define STM32_LPTIM4CLK STM32_PCLK4
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/**
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* @brief LPTIM5 clock.
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*/
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#define STM32_LPTIM5CLK STM32_PCLK4
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#elif STM32_LPTIM345SEL == STM32_LPTIM345SEL_PLL2_P_CK
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#define STM32_LPTIM3CLK STM32_PLL2_P_CK
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#define STM32_LPTIM4CLK STM32_PLL2_P_CK
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#define STM32_LPTIM5CLK STM32_PLL2_P_CK
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#elif STM32_LPTIM345SEL == STM32_LPTIM345SEL_PLL3_P_CK
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#define STM32_LPTIM3CLK STM32_PLL3_P_CK
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#define STM32_LPTIM4CLK STM32_PLL3_P_CK
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#define STM32_LPTIM5CLK STM32_PLL3_P_CK
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#elif STM32_LPTIM345SEL == STM32_LPTIM345SEL_LSE_CK
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#define STM32_LPTIM3CLK STM32_LSECLK
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#define STM32_LPTIM4CLK STM32_LSECLK
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#define STM32_LPTIM5CLK STM32_LSECLK
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#elif STM32_LPTIM345SEL == STM32_LPTIM345SEL_LSI_CK
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#define STM32_LPTIM3CLK STM32_LSICLK
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#define STM32_LPTIM4CLK STM32_LSICLK
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#define STM32_LPTIM5CLK STM32_LSICLK
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#elif STM32_LPTIM345SEL == STM32_LPTIM345SEL_PER_CK
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#define STM32_LPTIM3CLK STM32_PER_CK
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#define STM32_LPTIM4CLK STM32_PER_CK
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#define STM32_LPTIM5CLK STM32_PER_CK
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#else
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#error "invalid source selected for STM32_LPTIM345SEL clock"
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#endif
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#if (STM32_USART16SEL == STM32_USART16SEL_PCLK2) || defined(__DOXYGEN__)
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/**
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* @brief USART1 clock.
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@ -2287,6 +2367,7 @@
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* @brief USART6 clock.
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*/
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#define STM32_USART6CLK STM32_PCLK2
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#elif STM32_USART1SEL == STM32_USART16SEL_PLL2_Q_CK
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#define STM32_USART1CLK STM32_PLL2_Q_CK
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#define STM32_USART6CLK STM32_PLL2_Q_CK
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@ -2336,6 +2417,7 @@
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* @brief USART8 clock.
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*/
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#define STM32_USART8CLK STM32_PCLK2
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#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL2_Q_CK
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#define STM32_USART2CLK STM32_PLL2_Q_CK
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#define STM32_USART3CLK STM32_PLL2_Q_CK
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@ -2375,6 +2457,161 @@
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#error "invalid source selected for STM32_USART234578SEL clock"
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#endif
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#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK4) || defined(__DOXYGEN__)
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/**
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* @brief LPUART1 clock.
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*/
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#define STM32_LPUART1CLK STM32_PCLK1
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#elif STM32_LPUART1SEL == STM32_LPUART1SEL_PLL2_Q_CK
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#define STM32_LPUART1CLK STM32_PLL2_Q_CK
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#elif STM32_LPUART1SEL == STM32_LPUART1SEL_PLL3_Q_CK
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#define STM32_LPUART1CLK STM32_PLL3_Q_CK
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#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI_KER_CK
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#define STM32_LPUART1CLK STM32_HSICLK
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#elif STM32_LPUART1SEL == STM32_LPUART1SEL_CSI_KER_CK
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#define STM32_LPUART1CLK STM32_CSICLK
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#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE_CK
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#define STM32_LPUART1CLK STM32_LSECLK
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#else
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#error "invalid source selected for STM32_LPUART1SEL clock"
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#endif
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#if (STM32_SPI123SEL == STM32_SPI123SEL_PLL1_Q_CK) || defined(__DOXYGEN__)
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/**
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* @brief SPI1 clock.
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*/
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#define STM32_SPI1CLK STM32_PLL1_Q_CK
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/**
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* @brief SPI2 clock.
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*/
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#define STM32_SPI2CLK STM32_PLL1_Q_CK
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/**
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* @brief SPI3 clock.
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*/
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#define STM32_SPI3CLK STM32_PLL1_Q_CK
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#elif STM32_SPI123SEL == STM32_SPI123SEL_PLL2_P_CK
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#define STM32_SPI1CLK STM32_PLL2_P_CK
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#define STM32_SPI2CLK STM32_PLL2_P_CK
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#define STM32_SPI3CLK STM32_PLL2_P_CK
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#elif STM32_SPI123SEL == STM32_SPI123SEL_PLL3_P_CK
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#define STM32_SPI1CLK STM32_PLL3_P_CK
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#define STM32_SPI2CLK STM32_PLL3_P_CK
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#define STM32_SPI3CLK STM32_PLL3_P_CK
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#elif STM32_SPI123SEL == STM32_SPI123SEL_I2S_CKIN
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#define STM32_SPI1CLK 0
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#define STM32_SPI2CLK 0
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#define STM32_SPI3CLK 0
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#elif STM32_SPI123SEL == STM32_SPI123SEL_PLL2_P_CK
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#define STM32_SPI1CLK STM32_PER_CK
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#define STM32_SPI2CLK STM32_PER_CK
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#define STM32_SPI3CLK STM32_PER_CK
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#else
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#error "invalid source selected for STM32_SPI123SEL clock"
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#endif
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#if (STM32_SPI45SEL == STM32_SPI45SEL_PCLK2) || defined(__DOXYGEN__)
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/**
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* @brief SPI4 clock.
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*/
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#define STM32_SPI4CLK STM32_PCLK2
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/**
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* @brief SPI5 clock.
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*/
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#define STM32_SPI5CLK STM32_PCLK2
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#elif STM32_SPI45SEL == STM32_SPI45SEL_PLL2_Q_CK
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#define STM32_SPI4CLK STM32_PLL2_Q_CK
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#define STM32_SPI5CLK STM32_PLL2_Q_CK
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#elif STM32_SPI45SEL == STM32_SPI45SEL_PLL3_Q_CK
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#define STM32_SPI4CLK STM32_PLL3_Q_CK
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#define STM32_SPI5CLK STM32_PLL3_Q_CK
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#elif STM32_SPI45SEL == STM32_SPI45SEL_HSI_KER_CK
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#define STM32_SPI4CLK STM32_HSICLK
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#define STM32_SPI5CLK STM32_HSICLK
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#elif STM32_SPI45SEL == STM32_SPI45SEL_CSI_KER_CK
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#define STM32_SPI4CLK STM32_CSICLK
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#define STM32_SPI5CLK STM32_CSICLK
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#elif STM32_SPI45SEL == STM32_SPI45SEL_HSE_CK
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#define STM32_SPI4CLK STM32_HSECLK
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#define STM32_SPI5CLK STM32_HSECLK
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#else
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#error "invalid source selected for STM32_SPI45SEL clock"
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#endif
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#if (STM32_SPI6SEL == STM32_SPI6SEL_PCLK4) || defined(__DOXYGEN__)
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/**
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* @brief SPI6 clock.
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*/
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#define STM32_SPI6CLK STM32_PCLK4
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#elif STM32_SPI6SEL == STM32_SPI6SEL_PLL2_P_CK
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#define STM32_SPI6CLK STM32_PLL2_P_CK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_PLL3_Q_CK
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#define STM32_SPI6CLK STM32_PLL3_Q_CK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_HSI_KER_CK
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#define STM32_SPI6CLK STM32_HSICLK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_CSI_KER_CK
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#define STM32_SPI6CLK STM32_CSICLK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_HSE_CK
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#define STM32_SPI6CLK STM32_HSECLK
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#else
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#error "invalid source selected for STM32_SPI6SEL clock"
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#endif
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#if (STM32_I2C123SEL == STM32_I2C123SEL_PCLK1) || defined(__DOXYGEN__)
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/**
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* @brief I2C1 clock.
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*/
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#define STM32_I2C1CLK STM32_PCLK1
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/**
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* @brief I2C2 clock.
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*/
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#define STM32_I2C2CLK STM32_PCLK1
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/**
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* @brief I2C2 clock.
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*/
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#define STM32_I2C2CLK STM32_PCLK1
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#elif STM32_I2C123SEL == STM32_I2C123SEL_PLL3_R_CK
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#define STM32_I2C1CLK STM32_PLL3_R_CK
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#define STM32_I2C2CLK STM32_PLL3_R_CK
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#define STM32_I2C2CLK STM32_PLL3_R_CK
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#elif STM32_I2C123SEL == STM32_I2C123SEL_HSI_KER_CK
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#define STM32_I2C1CLK STM32_HSICLK
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#define STM32_I2C2CLK STM32_HSICLK
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#define STM32_I2C2CLK STM32_HSICLK
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#elif STM32_I2C123SEL == STM32_I2C123SEL_CSI_KER_CK
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#define STM32_I2C1CLK STM32_CSICLK
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#define STM32_I2C2CLK STM32_CSICLK
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#define STM32_I2C2CLK STM32_CSICLK
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#else
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#error "invalid source selected for STM32_I2C123SEL clock"
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#endif
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#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK4) || defined(__DOXYGEN__)
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/**
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* @brief I2C1 clock.
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*/
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#define STM32_I2C4CLK STM32_PCLK4
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#elif STM32_I2C4SEL == STM32_I2C4SEL_PLL3_R_CK
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#define STM32_I2C4CLK STM32_I2C123SEL_PLL3_R_CK
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#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI_KER_CK
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#define STM32_I2C4CLK STM32_HSICLK
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#elif STM32_I2C4SEL == STM32_I2C4SEL_CSI_KER_CK
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#define STM32_I2C4CLK STM32_CSICLK
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#else
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#error "invalid source selected for STM32_I2C4SEL clock"
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#endif
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@ -2398,73 +2635,6 @@
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#if 0
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/**
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* @brief I2C1 frequency.
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*/
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#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_I2C1CLK STM32_PCLK1
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#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
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#define STM32_I2C1CLK STM32_SYSCLK
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#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI
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#define STM32_I2C1CLK STM32_HSICLK
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#else
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#error "invalid source selected for I2C1 clock"
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#endif
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/**
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* @brief I2C2 frequency.
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*/
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#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_I2C2CLK STM32_PCLK1
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#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
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#define STM32_I2C2CLK STM32_SYSCLK
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#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI
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#define STM32_I2C2CLK STM32_HSICLK
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#else
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#error "invalid source selected for I2C2 clock"
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#endif
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/**
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* @brief I2C3 frequency.
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*/
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#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_I2C3CLK STM32_PCLK1
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#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
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#define STM32_I2C3CLK STM32_SYSCLK
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#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI
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#define STM32_I2C3CLK STM32_HSICLK
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#else
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#error "invalid source selected for I2C3 clock"
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#endif
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/**
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* @brief I2C4 frequency.
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*/
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#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_I2C4CLK STM32_PCLK1
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#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
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#define STM32_I2C4CLK STM32_SYSCLK
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#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI
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#define STM32_I2C4CLK STM32_HSICLK
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#else
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#error "invalid source selected for I2C4 clock"
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#endif
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/**
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* @brief LPTIM1 frequency.
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*/
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#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
|
||||
#define STM32_LPTIM1CLK STM32_PCLK1
|
||||
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
|
||||
#define STM32_LPTIM1CLK STM32_LSICLK
|
||||
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI
|
||||
#define STM32_LPTIM1CLK STM32_HSICLK
|
||||
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
|
||||
#define STM32_LPTIM1CLK STM32_LSECLK
|
||||
#else
|
||||
#error "invalid source selected for LPTIM1 clock"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief 48MHz frequency.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue