mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3462 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
a8feb8613b
commit
6d159cc390
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@ -55,509 +55,26 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/**
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* @brief Platform name.
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*/
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#if defined(__DOXYGEN__)
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/**
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* @name Platform identification
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* @{
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*/
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#define PLATFORM_NAME "STM32"
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/** @} */
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#elif defined(STM32F10X_LD_VL)
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/*
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* Capability flags for Value Line Low Density devices.
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*/
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#define PLATFORM_NAME "STM32 Value Line Low Density"
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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defined(STM32F10X_HD_VL) || defined(__DOXYGEN__)
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#include "hal_lld_f100.h"
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_DAC TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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#define STM32_HAS_ETH FALSE
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#define STM32_EXTI_NUM_CHANNELS 19
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 FALSE
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_SDIO FALSE
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#define STM32_HAS_SPI1 TRUE
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#define STM32_HAS_SPI2 FALSE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 TRUE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 TRUE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_HAS_TIM17 TRUE
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#elif defined(STM32F10X_MD_VL)
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/*
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* Capability flags for Value Line Medium Density devices.
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*/
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#define PLATFORM_NAME "STM32 Value Line Medium Density"
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#include "hal_lld_f100.h"
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_DAC TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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#define STM32_HAS_ETH FALSE
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#define STM32_EXTI_NUM_CHANNELS 19
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_SDIO FALSE
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#define STM32_HAS_SPI1 TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 TRUE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 TRUE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_HAS_TIM17 TRUE
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#elif defined(STM32F10X_LD)
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/*
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* Capability flags for Performance Line Low Density devices.
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*/
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#define PLATFORM_NAME "STM32 Performance Line Low Density"
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#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
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defined(STM32F10X_HD) || defined(STM32F10X_XL) || \
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defined(__DOXYGEN__)
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#include "hal_lld_f103.h"
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_DAC FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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#define STM32_HAS_ETH FALSE
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#define STM32_EXTI_NUM_CHANNELS 19
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 FALSE
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_SDIO FALSE
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#define STM32_HAS_SPI1 TRUE
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#define STM32_HAS_SPI2 FALSE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#elif defined(STM32F10X_MD)
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/*
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* Capability flags for Performance Line Medium Density devices.
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*/
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#define PLATFORM_NAME "STM32 Performance Line Medium Density"
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#include "hal_lld_f103.h"
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_DAC FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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#define STM32_HAS_ETH FALSE
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#define STM32_EXTI_NUM_CHANNELS 19
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_SDIO FALSE
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#define STM32_HAS_SPI1 TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USB TRUE
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#define STM32_HAS_OTG1 FALSE
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#elif defined(STM32F10X_HD)
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/*
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* Capability flags for Performance Line High Density devices.
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*/
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#define PLATFORM_NAME "STM32 Performance Line High Density"
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#include "hal_lld_f103.h"
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 TRUE
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_DAC TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 TRUE
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#define STM32_HAS_ETH FALSE
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#define STM32_EXTI_NUM_CHANNELS 19
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_SDIO TRUE
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#define STM32_HAS_SPI1 TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 TRUE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 TRUE
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#define STM32_HAS_TIM8 TRUE
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#define STM32_HAS_TIM9 TRUE
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#define STM32_HAS_TIM10 TRUE
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#define STM32_HAS_TIM11 TRUE
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#define STM32_HAS_TIM12 TRUE
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#define STM32_HAS_TIM13 TRUE
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#define STM32_HAS_TIM14 TRUE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USB TRUE
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#define STM32_HAS_OTG1 FALSE
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#elif defined(STM32F10X_XL)
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/*
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* Capability flags for Performance Line eXtra Density devices.
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*/
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#define PLATFORM_NAME "STM32 Performance Line eXtra Density"
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#include "hal_lld_f103.h"
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 TRUE
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_DAC TRUE
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#define STM32_HAS_DMA1 TRUE
|
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#define STM32_HAS_DMA2 TRUE
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#define STM32_HAS_ETH FALSE
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#define STM32_EXTI_NUM_CHANNELS 19
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_SDIO TRUE
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#define STM32_HAS_SPI1 TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 TRUE
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#define STM32_HAS_TIM6 TRUE
|
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#define STM32_HAS_TIM7 TRUE
|
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#define STM32_HAS_TIM8 TRUE
|
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#define STM32_HAS_TIM9 FALSE
|
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 FALSE
|
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
|
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#define STM32_HAS_USART3 TRUE
|
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USB TRUE
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||||
#define STM32_HAS_OTG1 FALSE
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||||
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#elif defined(STM32F10X_CL)
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||||
/*
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||||
* Capability flags for Connectivity Line devices.
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||||
*/
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||||
#define PLATFORM_NAME "STM32 Connectivity Line"
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#elif defined(STM32F10X_CL) || defined(__DOXYGEN__)
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#include "hal_lld_f105_f107.h"
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
|
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#define STM32_HAS_ADC3 FALSE
|
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||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 TRUE
|
||||
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||||
#define STM32_HAS_DAC TRUE
|
||||
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#define STM32_HAS_DMA1 TRUE
|
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#define STM32_HAS_DMA2 TRUE
|
||||
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#define STM32_HAS_ETH TRUE
|
||||
|
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#define STM32_EXTI_NUM_CHANNELS 20
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||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
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||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
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||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 TRUE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 TRUE
|
||||
|
||||
#else
|
||||
#error "unspecified, unsupported or invalid STM32 platform"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -40,10 +40,35 @@
|
|||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#if defined(__DOXYGEN__)
|
||||
#define PLATFORM_NAME "STM32 Value Line"
|
||||
|
||||
#elif defined(STM32F10X_LD_VL)
|
||||
#define PLATFORM_NAME "STM32 Value Line Low Density"
|
||||
|
||||
#elif defined(STM32F10X_MD_VL)
|
||||
#define PLATFORM_NAME "STM32 Value Line Medium Density"
|
||||
#else
|
||||
#error "unsupported STM32 Value Line member"
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
|
||||
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CFGR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
|
||||
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
|
||||
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
|
||||
|
|
@ -92,11 +117,168 @@
|
|||
#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
|
||||
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as
|
||||
RTC clock. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F100 LD capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
#define STM32_EXTI_NUM_CHANNELS 19
|
||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 FALSE
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_LD_VL) */
|
||||
|
||||
#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F100 MD capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
#define STM32_EXTI_NUM_CHANNELS 19
|
||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_MD_VL) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform specific friendly IRQ names. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name IRQ VECTOR names
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
|
||||
#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
|
||||
detect. */
|
||||
|
|
@ -149,6 +331,7 @@
|
|||
#define TIM12_IRQHandler VectorEC /**< TIM12. */
|
||||
#define TIM13_IRQHandler VectorF0 /**< TIM13. */
|
||||
#define TIM14_IRQHandler VectorF4 /**< TIM14. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
|
|
|
|||
|
|
@ -40,10 +40,42 @@
|
|||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#if defined(__DOXYGEN__)
|
||||
#define PLATFORM_NAME "STM32 Performance Line"
|
||||
|
||||
#elif defined(STM32F10X_LD)
|
||||
#define PLATFORM_NAME "STM32 Performance Line Low Density"
|
||||
|
||||
#elif defined(STM32F10X_MD)
|
||||
#define PLATFORM_NAME "STM32 Performance Line Medium Density"
|
||||
|
||||
#elif defined(STM32F10X_HD)
|
||||
#define PLATFORM_NAME "STM32 Performance Line High Density"
|
||||
|
||||
#elif defined(STM32F10X_XL)
|
||||
#define PLATFORM_NAME "STM32 Performance Line eXtra Density"
|
||||
|
||||
#else
|
||||
#error "unsupported STM32 Performance Line member"
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
|
||||
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CFGR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
|
||||
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
|
||||
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
|
||||
|
|
@ -95,11 +127,316 @@
|
|||
#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
|
||||
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as
|
||||
RTC clock. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32F10X_LD) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F103 LD capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
#define STM32_HAS_DAC FALSE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
#define STM32_EXTI_NUM_CHANNELS 19
|
||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE FALSE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 FALSE
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_LD) */
|
||||
|
||||
#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F103 MD capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
#define STM32_HAS_DAC FALSE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
#define STM32_EXTI_NUM_CHANNELS 19
|
||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_MD) */
|
||||
|
||||
#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F103 HD capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
#define STM32_EXTI_NUM_CHANNELS 19
|
||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO TRUE
|
||||
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 TRUE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_HAS_TIM9 TRUE
|
||||
#define STM32_HAS_TIM10 TRUE
|
||||
#define STM32_HAS_TIM11 TRUE
|
||||
#define STM32_HAS_TIM12 TRUE
|
||||
#define STM32_HAS_TIM13 TRUE
|
||||
#define STM32_HAS_TIM14 TRUE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_HD) */
|
||||
|
||||
#if defined(STM32F10X_XL) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F103 XL capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
#define STM32_EXTI_NUM_CHANNELS 19
|
||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO TRUE
|
||||
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 TRUE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_XL) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform specific friendly IRQ names. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name IRQ VECTOR names
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
|
||||
#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
|
||||
detect. */
|
||||
|
|
@ -165,6 +502,7 @@
|
|||
#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */
|
||||
#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */
|
||||
#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
|
|
|
|||
|
|
@ -40,10 +40,25 @@
|
|||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#define PLATFORM_NAME "STM32 Connectivity Line"
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
|
||||
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CFGR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
|
||||
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
|
||||
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
|
||||
|
|
@ -97,15 +112,100 @@
|
|||
#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
|
||||
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as
|
||||
RTC clock. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CFGR2 register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CFGR2 register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
|
||||
#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name STM32F105/F107 CL capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 TRUE
|
||||
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
#define STM32_HAS_ETH TRUE
|
||||
|
||||
#define STM32_EXTI_NUM_CHANNELS 20
|
||||
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 TRUE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform specific friendly IRQ names. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name IRQ VECTOR names
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
|
||||
#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
|
||||
detect. */
|
||||
|
|
@ -172,7 +272,8 @@
|
|||
#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */
|
||||
#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */
|
||||
#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
|
|
@ -44,14 +44,24 @@
|
|||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Platform name.
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#define PLATFORM_NAME "STM32F2 High performance"
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HSICLK 16000000 /**< High speed internal clock. */
|
||||
#define STM32_LSICLK 38000 /**< Low speed internal clock. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_PLLCFGR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_PLLCFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
|
||||
#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
|
||||
#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
|
||||
|
|
@ -60,8 +70,12 @@
|
|||
|
||||
#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
|
||||
#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CFGR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_SW_MASK (3 << 0) /**< SW mask. */
|
||||
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
|
||||
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
|
||||
|
|
@ -120,11 +134,22 @@
|
|||
#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
|
||||
#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
|
||||
|
||||
/* RCC_PLLI2SCFGR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_PLLI2SCFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
|
||||
#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
|
||||
/** @} */
|
||||
|
||||
/* STM32F2xx capabilities.*/
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name STM32F4xx capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
|
|
@ -153,6 +178,7 @@
|
|||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
|
|
@ -189,11 +215,17 @@
|
|||
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_HAS_OTG2 TRUE
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform specific friendly IRQ names. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name IRQ VECTOR names
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
|
||||
#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
|
||||
detect. */
|
||||
|
|
@ -281,6 +313,8 @@
|
|||
#define DCMI_IRQHandler Vector178 /**< DCMI. */
|
||||
#define CRYP_IRQHandler Vector17C /**< CRYP. */
|
||||
#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */
|
||||
#define FPU_IRQHandler Vector184 /**< Floating Point Unit. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
|
|
@ -321,26 +355,12 @@
|
|||
#define STM32_LSE_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC clock setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_CLOCK_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USB clock setting.
|
||||
*/
|
||||
#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_USB_CLOCK_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Main clock source selection.
|
||||
* @note If the selected clock source is not the PLL then the PLL is not
|
||||
* initialized and started.
|
||||
* @note The default value is calculated for a 32MHz system clock from
|
||||
* the internal 16MHz HSI clock.
|
||||
* @note The default value is calculated for a 168MHz system clock from
|
||||
* an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_SW) || defined(__DOXYGEN__)
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
|
|
@ -350,8 +370,8 @@
|
|||
* @brief Clock source for the PLL.
|
||||
* @note This setting has only effect if the PLL is selected as the
|
||||
* system clock source.
|
||||
* @note The default value is calculated for a 120MHz system clock from
|
||||
* the external 25MHz HSE clock.
|
||||
* @note The default value is calculated for a 168MHz system clock from
|
||||
* an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
|
|
@ -360,8 +380,8 @@
|
|||
/**
|
||||
* @brief PLLM divider value.
|
||||
* @note The allowed values are 2..63.
|
||||
* @note The default value is calculated for a 120MHz system clock from
|
||||
* an external 25MHz HSE clock.
|
||||
* @note The default value is calculated for a 168MHz system clock from
|
||||
* an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLM_VALUE 25
|
||||
|
|
@ -370,8 +390,8 @@
|
|||
/**
|
||||
* @brief PLLN multiplier value.
|
||||
* @note The allowed values are 192..432.
|
||||
* @note The default value is calculated for a 120MHz system clock from
|
||||
* an external 25MHz HSE clock.
|
||||
* @note The default value is calculated for a 168MHz system clock from
|
||||
* an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLN_VALUE 240
|
||||
|
|
@ -380,8 +400,8 @@
|
|||
/**
|
||||
* @brief PLLP multiplier value.
|
||||
* @note The allowed values are DIV2, DIV4, DIV6, DIV8.
|
||||
* @note The default value is calculated for a 120MHz system clock from
|
||||
* an external 25MHz HSE clock.
|
||||
* @note The default value is calculated for a 168MHz system clock from
|
||||
* an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLP_VALUE 2
|
||||
|
|
@ -390,8 +410,8 @@
|
|||
/**
|
||||
* @brief PLLQ multiplier value.
|
||||
* @note The allowed values are 4..15.
|
||||
* @note The default value is calculated for a 120MHz system clock from
|
||||
* an external 25MHz HSE clock.
|
||||
* @note The default value is calculated for a 168MHz system clock from
|
||||
* an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLQ_VALUE 5
|
||||
|
|
@ -399,8 +419,8 @@
|
|||
|
||||
/**
|
||||
* @brief AHB prescaler value.
|
||||
* @note The default value is calculated for a 120MHz system clock from
|
||||
* an external 25MHz HSE clock.
|
||||
* @note The default value is calculated for a 168MHz system clock from
|
||||
* an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
|
|
|
|||
|
|
@ -50,27 +50,45 @@
|
|||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Platform name.
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#define PLATFORM_NAME "STM32L Ultra Low Power Medium Density"
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HSICLK 16000000 /**< High speed internal clock. */
|
||||
#define STM32_LSICLK 38000 /**< Low speed internal clock. */
|
||||
/** @} */
|
||||
|
||||
/* PWR_CR register bits definitions.*/
|
||||
/**
|
||||
* @name PWR_CR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
|
||||
#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
|
||||
#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
|
||||
#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
|
||||
#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
|
||||
#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
|
||||
#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
|
||||
#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CFGR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
|
||||
#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */
|
||||
#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
|
||||
|
|
@ -115,8 +133,12 @@
|
|||
#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */
|
||||
#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */
|
||||
#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */
|
||||
/** @} */
|
||||
|
||||
/* RCC_ICSCR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_ICSCR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
|
||||
#define STM32_MSIRANGE_64K (0 << 13) /**< 64KHz nominal. */
|
||||
#define STM32_MSIRANGE_128K (1 << 13) /**< 128KHz nominal. */
|
||||
|
|
@ -125,15 +147,27 @@
|
|||
#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
|
||||
#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
|
||||
#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
|
||||
/** @} */
|
||||
|
||||
/* RCC_CSR register bits definitions.*/
|
||||
/**
|
||||
* @name RCC_CSR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
|
||||
#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
|
||||
#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
|
||||
#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
|
||||
#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
|
||||
/** @} */
|
||||
|
||||
/* STM32L1xx capabilities.*/
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name STM32L1xx capabilities
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
|
|
@ -158,9 +192,11 @@
|
|||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
|
|
@ -197,9 +233,16 @@
|
|||
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform specific friendly IRQ names. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Platform specific friendly IRQ names
|
||||
* @name IRQ VECTOR names
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
|
||||
#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
|
||||
|
|
|
|||
|
|
@ -76,7 +76,11 @@
|
|||
*** 2.3.4 ***
|
||||
- FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620).
|
||||
- FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626).
|
||||
- NEW: Added EXT driver implementation for AT91SAM7x contributed by Florian.
|
||||
- NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute
|
||||
the capability macros into the appropriate file (previously those were all
|
||||
in the common hal_lld.h).
|
||||
- NEW: Added USE_COPT setting to all makefiles, contributed by Mabl.
|
||||
- NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian.
|
||||
(TODO: Test application missing).
|
||||
- NEW: Updated USB driver model and STM32 implementation and fixed several
|
||||
problems.
|
||||
|
|
|
|||
Loading…
Reference in New Issue