rusefi
/
ChibiOS
mirror of https://github.com/rusefi/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Incomplete OCTOSPIv2 for STM32. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15483 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2022-03-11 09:15:47 +00:00
parent 5fdb9afce9
commit 6fee977d76
13 changed files with 1077 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h
View File

@ -183,7 +183,8 @@
#define STM32_IRQ_MDMA_PRIORITY 9
#define STM32_IRQ_QUADSPI1_PRIORITY 10
#define STM32_IRQ_OCTOSPI1_PRIORITY 10
#define STM32_IRQ_OCTOSPI2_PRIORITY 10
#define STM32_IRQ_SDMMC1_PRIORITY 9
#define STM32_IRQ_SDMMC2_PRIORITY 9
@ -485,5 +486,16 @@
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_OCTOSPI1 TRUE
#define STM32_WSPI_USE_OCTOSPI2 TRUE
#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
#define STM32_WSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
#endif /* MCUCONF_H */

2
os/common/startup/ARMCMx/devices/STM32H7xx/cmparams.h
View File

@ -65,7 +65,7 @@
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 152
#define CORTEX_NUM_VECTORS 168
/* The following code is not processed when the file is included from an
asm module.*/

9
os/hal/ports/STM32/LLD/OCTOSPIv2/driver.mk Normal file
View File

@ -0,0 +1,9 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_WSPI TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c
endif
PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv2

464
os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c Normal file
View File

@ -0,0 +1,464 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file OCTOSPIv1/hal_wspi_lld.c
* @brief STM32 WSPI subsystem low level driver source.
*
* @addtogroup WSPI
* @{
*/
#include "hal.h"
#if (HAL_USE_WSPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/* Workarounds for bugs in ST headers.*/
#if !defined(OCTOSPI_FCR_CTOF) && defined(OCTOSPI_FCR_TOF)
#define OCTOSPI_FCR_CTOF OCTOSPI_FCR_TOF
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief OCTOSPI1 driver identifier.*/
#if STM32_WSPI_USE_OCTOSPI1 || defined(__DOXYGEN__)
WSPIDriver WSPID1;
#endif
/** @brief OCTOSPI2 driver identifier.*/
#if STM32_WSPI_USE_OCTOSPI2 || defined(__DOXYGEN__)
WSPIDriver WSPID2;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Waits for completion of previous operation.
*/
static inline void wspi_lld_sync(WSPIDriver *wspip) {
while ((wspip->ospi->SR & OCTOSPI_SR_BUSY) != 0U) {
}
}
/**
* @brief Shared service routine.
*
* @param[in] wspip pointer to the @p WSPIDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void wspi_lld_serve_dma_interrupt(WSPIDriver *wspip, uint32_t flags) {
(void)wspip;
(void)flags;
/* DMA errors handling.*/
#if defined(STM32_WSPI_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_WSPI_DMA_ERROR_HOOK(wspip);
}
#endif
}
/**
* @brief Shared service routine.
*
* @param[in] wspip pointer to the @p WSPIDriver object
*/
static void wspi_lld_serve_interrupt(WSPIDriver *wspip) {
/* Portable WSPI ISR code defined in the high level driver, note, it is
a macro.*/
_wspi_isr_code(wspip);
/* Stop everything, we need to give DMA enough time to complete the ongoing
operation. Race condition hidden here.*/
while (dmaStreamGetTransactionSize(wspip->dma) > 0U)
;
dmaStreamDisable(wspip->dma);
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_WSPI_USE_OCTOSPI1 || defined(__DOXYGEN__)
#if !defined(STM32_OCTOSPI1_SUPPRESS_ISR)
#if !defined(STM32_OCTOSPI1_HANDLER)
#error "STM32_OCTOSPI1_HANDLER not defined"
#endif
/**
* @brief STM32_OCTOSPI1_HANDLER interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_OCTOSPI1_HANDLER) {
OSAL_IRQ_PROLOGUE();
OCTOSPI1->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
wspi_lld_serve_interrupt(&WSPID1);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(STM32_OCTOSPI1_SUPPRESS_ISR) */
#endif /* STM32_WSPI_USE_OCTOSPI1 */
#if STM32_WSPI_USE_OCTOSPI2 || defined(__DOXYGEN__)
#if !defined(STM32_OCTOSPI2_SUPPRESS_ISR)
#if !defined(STM32_OCTOSPI2_HANDLER)
#error "STM32_OCTOSPI2_HANDLER not defined"
#endif
/**
* @brief STM32_OCTOSPI2_HANDLER interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_OCTOSPI2_HANDLER) {
OSAL_IRQ_PROLOGUE();
OCTOSPI2->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
wspi_lld_serve_interrupt(&WSPID2);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(STM32_OCTOSPI2_SUPPRESS_ISR) */
#endif /* STM32_WSPI_USE_OCTOSPI2 */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level WSPI driver initialization.
*
* @notapi
*/
void wspi_lld_init(void) {
#if STM32_WSPI_USE_OCTOSPI1
wspiObjectInit(&WSPID1);
WSPID1.ospi = OCTOSPI1;
WSPID1.dma = NULL;
WSPID1.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI1_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_WSPI_OCTOSPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_BYTE |
STM32_DMA_CR_MSIZE_BYTE |
STM32_DMA_CR_MINC |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
nvicEnableVector(STM32_OCTOSPI1_NUMBER, STM32_WSPI_OCTOSPI1_IRQ_PRIORITY);
#endif
#if STM32_WSPI_USE_OCTOSPI2
wspiObjectInit(&WSPID2);
WSPID2.ospi = OCTOSPI2;
WSPID2.dma = NULL;
WSPID2.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI2_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_WSPI_OCTOSPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_BYTE |
STM32_DMA_CR_MSIZE_BYTE |
STM32_DMA_CR_MINC |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
nvicEnableVector(STM32_OCTOSPI2_NUMBER, STM32_WSPI_OCTOSPI2_IRQ_PRIORITY);
#endif
}
/**
* @brief Configures and activates the WSPI peripheral.
*
* @param[in] wspip pointer to the @p WSPIDriver object
*
* @notapi
*/
void wspi_lld_start(WSPIDriver *wspip) {
/* If in stopped state then full initialization.*/
if (wspip->state == WSPI_STOP) {
#if STM32_WSPI_USE_OCTOSPI1
if (&WSPID1 == wspip) {
wspip->dma = dmaStreamAllocI(STM32_WSPI_OCTOSPI1_DMA_STREAM,
STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)wspi_lld_serve_dma_interrupt,
(void *)wspip);
osalDbgAssert(wspip->dma != NULL, "unable to allocate stream");
rccEnableOCTOSPI1(true);
dmaSetRequestSource(wspip->dma, STM32_DMAMUX1_OCTOSPI1);
}
#endif
#if STM32_WSPI_USE_OCTOSPI2
if (&WSPID2 == wspip) {
wspip->dma = dmaStreamAllocI(STM32_WSPI_OCTOSPI2_DMA_STREAM,
STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)wspi_lld_serve_dma_interrupt,
(void *)wspip);
osalDbgAssert(wspip->dma != NULL, "unable to allocate stream");
rccEnableOCTOSPI2(true);
dmaSetRequestSource(wspip->dma, STM32_DMAMUX1_OCTOSPI2);
}
#endif
/* Common initializations.*/
dmaStreamSetPeripheral(wspip->dma, &wspip->ospi->DR);
}
/* WSPI setup and enable.*/
wspip->ospi->DCR1 = wspip->config->dcr1;
wspip->ospi->DCR2 = wspip->config->dcr2 |
STM32_DCR2_PRESCALER(STM32_WSPI_OCTOSPI1_PRESCALER_VALUE - 1U);
wspip->ospi->DCR3 = wspip->config->dcr3;
wspip->ospi->CR = OCTOSPI_CR_TCIE | OCTOSPI_CR_DMAEN | OCTOSPI_CR_EN;
wspip->ospi->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
}
/**
* @brief Deactivates the WSPI peripheral.
*
* @param[in] wspip pointer to the @p WSPIDriver object
*
* @notapi
*/
void wspi_lld_stop(WSPIDriver *wspip) {
/* Waiting for the previous operation to complete, if any.*/
wspi_lld_sync(wspip);
/* If in ready state then disables the OCTOSPI clock.*/
if (wspip->state == WSPI_READY) {
/* WSPI disable.*/
wspip->ospi->CR = 0U;
/* Releasing the DMA.*/
dmaStreamFreeI(wspip->dma);
wspip->dma = NULL;
/* Stopping involved clocks.*/
#if STM32_WSPI_USE_OCTOSPI1
if (&WSPID1 == wspip) {
rccDisableOCTOSPI1();
}
#endif
}
}
/**
* @brief Sends a command without data phase.
* @post At the end of the operation the configured callback is invoked.
*
* @param[in] wspip pointer to the @p WSPIDriver object
* @param[in] cmdp pointer to the command descriptor
*
* @notapi
*/
void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
#if 0 //STM32_USE_STM32_D1_WORKAROUND == TRUE
/* If it is a command without address and alternate phases then the command
is sent as an alternate byte, the command phase is suppressed.*/
if ((cmdp->cfg & (WSPI_CFG_ADDR_MODE_MASK | WSPI_CFG_ALT_MODE_MASK)) == 0U) {
/* The command mode field is copied in the alternate mode field. All
other fields are not used in this scenario.*/
wspip->ospi->DLR = 0U;
wspip->ospi->ABR = cmdp->cmd;
wspip->ospi->CCR = (cmdp->cfg & WSPI_CFG_CMD_MODE_MASK) << 6U;
return;
}
#endif
wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
wspip->ospi->DLR = 0U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
wspip->ospi->AR = cmdp->addr;
}
/* Waiting for the previous operation to complete.*/
wspi_lld_sync(wspip);
}
/**
* @brief Sends a command with data over the WSPI bus.
* @post At the end of the operation the configured callback is invoked.
* @note If using DTR in 8 lines mode then the following restrictions
* apply:
* - Command size must be 0, 2 or 4 bytes.
* - Address must be even.
* - Alternate bytes size must be 0, 2 or 4 bytes.
* - Data size must be a multiple of two.
* .
* There is no check on the above conditions in order to keep the
* code efficient.
*
* @param[in] wspip pointer to the @p WSPIDriver object
* @param[in] cmdp pointer to the command descriptor
* @param[in] n number of bytes to send
* @param[in] txbuf the pointer to the transmit buffer
*
* @notapi
*/
void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
size_t n, const uint8_t *txbuf) {
dmaStreamSetMemory0(wspip->dma, txbuf);
dmaStreamSetTransactionSize(wspip->dma, n);
dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_M2P);
wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
wspip->ospi->AR = cmdp->addr;
}
dmaStreamEnable(wspip->dma);
}
/**
* @brief Sends a command then receives data over the WSPI bus.
* @post At the end of the operation the configured callback is invoked.
* @note If using DTR in 8 lines mode then the following restrictions
* apply:
* - Command size must be 0, 2 or 4 bytes.
* - Address must be even.
* - Alternate bytes size must be 0, 2 or 4 bytes.
* - Data size must be a multiple of two.
* .
* There is no check on the above conditions in order to keep the
* code efficient.
*
* @param[in] wspip pointer to the @p WSPIDriver object
* @param[in] cmdp pointer to the command descriptor
* @param[in] n number of bytes to send
* @param[out] rxbuf the pointer to the receive buffer
*
* @notapi
*/
void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
size_t n, uint8_t *rxbuf) {
dmaStreamSetMemory0(wspip->dma, rxbuf);
dmaStreamSetTransactionSize(wspip->dma, n);
dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_P2M);
wspip->ospi->CR = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) | OCTOSPI_CR_FMODE_0;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
wspip->ospi->AR = cmdp->addr;
}
dmaStreamEnable(wspip->dma);
}
#if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)
/**
* @brief Maps in memory space a WSPI flash device.
* @pre The memory flash device must be initialized appropriately
* before mapping it in memory space.
*
* @param[in] wspip pointer to the @p WSPIDriver object
* @param[in] cmdp pointer to the command descriptor
* @param[out] addrp pointer to the memory start address of the mapped
* flash or @p NULL
*
* @notapi
*/
void wspi_lld_map_flash(WSPIDriver *wspip,
const wspi_command_t *cmdp,
uint8_t **addrp) {
/* Starting memory mapped mode using the passed parameters.*/
wspip->ospi->CR = OCTOSPI_CR_FMODE_1 | OCTOSPI_CR_FMODE_0 | OCTOSPI_CR_EN;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->IR = cmdp->cmd;
wspip->ospi->ABR = 0U;
wspip->ospi->AR = 0U;
wspip->ospi->WTCR = 0U;
wspip->ospi->WCCR = 0U;
wspip->ospi->WIR = 0U;
wspip->ospi->WABR = 0U;
/* Mapped flash absolute base address.*/
#if STM32_WSPI_USE_OCTOSPI1
if (&WSPID1 == wspip) {
if (addrp != NULL) {
*addrp = (uint8_t *)0x90000000U;
}
}
#endif
#if STM32_WSPI_USE_OCTOSPI2
if (&WSPID2 == wspip) {
if (addrp != NULL) {
*addrp = (uint8_t *)0x70000000U;
}
}
#endif
}
/**
* @brief Unmaps from memory space a WSPI flash device.
* @post The memory flash device must be re-initialized for normal
* commands exchange.
*
* @param[in] wspip pointer to the @p WSPIDriver object
*
* @notapi
*/
void wspi_lld_unmap_flash(WSPIDriver *wspip) {
/* Aborting memory mapped mode.*/
wspip->ospi->CR |= OCTOSPI_CR_ABORT;
while ((wspip->ospi->CR & OCTOSPI_CR_ABORT) != 0U) {
}
/* Disabling memory mapped mode and re-enabling DMA and IRQs.*/
wspip->ospi->CR = OCTOSPI_CR_TCIE | OCTOSPI_CR_DMAEN | OCTOSPI_CR_EN;
}
#endif /* WSPI_SUPPORTS_MEMMAP == TRUE */
#endif /* HAL_USE_WSPI */
/** @} */

334
os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.h Normal file
View File

@ -0,0 +1,334 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file OCTOSPIv1/hal_wspi_lld.h
* @brief STM32 WSPI subsystem low level driver header.
*
* @addtogroup WSPI
* @{
*/
#ifndef HAL_WSPI_LLD_H
#define HAL_WSPI_LLD_H
#if (HAL_USE_WSPI == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name WSPI implementation capabilities
* @{
*/
#define WSPI_SUPPORTS_MEMMAP TRUE
#define WSPI_DEFAULT_CFG_MASKS TRUE
/** @} */
/**
* @name DCR1 register options
* @{
*/
#define STM32_DCR1_CK_MODE (1U << 0U)
#define STM32_DCR1_FRCK_MODE (1U << 1U)
#define STM32_DCR1_CSHT_MASK (7U << 8U)
#define STM32_DCR1_CSHT(n) ((n) << 8U)
#define STM32_DCR1_DEVSIZE_MASK (31U << 16U)
#define STM32_DCR1_DEVSIZE(n) ((n) << 16U)
#define STM32_DCR1_MTYP_MASK (7U << 16U)
#define STM32_DCR1_MTYP(n) ((n) << 24U)
/** @} */
/**
* @name DCR2 register options
* @{
*/
#define STM32_DCR2_PRESCALER_MASK (255U << 0U)
#define STM32_DCR2_PRESCALER(n) ((n) << 0U)
#define STM32_DCR2_WRAPSIZE_MASK (7U << 16U)
#define STM32_DCR2_WRAPSIZE(n) ((n) << 16U)
/**
* @name DCR3 register options
* @{
*/
#define STM32_DCR3_MAXTRAN_MASK (255U << 0U)
#define STM32_DCR3_MAXTRAN(n) ((n) << 0U)
#define STM32_DCR3_CSBOUND_MASK (7U << 16U)
#define STM32_DCR3_CSBOUND(n) ((n) << 16U)
/**
* @name DCR4 register options
* @{
*/
#define STM32_DCR4_REFRESH_MASK (255U << 0U)
#define STM32_DCR4_REFRESH(n) ((n) << 0U)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief WSPID1 driver enable switch.
* @details If set to @p TRUE the support for OCTOSPI1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_WSPI_USE_OCTOSPI1) || defined(__DOXYGEN__)
#define STM32_WSPI_USE_OCTOSPI1 FALSE
#endif
/**
* @brief WSPID2 driver enable switch.
* @details If set to @p TRUE the support for OCTOSPI2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_WSPI_USE_OCTOSPI2) || defined(__DOXYGEN__)
#define STM32_WSPI_USE_OCTOSPI2 FALSE
#endif
/**
* @brief OCTOSPI1 prescaler setting.
* @note This is the prescaler divider value 1..256. The maximum frequency
* varies depending on the STM32 model and operating conditions,
* find the details in the data sheet.
*/
#if !defined(STM32_WSPI_OCTOSPI1_PRESCALER_VALUE) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
#endif
/**
* @brief OCTOSPI2 prescaler setting.
* @note This is the prescaler divider value 1..256. The maximum frequency
* varies depending on the STM32 model and operating conditions,
* find the details in the data sheet.
*/
#if !defined(STM32_WSPI_OCTOSPI2_PRESCALER_VALUE) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#endif
/**
* @brief OCTOSPI1 interrupt priority level setting.
*/
#if !defined(STM32_WSPI_OCTOSPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#endif
/**
* @brief OCTOSPI2 interrupt priority level setting.
*/
#if !defined(STM32_WSPI_OCTOSPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#endif
/**
* @brief OCTOSPI1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_WSPI_OCTOSPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#endif
/**
* @brief OCTOSPI2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_WSPI_OCTOSPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#endif
/**
* @brief OCTOSPI1 DMA interrupt priority level setting.
*/
#if !defined(STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
#endif
/**
* @brief OCTOSPI2 DMA interrupt priority level setting.
*/
#if !defined(STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
#endif
/**
* @brief OCTOSPI DMA error hook.
*/
#if !defined(STM32_WSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_WSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(STM32_HAS_OCTOSPI1)
#define STM32_HAS_OCTOSPI1 FALSE
#endif
#if !defined(STM32_HAS_OCTOSPI2)
#define STM32_HAS_OCTOSPI2 FALSE
#endif
#if STM32_WSPI_USE_OCTOSPI1 && !STM32_HAS_OCTOSPI1
#error "OCTOSPI1 not present in the selected device"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && !STM32_HAS_OCTOSPI2
#error "OCTOSPI2 not present in the selected device"
#endif
#if !STM32_WSPI_USE_OCTOSPI1 && !STM32_WSPI_USE_OCTOSPI2
#error "WSPI driver activated but no OCTOSPI peripheral assigned"
#endif
/* Check on OCTOSPI prescaler setting.*/
#if (STM32_WSPI_OCTOSPI1_PRESCALER_VALUE < 1) || \
(STM32_WSPI_OCTOSPI1_PRESCALER_VALUE > 256)
#error "STM32_WSPI_OCTOSPI1_PRESCALER_VALUE not within 1..256"
#endif
/* Check on IRQ priorities.*/
#if STM32_WSPI_USE_OCTOSPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OCTOSPI1"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OCTOSPI2"
#endif
#if STM32_WSPI_USE_OCTOSPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OCTOSPI1 DMA"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OCTOSPI2 DMA"
#endif
/* Check on the presence of the DMA channels settings in mcuconf.h.*/
#if STM32_WSPI_USE_OCTOSPI1 && !defined(STM32_WSPI_OCTOSPI1_DMA_STREAM)
#error "OCTOSPI1 DMA stream not defined"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && !defined(STM32_WSPI_OCTOSPI2_DMA_STREAM)
#error "OCTOSPI2 DMA stream not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_WSPI_USE_OCTOSPI1 && \
!STM32_DMA_IS_VALID_STREAM(STM32_WSPI_OCTOSPI1_DMA_STREAM)
#error "invalid DMA stream associated to OCTOSPI1"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && \
!STM32_DMA_IS_VALID_STREAM(STM32_WSPI_OCTOSPI2_DMA_STREAM)
#error "invalid DMA stream associated to OCTOSPI2"
#endif
/* Check on DMA channels priority.*/
#if STM32_WSPI_USE_OCTOSPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to OCTOSPI1"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to OCTOSPI2"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the WSPI configuration structure.
*/
#define wspi_lld_config_fields \
/* DCR1 register initialization data.*/ \
uint32_t dcr1; \
/* DCR2 register initialization data. The prescaler field is internally \
ORed to this field, leave it to zero.*/ \
uint32_t dcr2; \
/* DCR3 register initialization data.*/ \
uint32_t dcr3; \
/* DCR4 register initialization data.*/ \
uint32_t dcr4
/**
* @brief Low level fields of the WSPI driver structure.
*/
#define wspi_lld_driver_fields \
/* Pointer to the OCTOSPIx registers block.*/ \
OCTOSPI_TypeDef *ospi; \
/* OCTOSPI DMA stream.*/ \
const stm32_dma_stream_t *dma; \
/* OCTOSPI DMA mode bit mask.*/ \
uint32_t dmamode
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if (STM32_WSPI_USE_OCTOSPI1 == TRUE) && !defined(__DOXYGEN__)
extern WSPIDriver WSPID1;
#endif
#if (STM32_WSPI_USE_OCTOSPI2 == TRUE) && !defined(__DOXYGEN__)
extern WSPIDriver WSPID2;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void wspi_lld_init(void);
void wspi_lld_start(WSPIDriver *wspip);
void wspi_lld_stop(WSPIDriver *wspip);
void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp);
void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
size_t n, const uint8_t *txbuf);
void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
size_t n, uint8_t *rxbuf);
#if WSPI_SUPPORTS_MEMMAP == TRUE
void wspi_lld_map_flash(WSPIDriver *wspip,
const wspi_command_t *cmdp,
uint8_t **addrp);
void wspi_lld_unmap_flash(WSPIDriver *wspip);
#endif
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_WSPI */
#endif /* HAL_WSPI_LLD_H */
/** @} */

110
os/hal/ports/STM32/LLD/OCTOSPIv2/stm32_octospi1.inc Normal file
View File

@ -0,0 +1,110 @@
/*
ChibiOS - Copyright (C) 2006..2022 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file OCTOSPIv2/stm32_octospi1.inc
* @brief Shared OCTOSPI1 handler.
*
* @addtogroup STM32_OCTOSPI1_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_OCTOSPI1)
#error "STM32_HAS_OCTOSPI1 not defined in registry"
#endif
#if STM32_HAS_OCTOSPI1
/* Priority settings checks.*/
#if !defined(STM32_IRQ_OCTOSPI1_PRIORITY)
#error "STM32_IRQ_OCTOSPI1_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_OCTOSPI1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_OCTOSPI1_PRIORITY"
#endif
#endif /* STM32_HAS_OCTOSPI1 */
/* Other checks.*/
#if (HAL_USE_WSPI && STM32_WSPI_USE_OCTOSPI1)
#define STM32_OCTOSPI1_IS_USED TRUE
#else
#define STM32_OCTOSPI1_IS_USED FALSE
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void octospi1_irq_init(void) {
#if STM32_OCTOSPI1_IS_USED
nvicEnableVector(STM32_OCTOSPI1_NUMBER, STM32_IRQ_OCTOSPI1_PRIORITY);
#endif
}
static inline void octospi1_irq_deinit(void) {
#if STM32_OCTOSPI1_IS_USED
nvicDisableVector(STM32_OCTOSPI1_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_OCTOSPI1_IS_USED|| defined(__DOXYGEN__)
/**
* @brief OCTOSPI1 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_OCTOSPI1_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_WSPI
#if STM32_WSPI_USE_OCTOSPI1
wspi_lld_serve_interrupt(&WSPID1);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

110
os/hal/ports/STM32/LLD/OCTOSPIv2/stm32_octospi2.inc Normal file
View File

@ -0,0 +1,110 @@
/*
ChibiOS - Copyright (C) 2006..2022 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file OCTOSPIv2/stm32_octospi1.inc
* @brief Shared OCTOSPI2 handler.
*
* @addtogroup STM32_OCTOSPI2_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_OCTOSPI2)
#error "STM32_HAS_OCTOSPI2 not defined in registry"
#endif
#if STM32_HAS_OCTOSPI2
/* Priority settings checks.*/
#if !defined(STM32_IRQ_OCTOSPI2_PRIORITY)
#error "STM32_IRQ_OCTOSPI2_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_OCTOSPI2_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_OCTOSPI2_PRIORITY"
#endif
#endif /* STM32_HAS_OCTOSPI2 */
/* Other checks.*/
#if (HAL_USE_WSPI && STM32_WSPI_USE_OCTOSPI2)
#define STM32_OCTOSPI2_IS_USED TRUE
#else
#define STM32_OCTOSPI2_IS_USED FALSE
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void octospi2_irq_init(void) {
#if STM32_OCTOSPI2_IS_USED
nvicEnableVector(STM32_OCTOSPI2_NUMBER, STM32_IRQ_OCTOSPI2_PRIORITY);
#endif
}
static inline void octospi2_irq_deinit(void) {
#if STM32_OCTOSPI2_IS_USED
nvicDisableVector(STM32_OCTOSPI2_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_OCTOSPI2_IS_USED|| defined(__DOXYGEN__)
/**
* @brief OCTOSPI2 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_OCTOSPI2_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_WSPI
#if STM32_WSPI_USE_OCTOSPI2
wspi_lld_serve_interrupt(&WSPID2);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

4
os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h
View File

@ -1225,6 +1225,7 @@
#define STM32_1WS_THRESHOLD 140000000U
#define STM32_2WS_THRESHOLD 210000000U
#define STM32_3WS_THRESHOLD 275000000U
#define STM32_4WS_THRESHOLD 0U
#define STM32_PLLOUT_MAX 550000000U
#define STM32_PLLOUT_MIN 1500000U
@ -1233,6 +1234,7 @@
#define STM32_1WS_THRESHOLD 133000000U
#define STM32_2WS_THRESHOLD 200000000U
#define STM32_3WS_THRESHOLD 0U
#define STM32_4WS_THRESHOLD 0U
#define STM32_PLLOUT_MAX 400000000U
#define STM32_PLLOUT_MIN 1500000U
@ -1241,6 +1243,7 @@
#define STM32_1WS_THRESHOLD 100000000U
#define STM32_2WS_THRESHOLD 150000000U
#define STM32_3WS_THRESHOLD 0U
#define STM32_4WS_THRESHOLD 0U
#define STM32_PLLOUT_MAX 300000000U
#define STM32_PLLOUT_MIN 1500000U
@ -1249,6 +1252,7 @@
#define STM32_1WS_THRESHOLD 70000000U
#define STM32_2WS_THRESHOLD 85000000U
#define STM32_3WS_THRESHOLD 0U
#define STM32_4WS_THRESHOLD 0U
#define STM32_PLLOUT_MAX 170000000U
#define STM32_PLLOUT_MIN 1500000U

1
os/hal/ports/STM32/STM32H7xx/platform_type2.mk
View File

@ -36,6 +36,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/MDMAv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/driver_v2.mk

9
os/hal/ports/STM32/STM32H7xx/stm32_isr.c
View File

@ -70,7 +70,8 @@
#if defined(HAL_LLD_TYPE1_H)
#include "stm32_quadspi1.inc"
#elif defined(HAL_LLD_TYPE2_H)
//#include "stm32_octospi1.inc"
#include "stm32_octospi1.inc"
#include "stm32_octospi2.inc"
#endif
#include "stm32_sdmmc1.inc"
@ -127,7 +128,8 @@ void irqInit(void) {
#if defined(HAL_LLD_TYPE1_H)
quadspi1_irq_init();
#elif defined(HAL_LLD_TYPE2_H)
// octospi1_irq_init();
octospi1_irq_init();
octospi2_irq_init();
#endif
sdmmc1_irq_init();
@ -181,7 +183,8 @@ void irqDeinit(void) {
#if defined(HAL_LLD_TYPE1_H)
quadspi1_irq_deinit();
#elif defined(HAL_LLD_TYPE2_H)
// octospi1_irq_deinit();
octospi1_irq_deinit();
octospi2_irq_deinit();
#endif
sdmmc1_irq_deinit();

9
os/hal/ports/STM32/STM32H7xx/stm32_isr.h
View File

@ -214,6 +214,15 @@
#define STM32_QUADSPI1_NUMBER 92
/*
* OCTOSPI units.
*/
#define STM32_OCTOSPI1_HANDLER Vector1B0
#define STM32_OCTOSPI2_HANDLER Vector298
#define STM32_OCTOSPI1_NUMBER 92
#define STM32_OCTOSPI2_NUMBER 150
/*
* SDMMC units.
*/

3
os/hal/ports/STM32/STM32H7xx/stm32_registry.h
View File

@ -192,6 +192,7 @@
/* OCTOSPI attributes.*/
#define STM32_HAS_OCTOSPI1 FALSE
#define STM32_HAS_OCTOSPI2 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
@ -425,6 +426,7 @@
/* OCTOSPI attributes.*/
#define STM32_HAS_OCTOSPI1 TRUE
#define STM32_HAS_OCTOSPI2 TRUE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
@ -648,6 +650,7 @@
/* OCTOSPI attributes.*/
#define STM32_HAS_OCTOSPI1 FALSE
#define STM32_HAS_OCTOSPI2 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE

14
tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl
View File

@ -194,7 +194,8 @@
#define STM32_IRQ_MDMA_PRIORITY ${doc.STM32_IRQ_MDMA_PRIORITY!"9"}
#define STM32_IRQ_QUADSPI1_PRIORITY ${doc.STM32_IRQ_QUADSPI1_PRIORITY!"10"}
#define STM32_IRQ_OCTOSPI1_PRIORITY ${doc.STM32_IRQ_OCTOSPI1_PRIORITY!"10"}
#define STM32_IRQ_OCTOSPI2_PRIORITY ${doc.STM32_IRQ_OCTOSPI2_PRIORITY!"10"}
#define STM32_IRQ_SDMMC1_PRIORITY ${doc.STM32_IRQ_SDMMC1_PRIORITY!"9"}
#define STM32_IRQ_SDMMC2_PRIORITY ${doc.STM32_IRQ_SDMMC2_PRIORITY!"9"}
@ -496,5 +497,16 @@
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_OCTOSPI1 ${doc.STM32_WSPI_USE_OCTOSPI1!"FALSE"}
#define STM32_WSPI_USE_OCTOSPI2 ${doc.STM32_WSPI_USE_OCTOSPI2!"FALSE"}
#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI1_PRESCALER_VALUE!"1"}
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI2_PRESCALER_VALUE!"1"}
#define STM32_WSPI_OCTOSPI1_DMA_STREAM ${doc.STM32_WSPI_OCTOSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_WSPI_OCTOSPI2_DMA_STREAM ${doc.STM32_WSPI_OCTOSPI2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_PRIORITY!"1"}
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_DMA_PRIORITY!"1"}
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY!"10"}
#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY!"10"}
#define STM32_WSPI_DMA_ERROR_HOOK(qspip) ${doc.STM32_WSPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
#endif /* MCUCONF_H */