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STM32 FSMC NAND. Cleaned rest of v2.6 calls 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7130 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2014-08-05 14:37:04 +00:00
parent 3988ae9c5e
commit 70574490da
5 changed files with 138 additions and 34 deletions
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14
os/hal/ports/STM32/LLD/emc_lld.c
View File

@ -106,8 +106,7 @@ void emc_lld_start(EMCDriver *emcp) {
rccResetFSMC(); rccResetFSMC();
rccEnableFSMC(FALSE); rccEnableFSMC(FALSE);
#if STM32_EMC_USE_INT #if STM32_EMC_USE_INT
nvicEnableVector(FSMC_IRQn, nvicEnableVector(FSMC_IRQn, STM32_EMC_FSMC1_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_EMC_FSMC1_IRQ_PRIORITY));
#endif /* STM32_EMC_USE_INT */ #endif /* STM32_EMC_USE_INT */
} }
#endif /* PLATFORM_STM32_USE_EMC1 */ #endif /* PLATFORM_STM32_USE_EMC1 */
@ -150,9 +149,8 @@ void emc_lld_stop(EMCDriver *emcp) {
* @notapi * @notapi
*/ */
void emc_lld_serve_interrupt(void) { void emc_lld_serve_interrupt(void) {
#warning "This functionality untested"
chDbgPanic("Unrealized"); osalSysHalt("Unrealized");
} }
/** /**
@ -161,17 +159,19 @@ void emc_lld_serve_interrupt(void) {
* @notapi * @notapi
*/ */
CH_IRQ_HANDLER(FSMC_IRQHandler) { CH_IRQ_HANDLER(FSMC_IRQHandler) {
#warning "This functionality untested" osalSysHalt("This functionality untested");
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
#if STM32_EMCNAND_USE_EMCNAND1
if (EMCD1.nand1->SR & FSMC_SR_ISR_MASK){ if (EMCD1.nand1->SR & FSMC_SR_ISR_MASK){
EMCNANDD1.isr_handler(&EMCNANDD1, EMCD1.nand1->SR); EMCNANDD1.isr_handler(&EMCNANDD1, EMCD1.nand1->SR);
} }
#endif
#if STM32_EMCNAND_USE_EMCNAND2
if (EMCD1.nand2->SR & FSMC_SR_ISR_MASK){ if (EMCD1.nand2->SR & FSMC_SR_ISR_MASK){
EMCNANDD2.isr_handler(&EMCNANDD2, EMCD1.nand2->SR); EMCNANDD2.isr_handler(&EMCNANDD2, EMCD1.nand2->SR);
} }
#endif
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
} }
#endif /* STM32_EMC_USE_INT */ #endif /* STM32_EMC_USE_INT */

26
os/hal/ports/STM32/LLD/emcnand_lld.c
View File

@ -74,16 +74,10 @@ EMCNANDDriver EMCNANDD2;
* *
* @notapi * @notapi
*/ */
static void wakeup_isr(EMCNANDDriver *emcnandp, msg_t msg){ static void wakeup_isr(EMCNANDDriver *emcnandp){
osalDbgCheck(emcnandp->thread != NULL); osalDbgCheck(emcnandp->thread != NULL);
osalThreadResumeI(&emcnandp->thread, MSG_OK);
if (emcnandp->thread) {
thread_t *tp = emcnandp->thread;
emcnandp->thread = NULL;
tp->p_u.rdymsg = msg;
chSchReadyI(tp);
}
} }
/** /**
@ -93,8 +87,8 @@ static void wakeup_isr(EMCNANDDriver *emcnandp, msg_t msg){
*/ */
static void emcnand_lld_suspend_thread(EMCNANDDriver *emcnandp) { static void emcnand_lld_suspend_thread(EMCNANDDriver *emcnandp) {
emcnandp->thread = chThdGetSelfX(); //emcnandp->thread = chThdGetSelfX();
chSchGoSleepS(CH_STATE_SUSPENDED); osalThreadSuspendS(&emcnandp->thread);
} }
/** /**
@ -130,7 +124,7 @@ static uint32_t calc_eccps(EMCNANDDriver *emcnandp){
*/ */
static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) { static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) {
emcnandp->nand->SR |= FSMC_SR_IREN; emcnandp->nand->SR |= FSMC_SR_IREN;
chDbgPanic("Function untested"); osalSysHalt("Function untested");
} }
/** /**
@ -142,7 +136,7 @@ static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) {
*/ */
static void emcnand_ready_isr_disable(EMCNANDDriver *emcnandp) { static void emcnand_ready_isr_disable(EMCNANDDriver *emcnandp) {
emcnandp->nand->SR &= ~FSMC_SR_IREN; emcnandp->nand->SR &= ~FSMC_SR_IREN;
chDbgPanic("Function untested"); osalSysHalt("Function untested");
} }
/** /**
@ -158,7 +152,7 @@ static void emcnand_isr_handler (EMCNANDDriver *emcnandp,
(void)emcnandp; (void)emcnandp;
(void)flags; (void)flags;
chDbgPanic("Unrealized"); osalSysHalt("Unrealized");
} }
#else /* STM32_EMC_USE_INT */ #else /* STM32_EMC_USE_INT */
/** /**
@ -205,13 +199,13 @@ static void emcnand_isr_handler(EMCNANDDriver *emcnandp){
case EMCNAND_ERASE: case EMCNAND_ERASE:
/* NAND reports about erase finish */ /* NAND reports about erase finish */
emcnandp->state = EMCNAND_READY; emcnandp->state = EMCNAND_READY;
wakeup_isr(emcnandp, MSG_OK); wakeup_isr(emcnandp);
break; break;
case EMCNAND_PROGRAM: case EMCNAND_PROGRAM:
/* NAND reports about page programming finish */ /* NAND reports about page programming finish */
emcnandp->state = EMCNAND_READY; emcnandp->state = EMCNAND_READY;
wakeup_isr(emcnandp, MSG_OK); wakeup_isr(emcnandp);
break; break;
default: default:
@ -257,7 +251,7 @@ static void emcnand_lld_serve_transfer_end_irq(EMCNANDDriver *emcnandp,
emcnandp->state = EMCNAND_READY; emcnandp->state = EMCNAND_READY;
emcnandp->rxdata = NULL; emcnandp->rxdata = NULL;
emcnandp->datalen = 0; emcnandp->datalen = 0;
wakeup_isr(emcnandp, MSG_OK); wakeup_isr(emcnandp);
break; break;
default: default:

65
testhal/STM32/STM32F4xx/FSMC_NAND/.cproject Normal file
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@ -0,0 +1,65 @@
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<externalSettings/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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44
testhal/STM32/STM32F4xx/FSMC_NAND/.project Normal file
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@ -0,0 +1,44 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>STM32F4xx-FSMC_NAND</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F4_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
</link>
</linkedResources>
<variableList>
<variable>
<name>CHIBIOS</name>
<value>file:/home/barthess/projects/chibios-svn</value>
</variable>
</variableList>
</projectDescription>

23
testhal/STM32/STM32F4xx/FSMC_NAND/main.c
View File

@ -51,6 +51,8 @@
****************************************************************************** ******************************************************************************
*/ */
#define USE_KILL_BLOCK_TEST FALSE
#define EMCNAND_TIME_SET ((uint32_t) 2) //(8nS) #define EMCNAND_TIME_SET ((uint32_t) 2) //(8nS)
#define EMCNAND_TIME_WAIT ((uint32_t) 6) //(30nS) #define EMCNAND_TIME_WAIT ((uint32_t) 6) //(30nS)
#define EMCNAND_TIME_HOLD ((uint32_t) 1) //(5nS) #define EMCNAND_TIME_HOLD ((uint32_t) 1) //(5nS)
@ -69,8 +71,6 @@
#define NAND_STATUS_READY ((uint8_t)1 << 6) #define NAND_STATUS_READY ((uint8_t)1 << 6)
#define NAND_STATUS_NOT_RPOTECTED ((uint8_t)1 << 7) #define NAND_STATUS_NOT_RPOTECTED ((uint8_t)1 << 7)
#define EMCNAND_USE_KILL_TEST TRUE
/* /*
****************************************************************************** ******************************************************************************
* EXTERNS * EXTERNS
@ -82,9 +82,11 @@
* PROTOTYPES * PROTOTYPES
****************************************************************************** ******************************************************************************
*/ */
#if !STM32_EMC_EMCNAND_USE_FSMC_INT
static void ready_isr_enable(void); static void ready_isr_enable(void);
static void ready_isr_disable(void); static void ready_isr_disable(void);
static void nand_ready_cb(EXTDriver *extp, expchannel_t channel); static void nand_ready_cb(EXTDriver *extp, expchannel_t channel);
#endif
/* /*
****************************************************************************** ******************************************************************************
@ -141,6 +143,7 @@ static const EMCNANDConfig nandcfg = {
/** /**
* *
*/ */
#if !STM32_EMC_EMCNAND_USE_FSMC_INT
static const EXTConfig extcfg = { static const EXTConfig extcfg = {
{ {
{EXT_CH_MODE_DISABLED, NULL}, //0 {EXT_CH_MODE_DISABLED, NULL}, //0
@ -168,6 +171,7 @@ static const EXTConfig extcfg = {
{EXT_CH_MODE_DISABLED, NULL}, {EXT_CH_MODE_DISABLED, NULL},
} }
}; };
#endif /* !STM32_EMC_EMCNAND_USE_FSMC_INT */
/* /*
* *
@ -175,7 +179,7 @@ static const EXTConfig extcfg = {
volatile uint32_t IdleCnt = 0; volatile uint32_t IdleCnt = 0;
volatile systime_t T = 0; volatile systime_t T = 0;
#if EMCNAND_USE_KILL_TEST #if USE_KILL_BLOCK_TEST
volatile uint32_t KillCycle = 0; volatile uint32_t KillCycle = 0;
#endif #endif
@ -187,12 +191,12 @@ volatile uint32_t KillCycle = 0;
****************************************************************************** ******************************************************************************
*/ */
#if !STM32_EMC_EMCNAND_USE_FSMC_INT
static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){ static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){
(void)extp; (void)extp;
(void)channel; (void)channel;
#if !STM32_EMC_EMCNAND_USE_FSMC_INT
EMCNANDD1.isr_handler(&EMCNANDD1); EMCNANDD1.isr_handler(&EMCNANDD1);
#endif
} }
static void ready_isr_enable(void) { static void ready_isr_enable(void) {
@ -202,6 +206,7 @@ static void ready_isr_enable(void) {
static void ready_isr_disable(void) { static void ready_isr_disable(void) {
extChannelDisable(&EXTD1, GPIOD_NAND_RB); extChannelDisable(&EXTD1, GPIOD_NAND_RB);
} }
#endif
static void nand_wp_assert(void) { static void nand_wp_assert(void) {
palClearPad(GPIOB, GPIOB_NAND_WP); palClearPad(GPIOB, GPIOB_NAND_WP);
@ -562,7 +567,9 @@ int main(void) {
chSysInit(); chSysInit();
emcStart(&EMCD1, &emccfg); emcStart(&EMCD1, &emccfg);
#if !STM32_EMC_EMCNAND_USE_FSMC_INT
extStart(&EXTD1, &extcfg); extStart(&EXTD1, &extcfg);
#endif
emcnandStart(&EMCNANDD1, &nandcfg); emcnandStart(&EMCNANDD1, &nandcfg);
chThdSleepMilliseconds(4000); chThdSleepMilliseconds(4000);
@ -616,12 +623,6 @@ int main(void) {
while (TRUE) { while (TRUE) {
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
} }
/*warning suppressor */
#if STM32_EMC_EMCNAND_USE_FSMC_INT
(void)ready_isr_enable;
(void)ready_isr_disable;
#endif
} }