diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
index 7a80a1258..572290dd8 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
@@ -148,8 +148,9 @@
   #error "invalid STM32_MSISRANGE value specified"
 #endif
 
+/* Some headers do not have this definition.*/
 #if !defined(RCC_CFGR_SWS_MSI)
-#define RCC_CFGR_SWS_MSI                0U
+#define RCC_CFGR_SWS_MSI            0U
 #endif
 
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.c b/os/hal/ports/STM32/STM32G0xx/hal_lld.c
index 09ea8e6cc..22b71a66c 100644
--- a/os/hal/ports/STM32/STM32G0xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.c
@@ -34,7 +34,7 @@
 
 /**
  * @brief   CMSIS system core clock variable.
- * @note    It is declared in system_stm32l4xx.h.
+ * @note    It is declared in system_stm32g0xx.h.
  */
 uint32_t SystemCoreClock = STM32_HCLK;
 
@@ -47,46 +47,42 @@ uint32_t SystemCoreClock = STM32_HCLK;
 /*===========================================================================*/
 
 /**
- * @brief   Initializes the backup domain.
- * @note    WARNING! Changing RTC clock source impossible without resetting
- *          of the whole BKP domain.
+ * @brief   Resets the backup domain.
  */
-static void hal_lld_backup_domain_init(void) {
+__STATIC_INLINE void bd_reset(void) {
 
   /* Reset BKP domain if different clock source selected.*/
   if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
     /* Backup domain reset.*/
     RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
+    RCC->BDCR = 0U;
   }
+}
 
-#if STM32_LSE_ENABLED
-  /* LSE activation.*/
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                       /* Wait until LSE is stable.    */
-#endif
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing RTC clock source impossible without reset
+ *          of the whole BKP domain.
+ */
+__STATIC_INLINE void bd_init(void) {
+  uint32_t bdcr;
+
+  /* Current settings.*/
+  bdcr = RCC->BDCR;
 
 #if HAL_USE_RTC
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->BDCR |= STM32_RTCSEL;
-
-    /* RTC clock enabled.*/
-    RCC->BDCR |= RCC_BDCR_RTCEN;
+  /* RTC clock enabled.*/
+  if ((bdcr & RCC_BDCR_RTCEN) == 0) {
+    bdcr |= RCC_BDCR_RTCEN;
   }
 #endif /* HAL_USE_RTC */
 
-  /* Low speed output mode.*/
-  RCC->BDCR |= STM32_LSCOSEL;
+  /* Selectors.*/
+  bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK);
+  bdcr |= STM32_RTCSEL | STM32_LSCOSEL;
+
+  /* Final settings.*/
+  RCC->BDCR = bdcr;
 }
 
 /*===========================================================================*/
@@ -104,27 +100,16 @@ static void hal_lld_backup_domain_init(void) {
  */
 void hal_lld_init(void) {
 
-  /* Reset of all peripherals.*/
-  rccResetAHB(~0);
-  rccResetAPBR1(~RCC_APBRSTR1_PWRRST);
-  rccResetAPBR2(~0);
-
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(true);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
   /* DMA subsystems initialization.*/
 #if defined(STM32_DMA_REQUIRED)
   dmaInit();
 #endif
 
+  /* NVIC initialization.*/
+  nvicInit();
+
   /* IRQ subsystem initialization.*/
   irqInit();
-
-  /* Programmable voltage detector settings.*/
-  PWR->CR2 = STM32_PWR_CR2;
 }
 
 /**
@@ -137,76 +122,40 @@ void hal_lld_init(void) {
 void stm32_clock_init(void) {
 
 #if !STM32_NO_INIT
-  /* PWR clock enable.*/
-#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
-  RCC->APBENR1 = RCC_APBENR1_PWREN | RCC_APBENR1_RTCAPBEN;
-#else
-  RCC->APBENR1 = RCC_APBENR1_PWREN;
-#endif
+  /* Reset of all peripherals.*/
+  rccResetAHB(~0);
+  rccResetAPBR1(~0);
+  rccResetAPBR2(~0);
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, false);
+
+  /* PWR clock enable, backup domain made accessible.*/
+  rccEnablePWRInterface(false);
 
   /* Core voltage setup.*/
-  PWR->CR1 = STM32_VOS;
+  PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
   while ((PWR->SR2 & PWR_SR2_VOSF) != 0)    /* Wait until regulator is      */
     ;                                       /* stable.                      */
 
-#if STM32_HSI16_ENABLED
-  /* HSI activation.*/
-  RCC->CR |= RCC_CR_HSION | STM32_HSIDIV;
-  while ((RCC->CR & RCC_CR_HSIRDY) == 0)
-    ;                                       /* Wait until HSI16 is stable.  */
-#endif
+  /* Additional PWR configurations.*/
+  PWR->CR2 = STM32_PWR_CR2;
 
-#if STM32_HSE_ENABLED
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
-#endif
-  /* HSE activation.*/
-  RCC->CR |= RCC_CR_HSEON;
-  while ((RCC->CR & RCC_CR_HSERDY) == 0)
-    ;                                       /* Wait until HSE is stable.    */
-#endif
+  /* Backup domain reset.*/
+  bd_reset();
 
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Wait until LSI is stable.    */
-#endif
+  /* Clocks setup.*/
+  lse_init();
+  lsi_init();
+  hsi16_init();
+  hse_init();
 
-  /* Backup domain access enabled and left open.*/
-  PWR->CR1 |= PWR_CR1_DBP;
+  /* Backup domain initializations.*/
+  bd_init();
 
-#if STM32_LSE_ENABLED
-  /* LSE activation.*/
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                       /* Wait until LSE is stable.    */
-#endif
-
-#if STM32_ACTIVATE_PLL
-  /* PLLM and PLLSRC are common to all PLLs.*/
-  RCC->PLLCFGR = STM32_PLLR    | STM32_PLLREN  |
-                 STM32_PLLQ    | STM32_PLLQEN  |
-                 STM32_PLLP    | STM32_PLLPEN  |
-                 STM32_PLLN    | STM32_PLLM    |
-                 STM32_PLLSRC;
-#endif
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->CR |= RCC_CR_PLLON;
-
-  /* Waiting for PLL lock.*/
-  while ((RCC->CR & RCC_CR_PLLRDY) == 0)
-    ;
-#endif
+  /* PLLs activation, if required.*/
+  pll_init();
 
   /* Other clock-related settings (dividers, MCO etc).*/
   RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE | STM32_HPRE;
@@ -219,7 +168,7 @@ void stm32_clock_init(void) {
                STM32_CECSEL    | STM32_USART2SEL | STM32_USART1SEL |
                STM32_LPUART1SEL;
 
-  /* Set flash WS's for SYSCLK source */
+  /* Set flash WS's for SYSCLK source.*/
   FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
                STM32_FLASHBITS;
   while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
@@ -235,10 +184,6 @@ void stm32_clock_init(void) {
 #endif
 
 #endif /* STM32_NO_INIT */
-
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, true);
 }
 
 /** @} */
diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.h b/os/hal/ports/STM32/STM32G0xx/hal_lld.h
index 4321ca8d7..0abcdf083 100644
--- a/os/hal/ports/STM32/STM32G0xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.h
@@ -68,14 +68,6 @@
 #endif
 /** @} */
 
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSI16CLK          16000000U   /**< 16MHz internal clock.      */
-#define STM32_LSICLK            32000U      /**< Low speed internal clock.  */
-/** @} */
-
 /**
  * @name    PWR_CR1 register bits definitions
  * @{
@@ -142,26 +134,6 @@
 #define STM32_SW_LSI            (3U << 0U)  /**< SYSCLK source is LSI.      */
 #define STM32_SW_LSE            (4U << 0U)  /**< SYSCLK source is LSE.      */
 
-#define STM32_HPRE_MASK         (15U << 8U) /**< HPRE field mask.           */
-#define STM32_HPRE_FIELD(n)     ((n) << 8U) /**< HPRE field value.          */
-#define STM32_HPRE_DIV1         STM32_HPRE_FIELD(0U)
-#define STM32_HPRE_DIV2         STM32_HPRE_FIELD(8U)
-#define STM32_HPRE_DIV4         STM32_HPRE_FIELD(9U)
-#define STM32_HPRE_DIV8         STM32_HPRE_FIELD(10U)
-#define STM32_HPRE_DIV16        STM32_HPRE_FIELD(11U)
-#define STM32_HPRE_DIV64        STM32_HPRE_FIELD(12U)
-#define STM32_HPRE_DIV128       STM32_HPRE_FIELD(13U)
-#define STM32_HPRE_DIV256       STM32_HPRE_FIELD(14U)
-#define STM32_HPRE_DIV512       STM32_HPRE_FIELD(15U)
-
-#define STM32_PPRE_MASK         (7U << 12U)  /**< PPRE field mask.          */
-#define STM32_PPRE_FIELD(n)     ((n) << 12U) /**< PPRE field value.         */
-#define STM32_PPRE_DIV1         STM32_PPRE_FIELD(0U)
-#define STM32_PPRE_DIV2         STM32_PPRE_FIELD(4U)
-#define STM32_PPRE_DIV4         STM32_PPRE_FIELD(5U)
-#define STM32_PPRE_DIV8         STM32_PPRE_FIELD(6U)
-#define STM32_PPRE_DIV16        STM32_PPRE_FIELD(7U)
-
 #define STM32_MCOSEL_MASK       (7U << 24U) /**< MCOSEL field mask.         */
 #define STM32_MCOSEL_NOCLOCK    (0U << 24U) /**< No clock on MCO pin.       */
 #define STM32_MCOSEL_SYSCLK     (1U << 24U) /**< SYSCLK on MCO pin.         */
@@ -708,6 +680,61 @@
 #define STM32_ADCCLK_MAX            350000000
 /** @} */
 
+/**
+ * @name    PLL limits
+ * @{
+ */
+/**
+ * @brief   Maximum PLLM value.
+ */
+#define STM32_PLLM_VALUE_MAX        8
+
+/**
+ * @brief   Minimum PLLM value.
+ */
+#define STM32_PLLM_VALUE_MIN        1
+
+/**
+ * @brief   Maximum PLLN value.
+ */
+#define STM32_PLLN_VALUE_MAX        86
+
+/**
+ * @brief   Minimum PLLN value.
+ */
+#define STM32_PLLN_VALUE_MIN        8
+
+/**
+ * @brief   Maximum PLLR value.
+ */
+#define STM32_PLLR_VALUE_MAX        8
+
+/**
+ * @brief   Minimum PLLR value.
+ */
+#define STM32_PLLR_VALUE_MIN        2
+
+/**
+ * @brief   Maximum PLLQ value.
+ */
+#define STM32_PLLQ_VALUE_MAX        8
+
+/**
+ * @brief   Minimum PLLQ value.
+ */
+#define STM32_PLLQ_VALUE_MIN        2
+
+/**
+ * @brief   Maximum PLLP value.
+ */
+#define STM32_PLLP_VALUE_MAX        32
+
+/**
+ * @brief   Minimum PLLP value.
+ */
+#define STM32_PLLP_VALUE_MIN        2
+/** @} */
+
 /**
  * @name    Flash Wait states
  * @{
@@ -754,64 +781,70 @@
 #error "invalid STM32_VOS value specified"
 #endif
 
+/* Clock handlers.*/
+#include "stm32_lse.inc"
+#include "stm32_lsi.inc"
+#include "stm32_hsi16.inc"
+#include "stm32_hse.inc"
+
 /*
  * HSI16 related checks.
  */
 #if STM32_HSI16_ENABLED
 #else /* !STM32_HSI16_ENABLED */
 
-#if STM32_SW == STM32_SW_HSISYS
-#error "HSI16 not enabled, required by STM32_SW"
-#endif
+  #if STM32_SW == STM32_SW_HSISYS
+    #error "HSI16 not enabled, required by STM32_SW"
+  #endif
 
-#if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
-#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
+  #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+    #error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
+  #endif
 
-/* NOTE: Missing checks on the HSI16 pre-muxes, it is also required for newer
-   L4 devices.*/
+  /* NOTE: Missing checks on the HSI16 pre-muxes, it is also required for newer
+     L4 devices.*/
 
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) ||                                 \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLL) &&                                  \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI16))
-#error "HSI16 not enabled, required by STM32_MCOSEL"
-#endif
+  #if (STM32_MCOSEL == STM32_MCOSEL_HSI16) ||                               \
+      ((STM32_MCOSEL == STM32_MCOSEL_PLL) &&                                \
+       (STM32_PLLSRC == STM32_PLLSRC_HSI16))
+    #error "HSI16 not enabled, required by STM32_MCOSEL"
+  #endif
 
-#if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
-#error "HSI16 not enabled, required by STM32_USART1SEL"
-#endif
-#if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
-#error "HSI16 not enabled, required by STM32_USART2SEL"
-#endif
-#if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
-#error "HSI16 not enabled, required by STM32_LPUART1SEL"
-#endif
+  #if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_USART1SEL"
+  #endif
+  #if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_USART2SEL"
+  #endif
+  #if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_LPUART1SEL"
+  #endif
 
-#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV)
-#error "HSI16 not enabled, required by STM32_CECSEL"
-#endif
+  #if (STM32_CECSEL == STM32_CECSEL_HSI16DIV)
+    #error "HSI16 not enabled, required by STM32_CECSEL"
+  #endif
 
-#if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
-#error "HSI16 not enabled, required by STM32_I2C1SEL"
-#endif
-#if (STM32_I2S1SEL == STM32_I2S1SEL_HSI16)
-#error "HSI16 not enabled, required by STM32_I2S1SEL"
-#endif
+  #if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_I2C1SEL"
+  #endif
+  #if (STM32_I2S1SEL == STM32_I2S1SEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_I2S1SEL"
+  #endif
 
-#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
-#error "HSI16 not enabled, required by STM32_LPTIM1SEL"
-#endif
-#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16)
-#error "HSI16 not enabled, required by STM32_LPTIM2SEL"
-#endif
+  #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_LPTIM1SEL"
+  #endif
+  #if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_LPTIM2SEL"
+  #endif
 
-#if (STM32_RNGSEL == STM32_RNGSEL_HSI16)
-#error "HSI16 not enabled, required by STM32_RNGSEL"
-#endif
+  #if (STM32_RNGSEL == STM32_RNGSEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_RNGSEL"
+  #endif
 
-#if (STM32_ADCSEL == STM32_ADCSEL_HSI16)
-#error "HSI16 not enabled, required by STM32_ADCSEL"
-#endif
+  #if (STM32_ADCSEL == STM32_ADCSEL_HSI16)
+    #error "HSI16 not enabled, required by STM32_ADCSEL"
+  #endif
 
 #endif /* !STM32_HSI16_ENABLED */
 
@@ -819,21 +852,6 @@
  * HSE related checks.
  */
 #if STM32_HSE_ENABLED
-
-  #if STM32_HSECLK == 0
-    #error "HSE frequency not defined"
-  #else /* STM32_HSECLK != 0 */
-    #if defined(STM32_HSE_BYPASS)
-      #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
-        #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
-      #endif
-    #else /* !defined(STM32_HSE_BYPASS) */
-      #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-        #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-      #endif
-    #endif /* !defined(STM32_HSE_BYPASS) */
-  #endif /* STM32_HSECLK != 0 */
-
 #else /* !STM32_HSE_ENABLED */
 
   #if STM32_SW == STM32_SW_HSE
@@ -880,15 +898,6 @@
  * LSE related checks.
  */
 #if STM32_LSE_ENABLED
-
-  #if (STM32_LSECLK == 0)
-    #error "LSE frequency not defined"
-  #endif
-
-  #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-    #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-  #endif
-
 #else /* !STM32_LSE_ENABLED */
 
   #if STM32_RTCSEL == STM32_RTCSEL_LSE
@@ -909,59 +918,49 @@
  * @brief   STM32_HSIDIV field.
  */
 #if (STM32_HSIDIV_VALUE == 1) || defined(__DOXYGEN__)
-#define STM32_HSIDIV                STM32_HSIDIV_1
-#elif STM32_HSIDIV_VALUE == 2
-#define STM32_HSIDIV                STM32_HSIDIV_2
-#elif STM32_HSIDIV_VALUE == 4
-#define STM32_HSIDIV                STM32_HSIDIV_4
-#elif STM32_HSIDIV_VALUE == 8
-#define STM32_HSIDIV                STM32_HSIDIV_8
-#elif STM32_HSIDIV_VALUE == 16
-#define STM32_HSIDIV                STM32_HSIDIV_16
-#elif STM32_HSIDIV_VALUE == 32
-#define STM32_HSIDIV                STM32_HSIDIV_32
-#elif STM32_HSIDIV_VALUE == 64
-#define STM32_HSIDIV                STM32_HSIDIV_64
-#elif STM32_HSIDIV_VALUE == 128
-#define STM32_HSIDIV                STM32_HSIDIV_128
-#else
-#error "invalid STM32_HSIDIV_VALUE value specified"
-#endif
+  #define STM32_HSIDIV              STM32_HSIDIV_1
+
+#elif STM32_HSIDIV_VALUE == 2
+  #define STM32_HSIDIV              STM32_HSIDIV_2
+
+#elif STM32_HSIDIV_VALUE == 4
+  #define STM32_HSIDIV              STM32_HSIDIV_4
+
+#elif STM32_HSIDIV_VALUE == 8
+  #define STM32_HSIDIV              STM32_HSIDIV_8
+
+#elif STM32_HSIDIV_VALUE == 16
+  #define STM32_HSIDIV              STM32_HSIDIV_16
+
+#elif STM32_HSIDIV_VALUE == 32
+  #define STM32_HSIDIV              STM32_HSIDIV_32
+
+#elif STM32_HSIDIV_VALUE == 64
+  #define STM32_HSIDIV              STM32_HSIDIV_64
+
+#elif STM32_HSIDIV_VALUE == 128
+  #define STM32_HSIDIV              STM32_HSIDIV_128
 
-/**
- * @brief   STM32_PLLM field.
- */
-#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) ||                 \
-    defined(__DOXYGEN__)
-#define STM32_PLLM                  ((STM32_PLLM_VALUE - 1) << 4)
 #else
-#error "invalid STM32_PLLM_VALUE value specified"
+  #error "invalid STM32_HSIDIV_VALUE value specified"
 #endif
 
 /**
  * @brief   PLL input clock frequency.
  */
 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)
+  #define STM32_PLLCLKIN            (STM32_HSECLK / STM32_PLLM_VALUE)
 
 #elif STM32_PLLSRC == STM32_PLLSRC_HSI16
-#define STM32_PLLCLKIN              (STM32_HSI16CLK / STM32_PLLM_VALUE)
+  #define STM32_PLLCLKIN            (STM32_HSI16CLK / STM32_PLLM_VALUE)
 
 #elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
-#define STM32_PLLCLKIN              0
+  #define STM32_PLLCLKIN            0
 
 #else
 #error "invalid STM32_PLLSRC value specified"
 #endif
 
-/*
- * PLL input frequency range check.
- */
-#if (STM32_PLLCLKIN != 0) &&                                                \
-    ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
 /*
  * PLL enable check.
  */
@@ -973,57 +972,13 @@
     (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) ||                               \
     (STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) ||                             \
     defined(__DOXYGEN__)
+  /**
+   * @brief   PLL activation flag.
+   */
+  #define STM32_ACTIVATE_PLL          TRUE
 
-#if STM32_PLLCLKIN == 0
-#error "PLL activation required but no PLL clock selected"
-#endif
-
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
 #else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/**
- * @brief   STM32_PLLN field.
- */
-#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) ||                \
-    defined(__DOXYGEN__)
-#define STM32_PLLN                  (STM32_PLLN_VALUE << 8)
-#else
-#error "invalid STM32_PLLN_VALUE value specified"
-#endif
-
-/**
- * @brief   STM32_PLLR field.
- */
-#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 8)) ||                 \
-    defined(__DOXYGEN__)
-#define STM32_PLLR                  ((STM32_PLLR_VALUE - 1) << 29)
-#else
-#error "invalid STM32_PLLR_VALUE value specified"
-#endif
-
-/**
- * @brief   STM32_PLLQ field.
- */
-#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 8)) ||                 \
-    defined(__DOXYGEN__)
-#define STM32_PLLQ                  ((STM32_PLLQ_VALUE - 1) << 25)
-#else
-#error "invalid STM32_PLLQ_VALUE value specified"
-#endif
-
-/**
- * @brief   STM32_PLLP field.
- */
-#if ((STM32_PLLP_VALUE >= 2) && (STM32_PLLP_VALUE <= 32)) ||                \
-    defined(__DOXYGEN__)
-#define STM32_PLLP                  ((STM32_PLLP_VALUE - 1) << 17)
-#else
-#error "invalid STM32_PLLP_VALUE value specified"
+  #define STM32_ACTIVATE_PLL          FALSE
 #endif
 
 /**
@@ -1060,57 +1015,8 @@
 #define STM32_PLLPEN                (0 << 16)
 #endif
 
-/**
- * @brief   PLL VCO frequency.
- */
-#define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLN_VALUE)
-
-/*
- * PLL VCO frequency range check.
- */
-#if STM32_ACTIVATE_PLL &&                                                   \
-    ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
-#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
-#endif
-
-/**
- * @brief   PLL R output clock frequency.
- */
-#define STM32_PLL_R_CLKOUT          (STM32_PLLVCO / STM32_PLLR_VALUE)
-
-/**
- * @brief   PLL Q output clock frequency.
- */
-#define STM32_PLL_Q_CLKOUT          (STM32_PLLVCO / STM32_PLLQ_VALUE)
-
-/**
- * @brief   PLL P output clock frequency.
- */
-#define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLP_VALUE)
-
-/*
- * PLL-R output frequency range check.
- */
-#if STM32_ACTIVATE_PLL &&                                                   \
-    ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
-#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
-#endif
-
-/*
- * PLL-Q output frequency range check.
- */
-#if STM32_ACTIVATE_PLL &&                                                   \
-    ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
-#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
-#endif
-
-/*
- * PLL-P output frequency range check.
- */
-#if STM32_ACTIVATE_PLL &&                                                   \
-    ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
-#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
-#endif
+/* Inclusion of PLL-related checks and calculations.*/
+#include <stm32_pll_v2.inc>
 
 /**
  * @brief   HSISYS clock frequency.
@@ -1121,94 +1027,30 @@
  * @brief   System clock source.
  */
 #if STM32_NO_INIT || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_HSISYSCLK
+  #define STM32_SYSCLK              STM32_HSISYSCLK
 
 #elif (STM32_SW == STM32_SW_HSISYS)
-#define STM32_SYSCLK                STM32_HSISYSCLK
+  #define STM32_SYSCLK              STM32_HSISYSCLK
 
 #elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
+  #define STM32_SYSCLK              STM32_HSECLK
 
 #elif (STM32_SW == STM32_SW_PLLRCLK)
-#define STM32_SYSCLK                STM32_PLL_R_CLKOUT
+  #define STM32_SYSCLK              STM32_PLL_R_CLKOUT
 
 #elif (STM32_SW == STM32_SW_LSI)
-#define STM32_SYSCLK                STM32_LSICLK
+  #define STM32_SYSCLK              STM32_LSICLK
 
 #elif (STM32_SW == STM32_SW_LSE)
-#define STM32_SYSCLK                STM32_LSECLK
+  #define STM32_SYSCLK              STM32_LSECLK
 
 #else
 #error "invalid STM32_SW value specified"
 #endif
 
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/*
- * AHB frequency check.
- */
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB frequency.
- */
-#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK                  (STM32_HCLK / 1)
-
-#elif STM32_PPRE == STM32_PPRE_DIV2
-#define STM32_PCLK                  (STM32_HCLK / 2)
-
-#elif STM32_PPRE == STM32_PPRE_DIV4
-#define STM32_PCLK                  (STM32_HCLK / 4)
-
-#elif STM32_PPRE == STM32_PPRE_DIV8
-#define STM32_PCLK                  (STM32_HCLK / 8)
-
-#elif STM32_PPRE == STM32_PPRE_DIV16
-#define STM32_PCLK                  (STM32_HCLK / 16)
-
-#else
-#error "invalid STM32_PPRE value specified"
-#endif
+/* Bus handlers.*/
+#include "stm32_ahb.inc"
+#include "stm32_apb.inc"
 
 /*
  * Compatibility definitions.
@@ -1216,186 +1058,200 @@
 #define STM32_PCLK1                 STM32_PCLK
 #define STM32_PCLK2                 STM32_PCLK
 
-/*
- * APB frequency check.
- */
-#if STM32_PCLK > STM32_PCLK_MAX
-#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
-#endif
-
 /**
  * @brief   MCO divider clock frequency.
  */
 #if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_MCODIVCLK             0
+  #define STM32_MCODIVCLK           0
 
 #elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
-#define STM32_MCODIVCLK             STM32_SYSCLK
+  #define STM32_MCODIVCLK           STM32_SYSCLK
 
 #elif STM32_MCOSEL == STM32_MCOSEL_HSI16
-#define STM32_MCODIVCLK             STM32_HSI16CLK
+  #define STM32_MCODIVCLK           STM32_HSI16CLK
 
 #elif STM32_MCOSEL == STM32_MCOSEL_HSE
-#define STM32_MCODIVCLK             STM32_HSECLK
+  #define STM32_MCODIVCLK           STM32_HSECLK
 
 #elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK
-#define STM32_MCODIVCLK             STM32_PLL_R_CLKOUT
+  #define STM32_MCODIVCLK           STM32_PLL_R_CLKOUT
 
 #elif STM32_MCOSEL == STM32_MCOSEL_LSI
-#define STM32_MCODIVCLK             STM32_LSICLK
+  #define STM32_MCODIVCLK           STM32_LSICLK
 
 #elif STM32_MCOSEL == STM32_MCOSEL_LSE
-#define STM32_MCODIVCLK             STM32_LSECLK
+  #define STM32_MCODIVCLK           STM32_LSECLK
 
 #else
-#error "invalid STM32_MCOSEL value specified"
+  #error "invalid STM32_MCOSEL value specified"
 #endif
 
 /**
  * @brief   MCO output pin clock frequency.
  */
 #if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCOCLK                STM32_MCODIVCLK
+  #define STM32_MCOCLK              STM32_MCODIVCLK
 
 #elif STM32_MCOPRE == STM32_MCOPRE_DIV2
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 2)
+  #define STM32_MCOCLK              (STM32_MCODIVCLK / 2)
 
 #elif STM32_MCOPRE == STM32_MCOPRE_DIV4
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 4)
+  #define STM32_MCOCLK              (STM32_MCODIVCLK / 4)
 
 #elif STM32_MCOPRE == STM32_MCOPRE_DIV8
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 8)
+  #define STM32_MCOCLK              (STM32_MCODIVCLK / 8)
 
 #elif STM32_MCOPRE == STM32_MCOPRE_DIV16
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 16)
+  #define STM32_MCOCLK              (STM32_MCODIVCLK / 16)
 
 #elif STM32_MCOPRE == STM32_MCOPRE_DIV32
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 32)
+  #define STM32_MCOCLK              (STM32_MCODIVCLK / 32)
 
 #elif STM32_MCOPRE == STM32_MCOPRE_DIV64
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 64)
+  #define STM32_MCOCLK              (STM32_MCODIVCLK / 64)
 
 #elif STM32_MCOPRE == STM32_MCOPRE_DIV128
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 128)
+  #define STM32_MCOCLK              (STM32_MCODIVCLK / 128)
 
 #else
-#error "invalid STM32_MCOPRE value specified"
+  #error "invalid STM32_MCOPRE value specified"
 #endif
 
 /**
  * @brief   RTC clock frequency.
  */
 #if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                0
+  #define STM32_RTCCLK              0
 
 #elif STM32_RTCSEL == STM32_RTCSEL_LSE
-#define STM32_RTCCLK                STM32_LSECLK
+  #define STM32_RTCCLK              STM32_LSECLK
 
 #elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
+  #define STM32_RTCCLK              STM32_LSICLK
 
 #elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 32)
+  #define STM32_RTCCLK              (STM32_HSECLK / 32)
 
 #else
-#error "invalid STM32_RTCSEL value specified"
+  #error "invalid STM32_RTCSEL value specified"
 #endif
 
 /**
  * @brief   USART1 clock frequency.
  */
 #if (STM32_USART1SEL == STM32_USART1SEL_PCLK) || defined(__DOXYGEN__)
-#define STM32_USART1CLK             STM32_PCLK
+  #define STM32_USART1CLK           STM32_PCLK
+
 #elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
-#define STM32_USART1CLK             STM32_SYSCLK
+  #define STM32_USART1CLK           STM32_SYSCLK
+
 #elif STM32_USART1SEL == STM32_USART1SEL_HSI16
-#define STM32_USART1CLK             STM32_HSI16CLK
+  #define STM32_USART1CLK           STM32_HSI16CLK
+
 #elif STM32_USART1SEL == STM32_USART1SEL_LSE
-#define STM32_USART1CLK             STM32_LSECLK
+  #define STM32_USART1CLK           STM32_LSECLK
+
 #else
-#error "invalid source selected for USART1 clock"
+  #error "invalid source selected for USART1 clock"
 #endif
 
 /**
  * @brief   USART2 clock frequency.
  */
 #if (STM32_USART2SEL == STM32_USART2SEL_PCLK) || defined(__DOXYGEN__)
-#define STM32_USART2CLK             STM32_PCLK
+  #define STM32_USART2CLK           STM32_PCLK
+
 #elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
-#define STM32_USART2CLK             STM32_SYSCLK
+  #define STM32_USART2CLK           STM32_SYSCLK
+
 #elif STM32_USART2SEL == STM32_USART2SEL_HSI16
-#define STM32_USART2CLK             STM32_HSI16CLK
+  #define STM32_USART2CLK           STM32_HSI16CLK
+
 #elif STM32_USART2SEL == STM32_USART2SEL_LSE
-#define STM32_USART2CLK             STM32_LSECLK
+  #define STM32_USART2CLK           STM32_LSECLK
+
 #else
-#error "invalid source selected for USART2 clock"
+  #error "invalid source selected for USART2 clock"
 #endif
 
 /**
  * @brief   USART3 frequency.
  */
-#define STM32_USART3CLK            STM32_PCLK
+#define STM32_USART3CLK             STM32_PCLK
 
 /**
  * @brief   UART4 frequency.
  */
-#define STM32_UART4CLK             STM32_PCLK
+#define STM32_UART4CLK              STM32_PCLK
 
 /**
  * @brief   UART5 frequency.
  */
-#define STM32_UART5CLK             STM32_PCLK
+#define STM32_UART5CLK              STM32_PCLK
 
 /**
  * @brief   LPUART1 clock frequency.
  */
 #if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK) || defined(__DOXYGEN__)
-#define STM32_LPUART1CLK            STM32_PCLK
+  #define STM32_LPUART1CLK          STM32_PCLK
+
 #elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
-#define STM32_LPUART1CLK            STM32_SYSCLK
+  #define STM32_LPUART1CLK          STM32_SYSCLK
+
 #elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
-#define STM32_LPUART1CLK            STM32_HSI16CLK
+  #define STM32_LPUART1CLK          STM32_HSI16CLK
+
 #elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
-#define STM32_LPUART1CLK            STM32_LSECLK
+  #define STM32_LPUART1CLK          STM32_LSECLK
+
 #else
-#error "invalid source selected for LPUART1 clock"
+  #error "invalid source selected for LPUART1 clock"
 #endif
 
 /**
  * @brief   CEC clock frequency.
  */
 #if (STM32_CECSEL == STM32_CECSEL_HSI16DIV) || defined(__DOXYGEN__)
-#define STM32_CECCLK                (STM32_HSI16CLK / 448)
+  #define STM32_CECCLK              (STM32_HSI16CLK / 448)
+
 #elif STM32_CECSEL == STM32_CECSEL_LSE
-#define STM32_CECCLK                STM32_LSECLK
+  #define STM32_CECCLK              STM32_LSECLK
+
 #else
-#error "invalid source selected for CEC clock"
+  #error "invalid source selected for CEC clock"
 #endif
 
 /**
  * @brief   I2C1 clock frequency.
  */
 #if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK) || defined(__DOXYGEN__)
-#define STM32_I2C1CLK               STM32_PCLK
+  #define STM32_I2C1CLK             STM32_PCLK
+
 #elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
-#define STM32_I2C1CLK               STM32_SYSCLK
+  #define STM32_I2C1CLK             STM32_SYSCLK
+
 #elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
-#define STM32_I2C1CLK               STM32_HSI16CLK
+  #define STM32_I2C1CLK             STM32_HSI16CLK
+
 #else
-#error "invalid source selected for I2C1 clock"
+  #error "invalid source selected for I2C1 clock"
 #endif
 
 /**
  * @brief   I2S1 clock frequency.
  */
 #if (STM32_I2S1SEL == STM32_I2S1SEL_SYSCLK) || defined(__DOXYGEN__)
-#define STM32_I2S1CLK               STM32_SYSCLK
+  #define STM32_I2S1CLK             STM32_SYSCLK
+
 #elif STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK
-#define STM32_I2S1CLK               STM32_PLL_P_CLKOUT
+  #define STM32_I2S1CLK             STM32_PLL_P_CLKOUT
+
 #elif STM32_I2S1SEL == STM32_I2S1SEL_HSI16
-#define STM32_I2S1CLK               STM32_HSI16CLK
+  #define STM32_I2S1CLK             STM32_HSI16CLK
+
 #elif STM32_I2S1SEL == STM32_I2S1SEL_CKIN
-#define STM32_I2S1CLK               0 /* Unknown, would require a board value */
+  #define STM32_I2S1CLK             0 /* Unknown, would require a board value */
+
 #else
 #error "invalid source selected for I2S1 clock"
 #endif
@@ -1404,13 +1260,17 @@
  * @brief   LPTIM1 clock frequency.
  */
 #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK) || defined(__DOXYGEN__)
-#define STM32_LPTIM1CLK             STM32_PCLK
+  #define STM32_LPTIM1CLK           STM32_PCLK
+
 #elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
-#define STM32_LPTIM1CLK             STM32_LSICLK
+  #define STM32_LPTIM1CLK           STM32_LSICLK
+
 #elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
-#define STM32_LPTIM1CLK             STM32_HSI16CLK
+  #define STM32_LPTIM1CLK           STM32_HSI16CLK
+
 #elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
-#define STM32_LPTIM1CLK             STM32_LSECLK
+  #define STM32_LPTIM1CLK           STM32_LSECLK
+
 #else
 #error "invalid source selected for LPTIM1 clock"
 #endif
@@ -1419,13 +1279,17 @@
  * @brief   LPTIM2 clock frequency.
  */
 #if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK) || defined(__DOXYGEN__)
-#define STM32_LPTIM2CLK             STM32_PCLK
+  #define STM32_LPTIM2CLK           STM32_PCLK
+
 #elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
-#define STM32_LPTIM2CLK             STM32_LSICLK
+  #define STM32_LPTIM2CLK           STM32_LSICLK
+
 #elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
-#define STM32_LPTIM2CLK             STM32_HSI16CLK
+  #define STM32_LPTIM2CLK           STM32_HSI16CLK
+
 #elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
-#define STM32_LPTIM2CLK             STM32_LSECLK
+  #define STM32_LPTIM2CLK           STM32_LSECLK
+
 #else
 #error "invalid source selected for LPTIM2 clock"
 #endif
@@ -1434,28 +1298,37 @@
  * @brief   RNGDIV field.
  */
 #if (STM32_RNGDIV_VALUE == 1) || defined(__DOXYGEN__)
-#define STM32_RNGDIV                (0U << 28U)
+  #define STM32_RNGDIV              (0U << 28U)
+
 #elif STM32_RNGDIV_VALUE == 2
-#define STM32_RNGDIV                (1U << 28U)
+  #define STM32_RNGDIV              (1U << 28U)
+
 #elif STM32_RNGDIV_VALUE == 4
-#define STM32_RNGDIV                (2U << 28U)
+  #define STM32_RNGDIV              (2U << 28U)
+
 #elif STM32_RNGDIV_VALUE == 8
-#define STM32_RNGDIV                (3U << 28U)
+  #define STM32_RNGDIV              (3U << 28U)
+
 #else
-#error "invalid STM32_RNGDIV_VALUE value specified"
+  #error "invalid STM32_RNGDIV_VALUE value specified"
 #endif
 
 /**
  * @brief   RNG clock frequency.
  */
 #if (STM32_RNGSEL == STM32_RNGSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_RNGCLK                0
+  #define STM32_RNGCLK              0
+
 #elif STM32_RNGSEL == STM32_RNGSEL_HSI16
-#define STM32_RNGCLK                (STM32_HSI16CLK / STM32_RNGDIV_VALUE)
+  #define STM32_RNGCLK              (STM32_HSI16CLK / STM32_RNGDIV_VALUE)
+
 #elif STM32_RNGSEL == STM32_RNGSEL_SYSCLK
-#define STM32_RNGCLK                (STM32_SYSCLK / STM32_RNGDIV_VALUE)
+  #define STM32_RNGCLK              (STM32_SYSCLK / STM32_RNGDIV_VALUE)
+
 #elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK
-#define STM32_RNGCLK                (STM32_PLL_Q_CLKOUT / STM32_RNGDIV_VALUE)
+  #define STM32_RNGCLK              (STM32_PLL_Q_CLKOUT / STM32_RNGDIV_VALUE)
+
+
 #else
 #error "invalid source selected for RNG clock"
 #endif
@@ -1464,42 +1337,50 @@
  * @brief   ADC clock frequency.
  */
 #if (STM32_ADCSEL == STM32_ADCSEL_SYSCLK) || defined(__DOXYGEN__)
-#define STM32_ADCCLK                STM32_SYSCLK
+  #define STM32_ADCCLK              STM32_SYSCLK
+
 #elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK
-#define STM32_ADCCLK                STM32_PLL_P_CLKOUT
+  #define STM32_ADCCLK              STM32_PLL_P_CLKOUT
+
 #elif STM32_ADCSEL == STM32_ADCSEL_HSI16
-#define STM32_ADCCLK                STM32_HSI16CLK
+  #define STM32_ADCCLK              STM32_HSI16CLK
+
 #else
-#error "invalid source selected for ADC clock"
+  #error "invalid source selected for ADC clock"
 #endif
 
 /**
  * @brief   TIMPCLK clock frequency.
  */
 #if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMPCLK               (STM32_PCLK * 1)
+  #define STM32_TIMPCLK             (STM32_PCLK * 1)
+
 #else
-#define STM32_TIMPCLK               (STM32_PCLK * 2)
+  #define STM32_TIMPCLK             (STM32_PCLK * 2)
 #endif
 
 /**
  * @brief   TIM1 clock frequency.
  */
 #if (STM32_TIM1SEL == STM32_TIM1SEL_TIMPCLK) || defined(__DOXYGEN__)
-#define STM32_TIM1CLK               STM32_TIMPCLK
+  #define STM32_TIM1CLK             STM32_TIMPCLK
+
 #elif STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK
-#define STM32_TIM1CLK               STM32_PLL_Q_CLKOUT
+  #define STM32_TIM1CLK             STM32_PLL_Q_CLKOUT
+
 #else
-#error "invalid source selected for TIM1 clock"
+  #error "invalid source selected for TIM1 clock"
 #endif
 
 /**
  * @brief   TIM15 clock frequency.
  */
 #if (STM32_TIM15SEL == STM32_TIM15SEL_TIMPCLK) || defined(__DOXYGEN__)
-#define STM32_TIM15CLK              STM32_TIMPCLK
+  #define STM32_TIM15CLK            STM32_TIMPCLK
+
 #elif STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK
-#define STM32_TIM15CLK              STM32_PLL_Q_CLKOUT
+  #define STM32_TIM15CLK            STM32_PLL_Q_CLKOUT
+
 #else
 #error "invalid source selected for TIM15 clock"
 #endif
@@ -1518,16 +1399,16 @@
  * @brief   Flash settings.
  */
 #if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0
+  #define STM32_FLASHBITS           0
 
 #elif STM32_HCLK <= STM32_1WS_THRESHOLD
-#define STM32_FLASHBITS             FLASH_ACR_LATENCY_0
+  #define STM32_FLASHBITS           FLASH_ACR_LATENCY_0
 
 #elif STM32_HCLK <= STM32_2WS_THRESHOLD
-#define STM32_FLASHBITS             FLASH_ACR_LATENCY_1
+  #define STM32_FLASHBITS           FLASH_ACR_LATENCY_1
 
 #else
-#define STM32_FLASHBITS             (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)
+  #define STM32_FLASHBITS           (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)
 #endif
 
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32G0xx/platform.mk b/os/hal/ports/STM32/STM32G0xx/platform.mk
index b623ec10d..089625043 100644
--- a/os/hal/ports/STM32/STM32G0xx/platform.mk
+++ b/os/hal/ports/STM32/STM32G0xx/platform.mk
@@ -32,6 +32,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h
index b5b3e5812..d6dc2d602 100644
--- a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h
@@ -84,6 +84,23 @@
 #define STM32_HAS_CRYP1                     FALSE
 #endif
 
+/* RCC attributes (common).*/
+#define STM32_RCC_HAS_HSI16                 TRUE
+#define STM32_RCC_HAS_HSI48                 FALSE
+#define STM32_RCC_HAS_MSI                   FALSE
+#define STM32_RCC_HAS_LSI                   TRUE
+#define STM32_RCC_HAS_LSI_PRESCALER         FALSE
+#define STM32_RCC_HAS_LSE                   TRUE
+#define STM32_RCC_HAS_HSE                   TRUE
+
+#define STM32_RCC_HAS_PLL                   TRUE
+#define STM32_RCC_PLL_HAS_P                 TRUE
+/*#define STM32_RCC_PLL_HAS_Q                 TRUE*/ /* Varies, see below.*/
+#define STM32_RCC_PLL_HAS_R                 TRUE
+
+#define STM32_RCC_HAS_PLLSAI1               FALSE
+#define STM32_RCC_HAS_PLLSAI2               FALSE
+
 /* SPI attributes. */
 #define STM32_HAS_SPIR                      FALSE
 
@@ -161,6 +178,9 @@
 /* QUADSPI attributes.*/
 #define STM32_HAS_QUADSPI1                  FALSE
 
+/* RCC attributes.*/
+#define STM32_RCC_PLL_HAS_Q                 FALSE
+
 /* SDMMC attributes.*/
 #define STM32_HAS_SDMMC1                    FALSE
 #define STM32_HAS_SDMMC2                    FALSE
@@ -339,6 +359,9 @@
 /* QUADSPI attributes.*/
 #define STM32_HAS_QUADSPI1                  FALSE
 
+/* RCC attributes.*/
+#define STM32_RCC_PLL_HAS_Q                 TRUE
+
 /* SDMMC attributes.*/
 #define STM32_HAS_SDMMC1                    FALSE
 #define STM32_HAS_SDMMC2                    FALSE
diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
index 14957b33a..eb03db1ed 100644
--- a/os/hal/ports/STM32/STM32G4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
@@ -133,6 +133,10 @@ void stm32_clock_init(void) {
   rccResetAPB1R2(~0);
   rccResetAPB2(~0);
 
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
+
   /* PWR clock enable.*/
 #if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
   rccEnableAPB1R1(RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN, false)
@@ -180,7 +184,7 @@ void stm32_clock_init(void) {
                 STM32_USART1SEL;
   RCC->CCIPR2 = STM32_QSPISEL    | STM32_I2C4SEL;
 
-  /* Set flash WS's for SYSCLK source */
+  /* Set flash WS's for SYSCLK source.*/
   FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN   |
                FLASH_ACR_PRFTEN   | STM32_FLASHBITS;
   while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
@@ -195,10 +199,6 @@ void stm32_clock_init(void) {
     ;
 #endif
 
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
-
 #endif /* STM32_NO_INIT */
 }
 
diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
index 190597627..0edb4bafa 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
@@ -136,13 +136,13 @@ void stm32_clock_init(void) {
   FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
                STM32_MSI_FLASHBITS;
 
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(false);
-
   /* SYSCFG clock enabled here because it is a multi-functional unit shared
      among multiple drivers.*/
   rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
 
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(false);
+
   /* Core voltage setup, backup domain access enabled and left open.*/
   PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
   while ((PWR->SR2 & PWR_SR2_VOSF) != 0)    /* Wait until regulator is      */
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
index c6f16a5f1..7034736f2 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -136,13 +136,13 @@ void stm32_clock_init(void) {
   FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
                STM32_MSI_FLASHBITS;
 
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(false);
-
   /* SYSCFG clock enabled here because it is a multi-functional unit shared
      among multiple drivers.*/
   rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
 
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(false);
+
   /* Core voltage setup, backup domain access enabled and left open.*/
   PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
   while ((PWR->SR2 & PWR_SR2_VOSF) != 0)    /* Wait until regulator is      */
diff --git a/os/hal/ports/STM32/STM32L5xx/hal_lld.c b/os/hal/ports/STM32/STM32L5xx/hal_lld.c
index 4a5e22ec0..bbf7b9d7c 100644
--- a/os/hal/ports/STM32/STM32L5xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L5xx/hal_lld.c
@@ -158,6 +158,10 @@ void stm32_clock_init(void) {
   secflags = RCC->SECSR;
 #endif
 
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
+
   /* PWR clock enable.*/
 #if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
   RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
@@ -268,10 +272,6 @@ void stm32_clock_init(void) {
   /* Cache enable.*/
   icache_init();
 
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
-
 #endif /* STM32_NO_INIT */
 }