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Invalidate D Cache and TLB before setup MMU 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11076 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
isiora 2017-11-25 17:24:10 +00:00
parent 1d3f02c7ef
commit 70c245e116
1 changed files with 10 additions and 3 deletions
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13
os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c
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@ -98,6 +98,13 @@ static uint32_t mmuTable[4096] CC_ALIGN(16384);
void __mmu_init(void) { void __mmu_init(void) {
uint32_t pm; uint32_t pm;
/*
* Invalidate L1 D Cache if it was disabled
*/
pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk) == 0) {
__L1C_CleanInvalidateCache(DCISW_INVALIDATE);
}
/* /*
* Default, undefined regions * Default, undefined regions
*/ */
@ -327,9 +334,10 @@ void __mmu_init(void) {
TTE_SECT_EXE_NEVER | TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT; TTE_SECT_S | TTE_TYPE_SECT;
/* /*
* Invalidate L1 I/D cache * Invalidate TLB and L1 I cache
* Enable caches and MMU * Enable caches and MMU
*/ */
MMU_InvalidateTLB();
__set_TTBR0((uint32_t)mmuTable|0x5B); __set_TTBR0((uint32_t)mmuTable|0x5B);
__set_DACR(0xC0000000); __set_DACR(0xC0000000);
__DSB(); __DSB();
@ -350,11 +358,10 @@ void __mmu_init(void) {
if ((pm & SCTLR_M_Msk) == 0) if ((pm & SCTLR_M_Msk) == 0)
__set_SCTLR(pm | SCTLR_M_Msk); __set_SCTLR(pm | SCTLR_M_Msk);
/* /*
* L1 D cache clean, invalidate and enable * L1 D cache enable
*/ */
pm = __get_SCTLR(); pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk) == 0) { if ((pm & SCTLR_C_Msk) == 0) {
__L1C_CleanInvalidateCache(DCISW_CLEAN_AND_INV);
__set_SCTLR(pm | SCTLR_C_Msk); __set_SCTLR(pm | SCTLR_C_Msk);
} }
} }