From 758ee812ec1008023e1a826a00a5ef109bde3d26 Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Wed, 18 Mar 2020 15:43:05 +0000 Subject: [PATCH] Updated STM32L5 CMSIS header git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13452 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/common/ext/ST/STM32L5xx/stm32l552xx.h | 120 +++++++++++++++++------ os/common/ext/ST/STM32L5xx/stm32l562xx.h | 112 ++++++++++++++++----- os/common/ext/ST/STM32L5xx/stm32l5xx.h | 2 +- 3 files changed, 179 insertions(+), 55 deletions(-) diff --git a/os/common/ext/ST/STM32L5xx/stm32l552xx.h b/os/common/ext/ST/STM32L5xx/stm32l552xx.h index 831f8d6c2..4179c2f1b 100644 --- a/os/common/ext/ST/STM32L5xx/stm32l552xx.h +++ b/os/common/ext/ST/STM32L5xx/stm32l552xx.h @@ -207,9 +207,7 @@ typedef enum #define __SAUREGION_PRESENT 1U /* SAU regions present */ #define __MPU_PRESENT 1U /* MPU present */ #define __VTOR_PRESENT 1U /* VTOR present */ -/* CHIBIOS FIX */ -//#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /* FPU present */ #define __DSP_PRESENT 1U /* DSP extension present */ @@ -446,7 +444,7 @@ typedef struct } DFSDM_Channel_TypeDef; /** - * @brief Debug MCU - TODO review for STM32L5 to be done + * @brief Debug MCU */ typedef struct { @@ -454,7 +452,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ } DBGMCU_TypeDef; /** @@ -1300,9 +1298,7 @@ typedef struct #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ -/* CHIBIOS FIX */ -//#elif (__ARMCC_VERSION >= 6010050) -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#elif (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ @@ -1673,22 +1669,88 @@ typedef struct #define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) #define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) -/* Debug MCU registers base address */ +/*!< Debug MCU registers base address */ #define DBGMCU_BASE (0xE0044000UL) #define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ #define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */ -/* Internal Flash size */ +/*!< Internal Flash size */ #define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \ ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \ (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U))) -/* OTP Area */ +/*!< OTP Area */ #define OTP_BASE (0x0BFA0000UL) #define OTP_SIZE (0x200U) +/*!< Bootloader Area */ +#define BL_ID_ADDR (0x0BF97FFEUL) /*!< Bootloader ID address */ +#define BL_ID (*(uint8_t*)BL_ID_ADDR) /*!< Bootloader ID */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF97F40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF97FFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x0BF97F40UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL90; /*!< RSSLIB Bootloader ID90 Close and exit HDP Address offset: 0x20 */ + __IM uint32_t Reserved2; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL91; /*!< RSSLIB Bootloader ID91 Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + /** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */ @@ -4514,21 +4576,21 @@ typedef struct #define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk /******************** Bit definition for DBGMCU_APB2FZ register ************/ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U) -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U) -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ -#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U) -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ -#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U) -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ -#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ -#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /******************************************************************************/ /* */ @@ -16298,13 +16360,11 @@ typedef struct /****************** Bit definition for SYSCFG_RSSCMDR register **************/ #define SYSCFG_RSSCMDR_RSSCMD_Pos (0U) -#if defined(USE_CUT2_0) #define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ -#else -#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */ -#endif #define SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk /*!< RSS commands */ +#define SYSCFG_RSSCMDR_RSSCMD_BOOTLOADER ((uint16_t)0x01C0U) + /*****************************************************************************/ /* */ /* Global TrustZone Control */ diff --git a/os/common/ext/ST/STM32L5xx/stm32l562xx.h b/os/common/ext/ST/STM32L5xx/stm32l562xx.h index 0c7fb72ed..df6de96af 100644 --- a/os/common/ext/ST/STM32L5xx/stm32l562xx.h +++ b/os/common/ext/ST/STM32L5xx/stm32l562xx.h @@ -478,7 +478,7 @@ typedef struct } DFSDM_Channel_TypeDef; /** - * @brief Debug MCU - TODO review for STM32L5 to be done + * @brief Debug MCU */ typedef struct { @@ -486,7 +486,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ } DBGMCU_TypeDef; /** @@ -1757,22 +1757,88 @@ typedef struct #define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) #define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) -/* Debug MCU registers base address */ +/*!< Debug MCU registers base address */ #define DBGMCU_BASE (0xE0044000UL) #define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ #define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */ -/* Internal Flash size */ +/*!< Internal Flash size */ #define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \ ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \ (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U))) -/* OTP Area */ +/*!< OTP Area */ #define OTP_BASE (0x0BFA0000UL) #define OTP_SIZE (0x200U) +/*!< Bootloader Area */ +#define BL_ID_ADDR (0x0BF97FFEUL) /*!< Bootloader ID address */ +#define BL_ID (*(uint8_t*)BL_ID_ADDR) /*!< Bootloader ID */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF97F40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF97FFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x0BF97F40UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL90; /*!< RSSLIB Bootloader ID90 Close and exit HDP Address offset: 0x20 */ + __IM uint32_t Reserved2; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL91; /*!< RSSLIB Bootloader ID91 Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + /** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */ @@ -4842,21 +4908,21 @@ typedef struct #define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk /******************** Bit definition for DBGMCU_APB2FZ register ************/ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U) -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U) -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ -#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U) -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ -#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U) -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ -#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ -#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /******************************************************************************/ /* */ @@ -17033,13 +17099,11 @@ typedef struct /****************** Bit definition for SYSCFG_RSSCMDR register **************/ #define SYSCFG_RSSCMDR_RSSCMD_Pos (0U) -#if defined(USE_CUT2_0) #define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ -#else -#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */ -#endif #define SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk /*!< RSS commands */ +#define SYSCFG_RSSCMDR_RSSCMD_BOOTLOADER ((uint16_t)0x01C0U) + /*****************************************************************************/ /* */ /* Global TrustZone Control */ diff --git a/os/common/ext/ST/STM32L5xx/stm32l5xx.h b/os/common/ext/ST/STM32L5xx/stm32l5xx.h index 054debe9e..07a7d337e 100644 --- a/os/common/ext/ST/STM32L5xx/stm32l5xx.h +++ b/os/common/ext/ST/STM32L5xx/stm32l5xx.h @@ -79,7 +79,7 @@ */ #define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32L5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32L5_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\