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I2C4 support without BDMA in I2Cv3. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13407 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-03-09 10:04:13 +00:00
parent 7384dbb0b9
commit 772e15a20d
6 changed files with 121 additions and 3 deletions
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5
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
View File

@ -199,6 +199,7 @@
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
@ -206,12 +207,16 @@
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*

31
os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c
View File

@ -112,6 +112,7 @@ I2CDriver I2CD4;
#if STM32_I2C_USE_DMA == TRUE
static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
#if STM32_I2C4_USE_BDMA == TRUE
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if (i2cp->is_bdma)
#endif
@ -123,6 +124,7 @@ static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
else
#endif
#endif /* STM32_I2C4_USE_BDMA == TRUE */
#if defined(STM32_I2C_DMA_REQUIRED)
{
dmaStreamEnable(i2cp->rx.dma);
@ -132,6 +134,7 @@ static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
#if STM32_I2C4_USE_BDMA == TRUE
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if (i2cp->is_bdma)
#endif
@ -143,6 +146,7 @@ static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
else
#endif
#endif /* STM32_I2C4_USE_BDMA == TRUE */
#if defined(STM32_I2C_DMA_REQUIRED)
{
dmaStreamEnable(i2cp->tx.dma);
@ -152,6 +156,7 @@ static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
#if STM32_I2C4_USE_BDMA == TRUE
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if (i2cp->is_bdma)
#endif
@ -163,6 +168,7 @@ static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
else
#endif
#endif /* STM32_I2C4_USE_BDMA == TRUE */
#if defined(STM32_I2C_DMA_REQUIRED)
{
dmaStreamDisable(i2cp->rx.dma);
@ -172,6 +178,7 @@ static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
static inline void i2c_lld_stop_tx_dma(I2CDriver *i2cp) {
#if STM32_I2C4_USE_BDMA == TRUE
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if (i2cp->is_bdma)
#endif
@ -183,6 +190,7 @@ static inline void i2c_lld_stop_tx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
else
#endif
#endif /* STM32_I2C4_USE_BDMA == TRUE */
#if defined(STM32_I2C_DMA_REQUIRED)
{
dmaStreamDisable(i2cp->tx.dma);
@ -764,8 +772,13 @@ void i2c_lld_init(void) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
I2CD4.is_bdma = true;
#endif
#if STM32_I2C4_USE_BDMA == TRUE
I2CD4.rx.bdma = NULL;
I2CD4.tx.bdma = NULL;
#else
I2CD4.rx.dma = NULL;
I2CD4.tx.dma = NULL;
#endif
#endif
#if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__)
nvicEnableVector(STM32_I2C4_GLOBAL_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY);
@ -904,6 +917,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C4(true);
#if STM32_I2C_USE_DMA == TRUE
{
#if STM32_I2C4_USE_BDMA == TRUE
i2cp->rx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_RX_BDMA_STREAM,
STM32_I2C_I2C4_IRQ_PRIORITY,
NULL,
@ -919,6 +933,23 @@ void i2c_lld_start(I2CDriver *i2cp) {
i2cp->txdmamode |= STM32_BDMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
bdmaSetRequestSource(i2cp->rx.bdma, STM32_DMAMUX2_I2C4_RX);
bdmaSetRequestSource(i2cp->tx.bdma, STM32_DMAMUX2_I2C4_TX);
#else /* STM32_I2C4_USE_BDMA != TRUE */
i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C4_RX_DMA_STREAM,
STM32_I2C_I2C4_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C4_TX_DMA_STREAM,
STM32_I2C_I2C4_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(i2cp->tx.dma != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
i2cp->txdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
dmaSetRequestSource(i2cp->rx.dma, STM32_DMAMUX1_I2C4_RX);
dmaSetRequestSource(i2cp->tx.dma, STM32_DMAMUX1_I2C4_TX);
#endif /* STM32_I2C4_USE_BDMA != TRUE */
}
#endif /* STM32_I2C_USE_DMA == TRUE */
}

66
os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.h
View File

@ -191,6 +191,27 @@
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks.*/
#if !defined(STM32_HAS_I2C1)
#error "STM32_HAS_I2C1 not defined in registry"
#endif
#if !defined(STM32_HAS_I2C2)
#error "STM32_HAS_I2C2 not defined in registry"
#endif
#if !defined(STM32_HAS_I2C3)
#error "STM32_HAS_I2C3 not defined in registry"
#endif
#if !defined(STM32_HAS_I2C4)
#error "STM32_HAS_I2C4 not defined in registry"
#endif
#if !defined(STM32_I2C4_USE_BDMA)
#error "STM32_I2C4_USE_BDMA not defined in registry"
#endif
/** @brief error checks */
#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
#error "I2C1 not present in the selected device"
@ -302,6 +323,8 @@
#endif
#if STM32_I2C_USE_I2C4
#if STM32_I2C4_USE_BDMA
#if !defined(STM32_I2C_I2C4_RX_BDMA_STREAM)
#error "STM32_I2C_I2C4_RX_BDMA_STREAM not defined"
#endif
@ -321,8 +344,34 @@
#if !STM32_BDMA_IS_VALID_PRIORITY(STM32_I2C_I2C4_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C4"
#endif
#else /* !STM32_I2C4_USE_BDMA */
#if !defined(STM32_I2C_I2C4_RX_DMA_STREAM)
#error "STM32_I2C_I2C4_RX_DMA_STREAM not defined"
#endif
#if !defined(STM32_I2C_I2C4_TX_DMA_STREAM)
#error "STM32_I2C_I2C4_TX_DMA_STREAM not defined"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C4_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C4 RX"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C4_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C4 TX"
#endif
#if !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C4_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C4"
#endif
#endif /* !STM32_I2C4_USE_BDMA */
#endif /* STM32_I2C_USE_I2C4 */
#if STM32_I2C4_USE_BDMA == TRUE
#if STM32_I2C_USE_I2C1 || STM32_I2C_USE_I2C2 || STM32_I2C_USE_I2C3
#define STM32_I2C_DMA_REQUIRED
#if !defined(STM32_DMA_REQUIRED)
@ -330,12 +379,25 @@
#endif
#endif
#else /* STM32_I2C4_USE_BDMA != TRUE */
#if STM32_I2C_USE_I2C1 || STM32_I2C_USE_I2C2 || STM32_I2C_USE_I2C3 || STM32_I2C_USE_I2C4
#define STM32_I2C_DMA_REQUIRED
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
#endif
#endif /* STM32_I2C4_USE_BDMA != TRUE */
#if STM32_I2C4_USE_BDMA == TRUE
#if STM32_I2C_USE_I2C4
#define STM32_I2C_BDMA_REQUIRED
#if !defined(STM32_BDMA_REQUIRED)
#define STM32_BDMA_REQUIRED
#endif
#endif
#endif /* STM32_I2C4_USE_BDMA == TRUE */
#endif /* STM32_I2C_USE_DMA == TRUE */
@ -440,11 +502,13 @@ struct I2CDriver {
*/
const stm32_dma_stream_t *dma;
#endif
#if (STM32_I2C4_USE_BDMA == TRUE) || defined(__DOXYGEN__)
#if defined(STM32_I2C_BDMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief Receive BDMA stream.
*/
const stm32_bdma_stream_t *bdma;
#endif
#endif
} rx;
/**
@ -457,11 +521,13 @@ struct I2CDriver {
*/
const stm32_dma_stream_t *dma;
#endif
#if (STM32_I2C4_USE_BDMA == TRUE) || defined(__DOXYGEN__)
#if defined(STM32_I2C_BDMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief Transmit DMA stream.
*/
const stm32_bdma_stream_t *bdma;
#endif
#endif
} tx;
#else /* STM32_I2C_USE_DMA == FALSE */

14
os/hal/ports/STM32/STM32H7xx/stm32_registry.h
View File

@ -29,9 +29,6 @@
/* Platform capabilities. */
/*===========================================================================*/
/* RNG attributes.*/
#define STM32_HAS_RNG1 TRUE
/* Cores.*/
#if defined(STM32H750xx) || defined(STM32H742xx) || \
defined(STM32H743xx) || defined(STM32H753xx)
@ -46,6 +43,17 @@
* @name STM32H7xx capabilities
* @{
*/
/*===========================================================================*/
/* Common. */
/*===========================================================================*/
/* RNG attributes.*/
#define STM32_HAS_RNG1 TRUE
/* I2C attributes.*/
#define STM32_I2C4_USE_BDMA TRUE
/*===========================================================================*/
/* STM32H743xx, STM32H753xx, STM32H745xx, STM32H755xx, STM32H747xx, */
/* STM32H757xx. */

3
os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
View File

@ -71,6 +71,9 @@
#define STM32_HAS_CRYP1 FALSE
#endif
/* I2C attributes.*/
#define STM32_I2C4_USE_BDMA FALSE
/*===========================================================================*/
/* STM32L4yyxx+. */
/*===========================================================================*/

5
tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
View File

@ -210,6 +210,7 @@
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
@ -217,12 +218,16 @@
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
/*