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More STM32 ADC improvements. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2472 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2010-12-11 17:35:55 +00:00
parent 7adef2884e
commit 7d66301e92
5 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c
View File

@ -48,7 +48,7 @@ static const ADCConversionGroup adcgrpcfg = {
adccb, adccb,
/* HW dependent part.*/ /* HW dependent part.*/
0, 0,
ADC_CR2_TSVREFE | ADC_CR2_CONT, ADC_CR2_TSVREFE,
ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5), ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5),
0, 0,
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),

6
os/hal/platforms/STM32/adc_lld.c
View File

@ -204,7 +204,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
/* ADC setup.*/ /* ADC setup.*/
adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN; adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN;
adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON; adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA |
ADC_CR2_CONT | ADC_CR2_ADON;
adcp->ad_adc->SMPR1 = grpp->acg_smpr1; adcp->ad_adc->SMPR1 = grpp->acg_smpr1;
adcp->ad_adc->SMPR2 = grpp->acg_smpr2; adcp->ad_adc->SMPR2 = grpp->acg_smpr2;
adcp->ad_adc->SQR1 = grpp->acg_sqr1; adcp->ad_adc->SQR1 = grpp->acg_sqr1;
@ -212,7 +213,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->ad_adc->SQR3 = grpp->acg_sqr3; adcp->ad_adc->SQR3 = grpp->acg_sqr3;
/* ADC start by writing ADC_CR2_ADON a second time.*/ /* ADC start by writing ADC_CR2_ADON a second time.*/
adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON; adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA |
ADC_CR2_CONT | ADC_CR2_ADON;
} }
/** /**

4
os/hal/platforms/STM32/adc_lld.h
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@ -173,8 +173,8 @@ typedef struct {
/** /**
* @brief ADC CR2 register initialization data. * @brief ADC CR2 register initialization data.
* @note All the required bits must be defined into this field except * @note All the required bits must be defined into this field except
* @p ADC_CR2_DMA and @p ADC_CR2_ADON that are enforced inside the * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
* driver. * enforced inside the driver.
*/ */
uint32_t acg_cr2; uint32_t acg_cr2;
/** /**

6
readme.txt
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@ -74,9 +74,9 @@
there is the possibility that the various vendors would use different there is the possibility that the various vendors would use different
CMSIS versions now that CMSIS 2.x has been released. CMSIS versions now that CMSIS 2.x has been released.
- CHANGE: Modified the start of the ADC in the STM32 ADC driver, now it is - CHANGE: Modified the start of the ADC in the STM32 ADC driver, now it is
no more required to specify ADC_CR2_EXTSEL_SWSTART in the CR2 register no more required to specify ADC_CR2_EXTSEL_SWSTART and ADC_CR2_CONT
configuration. Also reordered the start sequence in order to allows a in the CR2 register configuration. Also reordered the start sequence
longer stabilization time for the ADC. in order to allows a longer stabilization time for the ADC.
*** 2.1.5 *** *** 2.1.5 ***
- FIX: Fixed references to non-existing SSP1 device in LPC13xx SPI device - FIX: Fixed references to non-existing SSP1 device in LPC13xx SPI device

2
testhal/STM32/ADC/main.c
View File

@ -55,7 +55,7 @@ static const ADCConversionGroup adcgrpcfg = {
ADC_GRP1_NUM_CHANNELS, ADC_GRP1_NUM_CHANNELS,
adccallback, adccallback,
0, 0,
ADC_CR2_TSVREFE | ADC_CR2_CONT, ADC_CR2_TSVREFE,
0, 0,
0, 0,
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),