mirror of https://github.com/rusefi/ChibiOS.git
RTC. Fixed some bugs and added locks into write functions. Haltest updated.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3790 35acf78f-673a-0410-8e92-d51de3d6d3f4
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bff048984e
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@ -80,17 +80,30 @@ static void rtc_lld_serve_interrupt(RTCDriver *rtcp) {
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}
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/**
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* @brief Waits for the previous registers write to finish.
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* @brief Acquire atomic write access to RTC registers.
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*
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* @notapi
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*/
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static void rtc_lld_wait_write(void) {
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static void rtc_lld_acquire(void) {
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/* Waits registers write completion.*/
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BEGIN:
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while ((RTC->CRL & RTC_CRL_RTOFF) == 0)
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;
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chSysLock();
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if ((RTC->CRL & RTC_CRL_RTOFF) == 0){
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chSysUnlock();
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goto BEGIN;
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}
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}
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/**
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* @brief Release atomic write access to RTC registers.
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*
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* @notapi
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*/
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#define rtc_lld_release() {chSysUnlock();}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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@ -130,21 +143,26 @@ void rtc_lld_init(void){
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while (!(RTC->CRL & RTC_CRL_RSF))
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;
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/* Write preload register only if its value differs.*/
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/* Write preload register only if its value is not equal to desired value.*/
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if (STM32_RTCCLK != (((uint32_t)(RTC->PRLH)) << 16) +
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((uint32_t)RTC->PRLL) + 1) {
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/* Enters configuration mode and writes PRLx registers then leaves the
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configuration mode.*/
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rtc_lld_wait_write();
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rtc_lld_acquire();
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RTC->CRL |= RTC_CRL_CNF;
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RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16);
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RTC->PRLL = (uint16_t)((STM32_RTCCLK - 1) & 0xFFFF);
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RTC->CRL &= ~RTC_CRL_CNF;
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rtc_lld_release();
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}
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/* All interrupts initially disabled.*/
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RTC->CRH = 0;
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if (RTC->CRH != 0){
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rtc_lld_acquire();
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RTC->CRH = 0;
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rtc_lld_release();
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}
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/* Callback initially disabled.*/
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RTCD1.callback = NULL;
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@ -164,11 +182,12 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
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(void)rtcp;
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rtc_lld_wait_write();
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rtc_lld_acquire();
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RTC->CRL |= RTC_CRL_CNF;
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RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16);
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RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF);
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RTC->CRL &= ~RTC_CRL_CNF;
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rtc_lld_release();
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}
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/**
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@ -216,7 +235,7 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
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/* Enters configuration mode and writes ALRHx registers then leaves the
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configuration mode.*/
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rtc_lld_wait_write();
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rtc_lld_acquire();
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RTC->CRL |= RTC_CRL_CNF;
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if (alarmspec != NULL) {
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RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);
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@ -227,6 +246,7 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
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RTC->ALRL = 0;
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}
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RTC->CRL &= ~RTC_CRL_CNF;
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rtc_lld_release();
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}
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/**
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@ -264,6 +284,7 @@ void rtc_lld_get_alarm(RTCDriver *rtcp,
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*/
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void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
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rtc_lld_acquire();
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if (callback != NULL) {
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rtcp->callback = callback;
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@ -276,9 +297,10 @@ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
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}
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else {
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nvicDisableVector(RTC_IRQn);
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RTC->CRL = 0;
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RTC->CRH = 0;
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RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
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RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE);
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}
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rtc_lld_release();
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}
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#endif /* HAL_USE_RTC */
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@ -72,9 +72,6 @@ static void hal_lld_backup_domain_init(void) {
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RCC->BDCR |= RCC_BDCR_RTCEN;
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}
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#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
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/* Backup domain access disabled for operations safety.*/
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PWR->CR &= ~PWR_CR_DBP;
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}
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/*===========================================================================*/
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@ -24,17 +24,23 @@
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RTCTime timespec;
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RTCAlarm alarmspec;
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#define TEST_ALARM_WAKEUP FALSE
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#define TEST_ALARM_WAKEUP TRUE
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#if TEST_ALARM_WAKEUP
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static void my_cb(RTCDriver *rtcp, rtcevent_t event) {
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(void)rtcp;
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(void)event;
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return;
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}
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/* sleep indicator thread */
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static WORKING_AREA(blinkWA, 128);
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static msg_t blink_thd(void *arg){
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(void)arg;
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while (TRUE) {
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chThdSleepMilliseconds(100);
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palTogglePad(IOPORT3, GPIOC_LED);
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palTogglePad(GPIOC, GPIOC_LED);
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}
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return 0;
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}
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@ -45,24 +51,32 @@ int main(void) {
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chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL);
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/* set alarm in near future */
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rtcGetTime(×pec);
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alarmspec.tv_sec = timespec.tv_sec + 60;
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rtcSetAlarm(&alarmspec);
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rtcGetTime(&RTCD1, ×pec);
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alarmspec.tv_sec = timespec.tv_sec + 30;
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rtcSetAlarm(&RTCD1, 0, &alarmspec);
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/* Needed just to switch interrupts on.*/
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rtcSetCallback(&RTCD1, my_cb);
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while (TRUE){
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chThdSleepSeconds(10);
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chSysLock();
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chThdSleepSeconds(10);
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chSysLock();
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/* going to anabiosis*/
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PWR->CR |= (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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__WFI();
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/* going to anabiosis*/
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PWR->CR |= (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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__WFI();
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}
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return 0;
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}
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#else /* TEST_ALARM_WAKEUP */
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/* Manually reloaded test alarm period.*/
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#define RTC_ALARMPERIOD 10
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BinarySemaphore alarm_sem;
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static void my_cb(RTCDriver *rtcp, rtcevent_t event) {
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(void)rtcp;
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@ -76,24 +90,36 @@ static void my_cb(RTCDriver *rtcp, rtcevent_t event) {
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break;
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case RTC_EVENT_ALARM:
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palTogglePad(GPIOC, GPIOC_LED);
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rtcGetTime(&RTCD1, ×pec);
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alarmspec.tv_sec = timespec.tv_sec + 10;
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rtcSetAlarm(&RTCD1, 0, &alarmspec);
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chBSemSignalI(&alarm_sem);
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break;
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}
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}
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int main(void) {
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msg_t status = RDY_TIMEOUT;
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halInit();
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chSysInit();
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chBSemInit(&alarm_sem, TRUE);
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rtcGetTime(&RTCD1, ×pec);
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alarmspec.tv_sec = timespec.tv_sec + 10;
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alarmspec.tv_sec = timespec.tv_sec + RTC_ALARMPERIOD;
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rtcSetAlarm(&RTCD1, 0, &alarmspec);
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rtcSetCallback(&RTCD1, my_cb);
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while (TRUE){
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chThdSleepMilliseconds(500);
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/* Wait until alarm callback signaled semaphore.*/
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status = chBSemWaitTimeout(&alarm_sem, S2ST(RTC_ALARMPERIOD + 5));
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if (status == RDY_TIMEOUT){
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chSysHalt();
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}
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else{
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rtcGetTime(&RTCD1, ×pec);
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alarmspec.tv_sec = timespec.tv_sec + RTC_ALARMPERIOD;
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rtcSetAlarm(&RTCD1, 0, &alarmspec);
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}
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}
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return 0;
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}
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@ -38,7 +38,7 @@
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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@ -50,7 +50,7 @@
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#define STM32_USB_CLOCK_REQUIRED TRUE
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#define STM32_USBPRE STM32_USBPRE_DIV1P5
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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