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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3629 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2011-12-17 19:25:30 +00:00
parent e062d10250
commit 8172ebaa5b
2 changed files with 40 additions and 35 deletions
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2
demos/ARMCM4-STM32F407-DISCOVERY/Makefile
View File

@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -mhard-float
USE_OPT = -O2 -ggdb -fomit-frame-pointer -mhard-float -mfpu=fpv4-sp-d16
endif
# C specific options here (added to USE_OPT).

73
os/ports/GCC/ARMCMx/chcore_v7m.c
View File

@ -111,28 +111,31 @@ void PendSVVector(void) {
* @brief Port-related initialization code.
*/
void _port_init(void) {
uint32_t reg;
/* Initialization of the vector table and priority related settings.*/
SCB_VTOR = CORTEX_VTOR_INIT;
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);
#if CORTEX_USE_FPU
/* CP10 and CP11 set to full access.*/
SCB_CPACR |= 0x00F00000;
{
uint32_t reg;
/* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
asm volatile ("mrs %0, CONTROL" : "=r" (reg) : : "memory");
reg |= 4;
asm volatile ("msr CONTROL, %0" : : "r" (reg) : "memory");
/* CP10 and CP11 set to full access.*/
SCB_CPACR |= 0x00F00000;
/* FPSCR and FPDSCR initially zero.*/
reg = 0;
asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory");
SCB_FPDSCR = reg;
/* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
asm volatile ("mrs %0, CONTROL" : "=r" (reg) : : "memory");
reg |= 4;
asm volatile ("msr CONTROL, %0" : : "r" (reg) : "memory");
/* Initializing the FPU context save in lazy mode.*/
SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
/* FPSCR and FPDSCR initially zero.*/
reg = 0;
asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory");
SCB_FPDSCR = reg;
/* Initializing the FPU context save in lazy mode.*/
SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
}
#endif
/* Initialization of the system vectors used by the port.*/
@ -155,6 +158,29 @@ void _port_irq_epilogue(void) {
/* Current PSP value.*/
asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
/* Adding an artificial exception return context, there is no need to
populate it fully.*/
ctxp--;
asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
ctxp->xpsr = (regarm_t)0x01000000;
/* The exit sequence is different depending on if a preemption is
required or not.*/
if (chSchIsPreemptionRequired()) {
/* Preemption is required we need to enforce a context switch.*/
ctxp->pc = _port_switch_from_isr;
#if CORTEX_USE_FPU
/* Triggering a lazy FPU state save.*/
asm volatile ("vmrs APSR_nzcv, FPSCR" : : : "memory");
#endif
}
else {
/* Preemption not required, we just need to exit the exception
atomically.*/
void _port_exit_from_isr(void);
ctxp->pc = _port_exit_from_isr;
}
#if CORTEX_USE_FPU
{
uint32_t fpccr;
@ -168,27 +194,6 @@ void _port_irq_epilogue(void) {
}
#endif
/* Adding an artificial exception return context, there is no need to
populate it fully.*/
ctxp--;
asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
ctxp->xpsr = (regarm_t)0x01000000;
/* The exit sequence is different depending on if a preemption is
required or not.*/
if (chSchIsPreemptionRequired()) {
/* Preemption is required we need to trigger a lazy FPU state save
and enforce a context switch.*/
ctxp->pc = _port_switch_from_isr;
asm volatile ("vmrs APSR_nzcv, FPSCR" : : : "memory");
}
else {
/* Preemption not required, we just need to exit the exception
atomically.*/
void _port_exit_from_isr(void);
ctxp->pc = _port_exit_from_isr;
}
/* Note, returning without unlocking is intentional, this is done in
order to keep the rest of the context switching atomic.*/
return;