mirror of https://github.com/rusefi/ChibiOS.git
[KINETIS] Registers and fields for ADC.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7249 35acf78f-673a-0410-8e92-d51de3d6d3f4
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spacecoaster
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@ -211,34 +211,34 @@ typedef struct
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typedef struct
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{
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__IO uint32_t SC1A; // offset: 0x00
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__IO uint32_t SC1B; // offset: 0x04
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__IO uint32_t CFG1; // offset: 0x08
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__IO uint32_t CFG2; // offset: 0x0C
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__I uint32_t RA; // offset: 0x10
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__I uint32_t RB; // offset: 0x14
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__IO uint32_t CV1; // offset: 0x18
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__IO uint32_t CV2; // offset: 0x1C
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__IO uint32_t SC2; // offset: 0x20
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__IO uint32_t SC3; // offset: 0x24
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__IO uint32_t OFS; // offset: 0x28
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__IO uint32_t PG; // offset: 0x2C
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__IO uint32_t MG; // offset: 0x30
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__IO uint32_t CLPD; // offset: 0x34
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__IO uint32_t CLPS; // offset: 0x38
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__IO uint32_t CLP4; // offset: 0x3C
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__IO uint32_t CLP3; // offset: 0x40
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__IO uint32_t CLP2; // offset: 0x44
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__IO uint32_t CLP1; // offset: 0x48
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__IO uint32_t CLP0; // offset: 0x4C
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uint32_t RESERVED0[1]; // offset: 0x50
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__IO uint32_t CLMD; // offset: 0x54
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__IO uint32_t CLMS; // offset: 0x58
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__IO uint32_t CLM4; // offset: 0x5C
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__IO uint32_t CLM3; // offset: 0x60
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__IO uint32_t CLM2; // offset: 0x64
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__IO uint32_t CLM1; // offset: 0x68
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__IO uint32_t CLM0; // offset: 0x6C
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__IO uint32_t SC1A; // ADC Status and Control Registers 1
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__IO uint32_t SC1B; // ADC Status and Control Registers 1
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__IO uint32_t CFG1; // ADC Configuration Register 1
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__IO uint32_t CFG2; // ADC Configuration Register 2
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__I uint32_t RA; // ADC Data Result Register
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__I uint32_t RB; // ADC Data Result Register
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__IO uint32_t CV1; // Compare Value Registers
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__IO uint32_t CV2; // Compare Value Registers
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__IO uint32_t SC2; // Status and Control Register 2
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__IO uint32_t SC3; // Status and Control Register 3
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__IO uint32_t OFS; // ADC Offset Correction Register
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__IO uint32_t PG; // ADC Plus-Side Gain Register
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__IO uint32_t MG; // ADC Minus-Side Gain Register
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__IO uint32_t CLPD; // ADC Plus-Side General Calibration Value Register
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__IO uint32_t CLPS; // ADC Plus-Side General Calibration Value Register
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__IO uint32_t CLP4; // ADC Plus-Side General Calibration Value Register
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__IO uint32_t CLP3; // ADC Plus-Side General Calibration Value Register
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__IO uint32_t CLP2; // ADC Plus-Side General Calibration Value Register
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__IO uint32_t CLP1; // ADC Plus-Side General Calibration Value Register
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__IO uint32_t CLP0; // ADC Plus-Side General Calibration Value Register
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uint32_t RESERVED0[1]; // ADC Minus-Side General Calibration Value Register
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__IO uint32_t CLMD; // ADC Minus-Side General Calibration Value Register
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__IO uint32_t CLMS; // ADC Minus-Side General Calibration Value Register
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__IO uint32_t CLM4; // ADC Minus-Side General Calibration Value Register
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__IO uint32_t CLM3; // ADC Minus-Side General Calibration Value Register
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__IO uint32_t CLM2; // ADC Minus-Side General Calibration Value Register
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__IO uint32_t CLM1; // ADC Minus-Side General Calibration Value Register
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__IO uint32_t CLM0; // ADC Minus-Side General Calibration Value Register
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} ADC_TypeDef;
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typedef struct
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@ -323,6 +323,13 @@ typedef struct
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__IO uint8_t C5;
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} UARTLP_TypeDef;
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typedef struct
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{
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__IO uint8_t LVDSC1;
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__IO uint8_t LVDSC2;
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__IO uint8_t REGSC;
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} PMC_TypeDef;
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/****************************************************************/
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/* Peripheral memory map */
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/****************************************************************/
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@ -350,6 +357,7 @@ typedef struct
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#define SPI0_BASE ((uint32_t)0x40076000)
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#define SPI1_BASE ((uint32_t)0x40077000)
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#define LLWU_BASE ((uint32_t)0x4007C000)
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#define PMC_BASE ((uint32_t)0x4007D000)
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#define GPIOA_BASE ((uint32_t)0x400FF000)
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#define GPIOB_BASE ((uint32_t)0x400FF040)
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#define GPIOC_BASE ((uint32_t)0x400FF080)
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@ -369,6 +377,7 @@ typedef struct
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#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
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#define SIM ((SIM_TypeDef *) SIM_BASE)
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#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
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#define PMC ((PMC_TypeDef *) PMC_BASE)
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#define PORTA ((PORT_TypeDef *) PORTA_BASE)
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#define PORTB ((PORT_TypeDef *) PORTB_BASE)
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#define PORTC ((PORT_TypeDef *) PORTC_BASE)
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@ -445,6 +454,20 @@ typedef struct
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#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */
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#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */
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/******* Bits definition for SIM_SCGC6 register ************/
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#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */
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#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */
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#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */
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#define SIM_SCGC6_TMP2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */
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#define SIM_SCGC6_TMP1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */
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#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */
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#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */
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#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */
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#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */
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/******* Bits definition for SIM_SCGC6 register ************/
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#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */
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/****** Bits definition for SIM_CLKDIV1 register ***********/
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#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */
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#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */
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@ -1145,5 +1168,30 @@ typedef struct
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#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */
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#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */
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#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */
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/****************************************************************/
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/* */
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/* Power Management Controller (PMC) */
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/* */
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/****************************************************************/
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/********* Bits definition for PMC_LVDSC1 register *************/
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#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */
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#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */
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#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */
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#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */
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#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */
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#define PMC_LVDSC1_LVDV_SHIFT 0
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#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
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/********* Bits definition for PMC_LVDSC1 register *************/
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#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */
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#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */
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#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */
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#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */
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#define PMC_LVDSC2_LVWV_SHIFT 0
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#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
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/********* Bits definition for PMC_REGSC register *************/
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#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */
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#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */
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#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */
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#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */
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#endif
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@ -395,6 +395,13 @@ typedef struct
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__IO uint8_t TIDT;
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} UART_TypeDef;
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typedef struct
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{
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__IO uint8_t LVDSC1;
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__IO uint8_t LVDSC2;
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__IO uint8_t REGSC;
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} PMC_TypeDef;
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typedef struct
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{
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__IO uint16_t STCTRLH;
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@ -526,6 +533,7 @@ typedef struct {
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#define UART2_BASE ((uint32_t)0x4006C000)
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#define USBOTG_BASE ((uint32_t)0x40072000)
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#define LLWU_BASE ((uint32_t)0x4007C000)
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#define PMC_BASE ((uint32_t)0x4007D000)
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#define GPIOA_BASE ((uint32_t)0x400FF000)
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#define GPIOB_BASE ((uint32_t)0x400FF040)
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#define GPIOC_BASE ((uint32_t)0x400FF080)
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@ -545,6 +553,7 @@ typedef struct {
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#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
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#define SIM ((SIM_TypeDef *) SIM_BASE)
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#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
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#define PMC ((PMC_TypeDef *) PMC_BASE)
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#define PORTA ((PORT_TypeDef *) PORTA_BASE)
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#define PORTB ((PORT_TypeDef *) PORTB_BASE)
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#define PORTC ((PORT_TypeDef *) PORTC_BASE)
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@ -1813,6 +1822,32 @@ typedef struct {
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#define UARTx_PFIFO_RXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_RXFIFOSIZE_SHIFT))
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#define UARTx_PFIFO_RXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_RXFIFOSIZE_SHIFT) & UARTx_PFIFO_RXFIFOSIZE_MASK)) /*!< Receive FIFO Buffer depth */
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/****************************************************************/
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/* */
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/* Power Management Controller (PMC) */
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/* */
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/****************************************************************/
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/********* Bits definition for PMC_LVDSC1 register *************/
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#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */
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#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */
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#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */
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#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */
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#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */
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#define PMC_LVDSC1_LVDV_SHIFT 0
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#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
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/********* Bits definition for PMC_LVDSC1 register *************/
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#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */
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#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */
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#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */
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#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */
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#define PMC_LVDSC2_LVWV_SHIFT 0
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#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
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/********* Bits definition for PMC_REGSC register *************/
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#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */
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#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */
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#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */
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#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */
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/****************************************************************/
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/* */
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/* Watchdog */
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