mirror of https://github.com/rusefi/ChibiOS.git
STM32 HAL improvements (CL devices).
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2820 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
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@ -34,6 +34,9 @@
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/*
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* HAL driver system settings.
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*/
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#define STM32_ACTIVATE_PLL1 TRUE
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#define STM32_ACTIVATE_PLL2 TRUE
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#define STM32_ACTIVATE_PLL3 TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_PREDIV1
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#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2
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@ -41,12 +44,13 @@
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#define STM32_PLLMUL_VALUE 9
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#define STM32_PREDIV2_VALUE 5
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#define STM32_PLL2MUL_VALUE 8
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#define STM32_PLL3MUL_VALUE 10
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
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#define STM32_MCO STM32_MCO_NOCLOCK
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#define STM32_MCO STM32_MCO_PLL3
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/*
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* ADC driver system settings.
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@ -146,43 +146,51 @@ void stm32_clock_init(void) {
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*/
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void stm32_clock_init(void) {
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/* HSI setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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/* HSI setup.*/
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RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Wait until HSI is stable. */
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RCC->CFGR = 0;
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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; /* Wait until HSI is the source.*/
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RCC->CFGR2 = 0;
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/* HSE setup, it is only performed if the HSE clock is selected as source
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of the system clock (directly or through the PLLs).*/
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#if (STM32_SW == STM32_SW_HSE) || \
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((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
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/* HSE setup, it is only performed if the current configuration uses
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it somehow.*/
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#if STM32_ACTIVATE_PLL2 || \
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STM32_ACTIVATE_PLL3 || \
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(STM32_SW == STM32_SW_HSE) || \
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((STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) && \
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(STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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; /* Waits until HSE is stable. */
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#endif
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/* PLL2 setup, it is only performed if the PLL2 clock is selected as source
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for the PLL clock else it is left disabled.*/
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#if STM32_SW == STM32_SW_PLL
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#if STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2
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RCC->CFGR2 |= STM32_PREDIV2 | STM32_PLL2MUL;
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RCC->CR |= RCC_CR_PLL2ON;
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/* Settings of various dividers and multipliers in CFGR2.*/
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RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
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STM32_PREDIV1 | STM32_PREDIV1SRC;
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/* PLL2 setup, if activated.*/
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#if STM32_ACTIVATE_PLL2
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RCC->CR |= RCC_CR_PLL2ON;
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while (!(RCC->CR & RCC_CR_PLL2RDY))
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; /* Waits until PLL is stable. */
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; /* Waits until PLL2 is stable. */
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#endif
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/* PLL setup, it is only performed if the PLL is the selected source of
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the system clock else it is left disabled.*/
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RCC->CFGR2 |= STM32_PREDIV1 | STM32_PREDIV1SRC;
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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/* PLL3 setup, if activated.*/
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#if STM32_ACTIVATE_PLL3
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RCC->CR |= RCC_CR_PLL3ON;
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while (!(RCC->CR & RCC_CR_PLL3RDY))
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; /* Waits until PLL3 is stable. */
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#endif
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/* PLL1 setup, if activated.*/
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#if STM32_ACTIVATE_PLL1
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL2 is stable. */
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; /* Waits until PLL1 is stable. */
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#endif
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/* Clock settings.*/
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@ -170,10 +170,35 @@
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief PLL1 main switch.
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* @note If this constant is set to @p TRUE then the PLL1 is initialized
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* and started.
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*/
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#if !defined(STM32_ACTIVATE_PLL1) || defined(__DOXYGEN__)
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#define STM32_ACTIVATE_PLL1 TRUE
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#endif
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/**
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* @brief PLL2 main switch.
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* @note If this constant is set to @p TRUE then the PLL2 is initialized
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* and started.
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*/
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#if !defined(STM32_ACTIVATE_PLL2) || defined(__DOXYGEN__)
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#define STM32_ACTIVATE_PLL2 TRUE
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#endif
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/**
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* @brief PLL3 main switch.
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* @note If this constant is set to @p TRUE then the PLL3 is initialized
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* and started.
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*/
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#if !defined(STM32_ACTIVATE_PLL3) || defined(__DOXYGEN__)
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#define STM32_ACTIVATE_PLL3 TRUE
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#endif
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/**
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* @brief Main clock source selection.
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* @note If the selected clock source is not the PLL then the PLL is not
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* initialized and started.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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@ -183,8 +208,6 @@
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/**
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* @brief Clock source for the PLL.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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@ -194,8 +217,6 @@
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/**
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* @brief PREDIV1 clock source.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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@ -205,8 +226,6 @@
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/**
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* @brief PREDIV1 division factor.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The allowed range is 1...16.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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@ -227,8 +246,6 @@
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/**
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* @brief PREDIV2 division factor.
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* @note This setting has only effect if the PLL2 is selected as the
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* clock source for the PLL.
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* @note The allowed range is 1...16.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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@ -246,6 +263,15 @@
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#define STM32_PLL2MUL_VALUE 8
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#endif
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/**
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* @brief PLL3 multiplier value.
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* @note The default value is calculated for a 50MHz clock from
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* a 25MHz crystal.
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*/
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#if !defined(STM32_PLL3MUL_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3MUL_VALUE 10
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#endif
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/**
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* @brief AHB prescaler value.
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* @note The default value is calculated for a 72MHz system clock from
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@ -294,6 +320,14 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* PLL2 usage check.*/
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#if STM32_ACTIVATE_PLL2 && \
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(STM32_PREDIV1SRC != STM32_PREDIV1SRC_PLL2) && \
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(STM32_MCO != STM32_MCO_PLL2)
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#error "PLL2 activated but not used"
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#endif
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/**
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* @brief PREDIV1 field.
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*/
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@ -338,9 +372,22 @@
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#error "invalid STM32_PLL2MUL_VALUE value specified"
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#endif
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/* The following values are only used if PLL2 clock is selected as source
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for the PLL clock */
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#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__)
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/**
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* @brief PLL3MUL field.
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*/
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#if ((STM32_PLL3MUL_VALUE >= 8) && (STM32_PLL3MUL_VALUE <= 14)) || \
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defined(__DOXYGEN__)
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#define STM32_PLL3MUL ((STM32_PLL3MUL_VALUE - 2) << 12)
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#elif (STM32_PLL3MUL_VALUE == 16)
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#define STM32_PLL3MUL (14 << 12)
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#elif (STM32_PLL3MUL_VALUE == 20)
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#define STM32_PLL3MUL (15 << 12)
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#else
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#error "invalid STM32_PLL3MUL_VALUE value specified"
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#endif
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/* The following values are only used if PLL2 is activated */
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#if STM32_ACTIVATE_PLL2
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/**
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* @brief PLL2 input frequency.
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*/
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@ -356,11 +403,44 @@
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*/
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#define STM32_PLL2CLKOUT (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
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/**
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* @brief PLL2 VCO clock frequency.
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*/
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#define STM32_PLL2VCO (STM32_PLL2CLKOUT * 2)
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/* PLL2 output frequency range check.*/
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#if (STM32_PLL2CLKOUT < 40000000) || (STM32_PLL2CLKOUT > 74000000)
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#error "STM32_PLL2CLKOUT outside acceptable range (40...74MHz)"
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#if (STM32_PLL2VCO < 80000000) || (STM32_PLL2VCO > 148000000)
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#error "STM32_PLL2VCO outside acceptable range (80...148MHz)"
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#endif
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#endif /* STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 */
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#endif /* STM32_ACTIVATE_PLL2 */
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/* The following values are only used if PLL3 is activated */
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#if STM32_ACTIVATE_PLL3
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/**
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* @brief PLL3 input frequency.
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*/
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#define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE)
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/* PLL3 input frequency range check.*/
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#if (STM32_PLL3CLKIN < 3000000) || (STM32_PLL3CLKIN > 5000000)
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#error "STM32_PLL3CLKIN outside acceptable range (3...5MHz)"
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#endif
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/**
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* @brief PLL3 output clock frequency.
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*/
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#define STM32_PLL3CLKOUT (STM32_PLL3CLKIN * STM32_PLL3MUL_VALUE)
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/**
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* @brief PLL3 VCO clock frequency.
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*/
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#define STM32_PLL3VCO (STM32_PLL3CLKOUT * 2)
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/* PLL3 output frequency range check.*/
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#if (STM32_PLL3VCO < 80000000) || (STM32_PLL3VCO > 148000000)
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#error "STM32_PLL3CLKOUT outside acceptable range (80...148MHz)"
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#endif
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#endif /* STM32_ACTIVATE_PLL3 */
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/**
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* @brief PREDIV1 input frequency.
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@ -377,9 +457,9 @@
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* @brief PLL input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__)
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#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
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#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / 2)
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#define STM32_PLLCLKIN (STM32_HSICLK / 2)
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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@ -392,11 +472,16 @@
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/**
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* @brief PLL output clock frequency.
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*/
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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/**
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* @brief PLL VCO clock frequency.
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*/
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#define STM32_PLLVCO (STM32_PLLCLKOUT * 2)
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/* PLL output frequency range check.*/
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#if (STM32_PLLCLKOUT < 18000000) || (STM32_PLLCLKOUT > 72000000)
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#error "STM32_PLLCLKOUT outside acceptable range (18...72MHz)"
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#if (STM32_PLLVCO < 36000000) || (STM32_PLLVCO > 144000000)
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#error "STM32_PLLVCO outside acceptable range (36...144MHz)"
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#endif
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/**
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@ -515,9 +600,9 @@
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* @brief OTG frequency.
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*/
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#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__)
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#define STM32_OTGFSCLK ((STM32_PLLCLKOUT * 2) / 3)
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#define STM32_OTGFSCLK (STM32_PLLVCO / 3)
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#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2)
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#define STM32_OTGFSCLK STM32_PLLCLKOUT
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#define STM32_OTGFSCLK (STM32_PLLVCO / 2)
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#else
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#error "invalid STM32_OTGFSPRE value specified"
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#endif
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@ -73,6 +73,8 @@
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*** 2.3.1 ***
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- FIX: Fixed invalid assertion in adcConvert() (bug 3205410)(backported
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to 2.2.3).
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- NEW: Added support for PLL3 in STM32 HAL driver. Note, the format of the
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mcuconf.h file is changed for STM32F105/STM32F107 devices.
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- NEW: Added board files for the Olimex STM32-P107.
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- NEW: Improved setup packets handling in the USB driver through a specific
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callback.
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