diff --git a/os/ex/ST/lis3mdl.c b/os/ex/ST/lis3mdl.c new file mode 100644 index 000000000..e8022ae2c --- /dev/null +++ b/os/ex/ST/lis3mdl.c @@ -0,0 +1,484 @@ +/* + ChibiOS - Copyright (C) 2016 Rocco Marco Guglielmi + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +*/ + +/** + * @file lis3mdl.c + * @brief LIS3MDL MEMS interface module code. + * + * @addtogroup lis3mdl + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "lis3mdl.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define LIS3MDL_SENS_4GA ((float)6842.0f) +#define LIS3MDL_SENS_8GA ((float)3421.0f) +#define LIS3MDL_SENS_12GA ((float)2281.0f) +#define LIS3MDL_SENS_16GA ((float)1711.0f) + +#define LIS3MDL_TEMP_SENS ((float)8.0f) + +#define LIS3MDL_DI ((uint8_t)0xFF) +#define LIS3MDL_DI_0 ((uint8_t)0x01) +#define LIS3MDL_DI_1 ((uint8_t)0x02) +#define LIS3MDL_DI_2 ((uint8_t)0x04) +#define LIS3MDL_DI_3 ((uint8_t)0x08) +#define LIS3MDL_DI_4 ((uint8_t)0x10) +#define LIS3MDL_DI_5 ((uint8_t)0x20) +#define LIS3MDL_DI_6 ((uint8_t)0x40) +#define LIS3MDL_DI_7 ((uint8_t)0x80) + +#define LIS3MDL_AD ((uint8_t)0x3F) +#define LIS3MDL_AD_0 ((uint8_t)0x01) +#define LIS3MDL_AD_1 ((uint8_t)0x02) +#define LIS3MDL_AD_2 ((uint8_t)0x04) +#define LIS3MDL_AD_3 ((uint8_t)0x08) +#define LIS3MDL_AD_4 ((uint8_t)0x10) +#define LIS3MDL_AD_5 ((uint8_t)0x20) +#define LIS3MDL_AD_6 ((uint8_t)0x40) + +#define LIS3MDL_RW ((uint8_t)0x80) + +#define LIS3MDL_AD_WHO_AM_I ((uint8_t)0x0F) +#define LIS3MDL_AD_CTRL_REG1 ((uint8_t)0x20) +#define LIS3MDL_AD_CTRL_REG2 ((uint8_t)0x21) +#define LIS3MDL_AD_CTRL_REG3 ((uint8_t)0x22) +#define LIS3MDL_AD_CTRL_REG4 ((uint8_t)0x23) +#define LIS3MDL_AD_CTRL_REG5 ((uint8_t)0x24) +#define LIS3MDL_AD_STATUS_REG ((uint8_t)0x27) +#define LIS3MDL_AD_OUT_X_L ((uint8_t)0x28) +#define LIS3MDL_AD_OUT_X_H ((uint8_t)0x29) +#define LIS3MDL_AD_OUT_Y_L ((uint8_t)0x2A) +#define LIS3MDL_AD_OUT_Y_H ((uint8_t)0x2B) +#define LIS3MDL_AD_OUT_Z_L ((uint8_t)0x2C) +#define LIS3MDL_AD_OUT_Z_H ((uint8_t)0x2D) +#define LIS3MDL_AD_TEMP_OUT_L ((uint8_t)0x2E) +#define LIS3MDL_AD_TEMP_OUT_H ((uint8_t)0x2F) +#define LIS3MDL_AD_INT_CFG ((uint8_t)0x30) +#define LIS3MDL_AD_INT_SOURCE ((uint8_t)0x31) +#define LIS3MDL_AD_INT_THS_L ((uint8_t)0x32) +#define LIS3MDL_AD_INT_THS_H ((uint8_t)0x33) + +#define LIS3MDL_CTRL_REG2_FS_MASK ((uint8_t)0x60) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if (LIS3MDL_USE_I2C) || defined(__DOXYGEN__) +/** + * @brief Reads registers value using I2C. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] reg first sub-register address + * @return the read value. + */ +uint8_t lis3mdlI2CReadRegister(I2CDriver *i2cp, lis3mdl_sad_t sad, uint8_t reg, + msg_t* msgp) { + msg_t msg; +#if defined(STM32F103_MCUCONF) + uint8_t rxbuf[2]; + msg = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, + TIME_INFINITE); + if(msgp != NULL){ + *msgp = msg; + } + return rxbuf[0]; +#else + uint8_t txbuf, rxbuf; + txbuf = reg; + msg = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, &rxbuf, 1, + TIME_INFINITE); + if(msgp != NULL){ + *msgp = msg; + } + return rxbuf; +#endif +} + +/** + * @brief Writes a value into a register using I2C. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] value the value to be written + * @return the operation status. + */ +msg_t lis3mdlI2CWriteRegister(I2CDriver *i2cp, lis3mdl_sad_t sad, uint8_t reg, + uint8_t value) { + uint8_t rxbuf; + uint8_t txbuf[2]; + switch (reg) { + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "lis3mdlI2CWriteRegister(), reserved register"); + case LIS3MDL_AD_WHO_AM_I: + case LIS3MDL_AD_STATUS_REG: + case LIS3MDL_AD_OUT_X_L: + case LIS3MDL_AD_OUT_X_H: + case LIS3MDL_AD_OUT_Y_L: + case LIS3MDL_AD_OUT_Y_H: + case LIS3MDL_AD_OUT_Z_L: + case LIS3MDL_AD_OUT_Z_H: + case LIS3MDL_AD_TEMP_OUT_L: + case LIS3MDL_AD_TEMP_OUT_H: + case LIS3MDL_AD_INT_SOURCE: + case LIS3MDL_AD_INT_THS_L: + case LIS3MDL_AD_INT_THS_H: + /* Read only registers cannot be written, the command is ignored.*/ + return MSG_RESET; + case LIS3MDL_AD_CTRL_REG1: + case LIS3MDL_AD_CTRL_REG2: + case LIS3MDL_AD_CTRL_REG3: + case LIS3MDL_AD_CTRL_REG4: + case LIS3MDL_AD_CTRL_REG5: + case LIS3MDL_AD_INT_CFG: + txbuf[0] = reg; + txbuf[1] = value; + return i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); + break; + } +} +#endif /* LIS3MDL_USE_I2C */ + +/* + * Interface implementation. + */ +static size_t get_axes_number(void *ip) { + + osalDbgCheck(ip != NULL); + return LIS3MDL_NUMBER_OF_AXES; +} + +static msg_t read_raw(void *ip, int32_t axes[LIS3MDL_NUMBER_OF_AXES]) { + + osalDbgCheck((ip != NULL) && (axes != NULL)); + osalDbgAssert((((LIS3MDLDriver *)ip)->state == LIS3MDL_READY), + "read_raw(), invalid state"); + +#if LIS3MDL_USE_I2C + osalDbgAssert((((LIS3MDLDriver *)ip)->config->i2cp->state == I2C_READY), + "read_raw(), channel not ready"); +#if LIS3MDL_SHARED_I2C + i2cAcquireBus(((LIS3MDLDriver *)ip)->config->i2cp); + i2cStart(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->i2ccfg); +#endif /* LIS3MDL_SHARED_I2C */ + + axes[0] = (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_OUT_X_L, NULL)); + axes[0] += (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_OUT_X_H, NULL) << 8); + axes[0] -= ((LIS3MDLDriver *)ip)->bias[0]; + + axes[1] = (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_OUT_Y_L, NULL)); + axes[1] += (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_OUT_Y_H, NULL) << 8); + axes[1] -= ((LIS3MDLDriver *)ip)->bias[1]; + + axes[2] = (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_OUT_Z_L, NULL)); + axes[2] += (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_OUT_Z_H, NULL) << 8); + axes[2] -= ((LIS3MDLDriver *)ip)->bias[2]; + +#if LIS3MDL_SHARED_I2C + i2cReleaseBus(((LIS3MDLDriver *)ip)->config->i2cp); +#endif /* LIS3MDL_SHARED_I2C */ +#endif /* LIS3MDL_USE_I2C */ + return MSG_OK; +} + +static msg_t read_cooked(void *ip, float axes[]) { + uint32_t i; + int32_t raw[LIS3MDL_NUMBER_OF_AXES]; + msg_t msg; + + osalDbgCheck((ip != NULL) && (axes != NULL)); + + osalDbgAssert((((LIS3MDLDriver *)ip)->state == LIS3MDL_READY), + "read_cooked(), invalid state"); + + msg = read_raw(ip, raw); + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES ; i++){ + axes[i] = raw[i] / ((LIS3MDLDriver *)ip)->sensitivity[i]; + } + return msg; +} + +static msg_t set_bias(void *ip, int32_t *bp) { + uint32_t i; + + osalDbgCheck((ip != NULL) && (bp !=NULL)); + + osalDbgAssert((((LIS3MDLDriver *)ip)->state == LIS3MDL_READY) || + (((LIS3MDLDriver *)ip)->state == LIS3MDL_STOP), + "set_bias(), invalid state"); + + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) { + ((LIS3MDLDriver *)ip)->bias[i] = bp[i]; + } + return MSG_OK; +} + +static msg_t reset_bias(void *ip) { + uint32_t i; + + osalDbgCheck(ip != NULL); + + osalDbgAssert((((LIS3MDLDriver *)ip)->state == LIS3MDL_READY) || + (((LIS3MDLDriver *)ip)->state == LIS3MDL_STOP), + "reset_bias(), invalid state"); + + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + ((LIS3MDLDriver *)ip)->bias[i] = 0; + return MSG_OK; +} + +static msg_t set_sensivity(void *ip, float *sp) { + uint32_t i; + + osalDbgCheck((ip != NULL) && (sp !=NULL)); + + osalDbgAssert((((LIS3MDLDriver *)ip)->state == LIS3MDL_READY), + "set_sensivity(), invalid state"); + + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) { + ((LIS3MDLDriver *)ip)->sensitivity[i] = sp[i]; + } + return MSG_OK; +} + +static msg_t reset_sensivity(void *ip) { + uint32_t i; + + osalDbgCheck(ip != NULL); + + osalDbgAssert((((LIS3MDLDriver *)ip)->state == LIS3MDL_READY), + "reset_sensivity(), invalid state"); + + if(((LIS3MDLDriver *)ip)->config->fullscale == LIS3MDL_FS_4GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + ((LIS3MDLDriver *)ip)->sensitivity[i] = LIS3MDL_SENS_4GA; + else if(((LIS3MDLDriver *)ip)->config->fullscale == LIS3MDL_FS_8GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + ((LIS3MDLDriver *)ip)->sensitivity[i] = LIS3MDL_SENS_8GA; + else if(((LIS3MDLDriver *)ip)->config->fullscale == LIS3MDL_FS_12GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + ((LIS3MDLDriver *)ip)->sensitivity[i] = LIS3MDL_SENS_12GA; + else if(((LIS3MDLDriver *)ip)->config->fullscale == LIS3MDL_FS_16GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + ((LIS3MDLDriver *)ip)->sensitivity[i] = LIS3MDL_SENS_16GA; + else + osalDbgAssert(FALSE, "reset_sensivity(), compass full scale issue"); + return MSG_OK; +} + +static msg_t get_temperature(void *ip, float* tempp) { + int16_t temp; +#if LIS3MDL_USE_I2C + osalDbgAssert((((LIS3MDLDriver *)ip)->config->i2cp->state == I2C_READY), + "gyro_read_raw(), channel not ready"); +#if LIS3MDL_SHARED_I2C + i2cAcquireBus(((LIS3MDLDriver *)ip)->config->i2cp); + i2cStart(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->i2ccfg); +#endif /* LIS3MDL_SHARED_I2C */ + temp = (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_TEMP_OUT_L, NULL)); + temp += (int16_t)(lis3mdlI2CReadRegister(((LIS3MDLDriver *)ip)->config->i2cp, + ((LIS3MDLDriver *)ip)->config->slaveaddress, + LIS3MDL_AD_TEMP_OUT_H, NULL) << 8); +#if LIS3MDL_SHARED_I2C + i2cReleaseBus(((LIS3MDLDriver *)ip)->config->i2cp); +#endif /* LIS3MDL_SHARED_I2C */ +#endif /* LIS3MDL_USE_I2C */ + *tempp = (float)temp / LIS3MDL_TEMP_SENS; + return MSG_OK; +} + +static const struct BaseSensorVMT vmt_basesensor = { + get_axes_number, read_raw, read_cooked +}; + +static const struct BaseCompassVMT vmt_basecompass = { + get_axes_number, read_raw, read_cooked, + set_bias, reset_bias, set_sensivity, reset_sensivity +}; + +static const struct LIS3MDLVMT vmt_lis3mdl = { + get_axes_number, read_raw, read_cooked, + set_bias, reset_bias, set_sensivity, reset_sensivity, + get_temperature +}; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes an instance. + * + * @param[out] devp pointer to the @p LIS3MDLDriver object + * + * @init + */ +void lis3mdlObjectInit(LIS3MDLDriver *devp) { + uint32_t i; + devp->vmt_basesensor = &vmt_basesensor; + devp->vmt_basecompass = &vmt_basecompass; + devp->vmt_lis3mdl = &vmt_lis3mdl; + devp->config = NULL; + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + devp->bias[i] = 0; + devp->state = LIS3MDL_STOP; +} + +/** + * @brief Configures and activates LIS3MDL Complex Driver peripheral. + * + * @param[in] devp pointer to the @p LIS3MDLDriver object + * @param[in] config pointer to the @p LIS3MDLConfig object + * + * @api + */ +void lis3mdlStart(LIS3MDLDriver *devp, const LIS3MDLConfig *config) { + uint32_t i; + osalDbgCheck((devp != NULL) && (config != NULL)); + + osalDbgAssert((devp->state == LIS3MDL_STOP) || (devp->state == LIS3MDL_READY), + "lis3mdlStart(), invalid state"); + + devp->config = config; + +#if LIS3MDL_USE_I2C +#if LIS3MDL_SHARED_I2C + i2cAcquireBus((devp)->config->i2cp); +#endif /* LIS3MDL_SHARED_I2C */ + i2cStart((devp)->config->i2cp, + (devp)->config->i2ccfg); + lis3mdlI2CWriteRegister(devp->config->i2cp, + devp->config->slaveaddress, + LIS3MDL_AD_CTRL_REG1, + devp->config->temperature | + devp->config->outputdatarate | + devp->config->operationmodexy); + lis3mdlI2CWriteRegister(devp->config->i2cp, + devp->config->slaveaddress, + LIS3MDL_AD_CTRL_REG2, + devp->config->fullscale); + lis3mdlI2CWriteRegister(devp->config->i2cp, + devp->config->slaveaddress, + LIS3MDL_AD_CTRL_REG3, + devp->config->conversionmode); + lis3mdlI2CWriteRegister(devp->config->i2cp, + devp->config->slaveaddress, + LIS3MDL_AD_CTRL_REG4, + devp->config->operationmodez | + devp->config->endianness); + lis3mdlI2CWriteRegister(devp->config->i2cp, + devp->config->slaveaddress, + LIS3MDL_AD_CTRL_REG5, + devp->config->blockdataupdate); +#if LIS3MDL_SHARED_I2C + i2cReleaseBus((devp)->config->i2cp); +#endif /* LIS3MDL_SHARED_I2C */ +#endif /* LIS3MDL_USE_I2C */ + /* Storing sensitivity information according to full scale value */ + if(devp->config->fullscale == LIS3MDL_FS_4GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + devp->sensitivity[i] = LIS3MDL_SENS_4GA; + else if(devp->config->fullscale == LIS3MDL_FS_8GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + devp->sensitivity[i] = LIS3MDL_SENS_8GA; + else if(devp->config->fullscale == LIS3MDL_FS_12GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + devp->sensitivity[i] = LIS3MDL_SENS_12GA; + else if(devp->config->fullscale == LIS3MDL_FS_16GA) + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + devp->sensitivity[i] = LIS3MDL_SENS_16GA; + else + osalDbgAssert(FALSE, "lis3mdlStart(), compass full scale issue"); + devp->state = LIS3MDL_READY; +} + +/** + * @brief Deactivates the LIS3MDL Complex Driver peripheral. + * + * @param[in] devp pointer to the @p LIS3MDLDriver object + * + * @api + */ +void lis3mdlStop(LIS3MDLDriver *devp) { + + osalDbgCheck(devp != NULL); + + osalDbgAssert((devp->state == LIS3MDL_STOP) || (devp->state == LIS3MDL_READY), + "lis3mdlStop(), invalid state"); + +#if (LIS3MDL_USE_I2C) + if (devp->state == LIS3MDL_STOP) { +#if LIS3MDL_SHARED_I2C + i2cAcquireBus((devp)->config->i2cp); + i2cStart((devp)->config->i2cp, + (devp)->config->i2ccfg); +#endif /* LIS3MDL_SHARED_I2C */ + lis3mdlI2CWriteRegister(devp->config->i2cp, + devp->config->slaveaddress, + LIS3MDL_AD_CTRL_REG3, + LIS3MDL_MD_POWER_DOWN); + i2cStop((devp)->config->i2cp); +#if LIS3MDL_SHARED_I2C + i2cReleaseBus((devp)->config->i2cp); +#endif /* LIS3MDL_SHARED_I2C */ + } +#endif /* LIS3MDL_USE_I2C */ + devp->state = LIS3MDL_STOP; +} +/** @} */ diff --git a/os/ex/ST/lis3mdl.h b/os/ex/ST/lis3mdl.h index 21a61e620..e80579984 100644 --- a/os/ex/ST/lis3mdl.h +++ b/os/ex/ST/lis3mdl.h @@ -92,8 +92,8 @@ #error "LIS3MDL_USE_I2C requires HAL_USE_I2C" #endif -#if LIS3MDL_SHARED_SPI && !SPI_USE_MUTUAL_EXCLUSION -#error "LIS3MDL_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION" +#if LIS3MDL_SHARED_I2C && !I2C_USE_MUTUAL_EXCLUSION +#error "LIS3MDL_SHARED_I2C requires I2C_USE_MUTUAL_EXCLUSION" #endif /*===========================================================================*/ @@ -173,6 +173,14 @@ typedef enum { LIS3MDL_OMZ_ULTRA = 0x0C /**< Z axis ultra performance mode */ }lis3mdl_omz_t; +/** + * @brief LIS3MDL temperature sensor enabling + */ +typedef enum { + LIS3MDL_TEMP_DISABLED = 0x00, /**< Temperature sensor disabled. */ + LIS3MDL_TEMP_ENABLED = 0x80 /**< Temperature sensor enabled. */ +}lis3mdl_temp_t; + /** * @brief LIS3MDL block data update */ @@ -251,6 +259,10 @@ typedef struct { * @brief LIS3MDL operation mode for Z axis */ lis3mdl_omz_t operationmodez; + /** + * @brief LIS3MDL temperature sensor enabling + */ + lis3mdl_temp_t temperature; /** * @brief LIS3MDL block data update */ @@ -322,7 +334,8 @@ struct LIS3MDLDriver { /** * @brief Get current MEMS temperature. - * @detail This information is very useful especially for high accuracy IMU + * @detail This information is very useful especially for high accuracy IMU. + * @note Temperature sensor must be enabled using a proper configuration. * * @param[in] ip pointer to a @p BaseCompass class. * @param[out] temp the MEMS temperature as single precision floating. diff --git a/os/hal/lib/peripherals/sensors/hal_compass.h b/os/hal/lib/peripherals/sensors/hal_compass.h index 041c82bdd..83efc9852 100644 --- a/os/hal/lib/peripherals/sensors/hal_compass.h +++ b/os/hal/lib/peripherals/sensors/hal_compass.h @@ -46,7 +46,16 @@ /** * @brief BaseCompass specific methods. */ -#define _base_compass_methods_alone +#define _base_compass_methods_alone \ + /* Invoke the set bias procedure.*/ \ + msg_t (*set_bias)(void *instance, int32_t biases[]); \ + /* Remove bias stored data.*/ \ + msg_t (*reset_bias)(void *instance); \ + /* Invoke the set sensitivity procedure.*/ \ + msg_t (*set_sensitivity)(void *instance, float sensitivities[]); \ + /* Restore sensitivity stored data to default.*/ \ + msg_t (*reset_sensitivity)(void *instance); + /** * @brief BaseCompass specific methods with inherited ones. @@ -125,6 +134,70 @@ typedef struct { */ #define compassReadCooked(ip, dp) \ (ip)->vmt_basecompass->read_cooked(ip, dp) + +/** + * @brief Updates compass bias data from received buffer. + * @note The bias buffer must have the same length of the + * the compass axes number. Bias must be computed on + * raw data and is a signed integer. + * + * @param[in] ip pointer to a @p BaseCompass class. + * @param[in] bp pointer to a buffer of bias values. + * + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more errors occurred. + * + * @api + */ +#define compassSetBias(ip, bp) \ + (ip)->vmt_basecompass->set_bias(ip, bp) + +/** + * @brief Reset compass bias data restoring it to zero. + * + * @param[in] ip pointer to a @p BaseCompass class. + * + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more errors occurred. + * + * @api + */ +#define compassResetBias(ip) \ + (ip)->vmt_basecompass->reset_bias(ip) + +/** + * @brief Updates compass sensitivity data from received buffer. + * @note The sensitivity buffer must have the same length of the + * the compass axes number. + * + * @param[in] ip pointer to a @p BaseCompass class. + * @param[in] sp pointer to a buffer of sensitivity values. + * + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more errors occurred. + * + * @api + */ +#define compassSetSensitivity(ip, sp) \ + (ip)->vmt_basecompass->set_sensitivity(ip, sp) + +/** + * @brief Reset compass sensitivity data restoring it to its typical + * value. + * + * @param[in] ip pointer to a @p BaseCompass class. + * + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more errors occurred. + * + * @api + */ +#define compassResetSensitivity(ip) \ + (ip)->vmt_basecompass->reset_sensitivity(ip) /** @} */ /*===========================================================================*/ diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/.cproject b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/.cproject new file mode 100644 index 000000000..0cbf370f8 --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/.cproject @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/.project b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/.project new file mode 100644 index 000000000..3adcc743b --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/.project @@ -0,0 +1,90 @@ + + + STM32L4xx-I2C-LIS3MDL + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_NUCLEO64_L476RG + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/Makefile b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/Makefile new file mode 100644 index 000000000..85a3c2c0b --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/Makefile @@ -0,0 +1,220 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = hard +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L476RG/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/os/ex/ST/lis3mdl.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32L476xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(LIS3MDLSRC) \ + $(STREAMSSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LIS3MDLINC) \ + $(STREAMSINC) $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DCHPRINTF_USE_FLOAT=1 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/chconf.h b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/chconf.h new file mode 100644 index 000000000..a554d3957 --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_NONE. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_NONE. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/debug/STM32L4xx-I2C-LIS3MDL (OpenOCD, Flash and Run).launch b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/debug/STM32L4xx-I2C-LIS3MDL (OpenOCD, Flash and Run).launch new file mode 100644 index 000000000..a943e81e9 --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/debug/STM32L4xx-I2C-LIS3MDL (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/halconf.h b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/halconf.h new file mode 100644 index 000000000..be911d195 --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/halconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/main.c b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/main.c new file mode 100644 index 000000000..f2cabe576 --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/main.c @@ -0,0 +1,106 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#include "chprintf.h" +#include "lis3mdl.h" + +/* Enable use of special ANSI escape sequences */ +#define CHPRINTF_USE_ANSI_CODE TRUE + +static BaseSequentialStream * chp = (BaseSequentialStream*) &SD2; + +/* LIS3MDL Driver: This object represent an LIS3MDL instance */ +static LIS3MDLDriver LIS3MDLD1; + +static int32_t rawdata[LIS3MDL_NUMBER_OF_AXES]; +static float cookeddata[LIS3MDL_NUMBER_OF_AXES]; + +static char axesID[LIS3MDL_NUMBER_OF_AXES] = {'X', 'Y', 'Z'}; +static uint32_t i; + +static const I2CConfig i2ccfg = { + STM32_TIMINGR_PRESC(15U) | + STM32_TIMINGR_SCLDEL(4U) | STM32_TIMINGR_SDADEL(2U) | + STM32_TIMINGR_SCLH(15U) | STM32_TIMINGR_SCLL(21U), + 0, + 0 +}; + +static const LIS3MDLConfig lis3mdlcfg = { + &I2CD1, + &i2ccfg, + LIS3MDL_SAD_VCC, + LIS3MDL_FS_4GA, + LIS3MDL_ODR_40HZ, + LIS3MDL_LP_DISABLED, + LIS3MDL_MD_CONTINUOUS, + LIS3MDL_OMXY_ULTRA, + LIS3MDL_OMZ_ULTRA, + LIS3MDL_TEMP_ENABLED, + LIS3MDL_BDU_BLOCKED, + LIS3MDL_END_LITTLE +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + palSetLineMode(LINE_ARD_D14, PAL_MODE_ALTERNATE(4) | PAL_STM32_OSPEED_HIGH); + palSetLineMode(LINE_ARD_D15, PAL_MODE_ALTERNATE(4) | PAL_STM32_OSPEED_HIGH); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * LIS3MDL Object Initialization + */ + lis3mdlObjectInit(&LIS3MDLD1); + + lis3mdlStart(&LIS3MDLD1, &lis3mdlcfg); + + while (TRUE) { + palToggleLine(LINE_LED_GREEN); + compassReadRaw(&LIS3MDLD1, rawdata); + compassReadCooked(&LIS3MDLD1, cookeddata); +#if CHPRINTF_USE_ANSI_CODE + chprintf(chp, "\033[2J\033[1;1H"); +#endif + chprintf(chp, "COMPASS DATA\r\n"); + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + chprintf(chp, "RAW-%c:%d\t\t", axesID[i], rawdata[i]); + chprintf(chp, "\r\n"); + for(i = 0; i < LIS3MDL_NUMBER_OF_AXES; i++) + chprintf(chp, "COOKED-%c:%.3f Gauss\t", axesID[i], cookeddata[i]); + chprintf(chp, "\r\n"); + chThdSleepMilliseconds(100); + } +} diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/mcuconf.h b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/mcuconf.h new file mode 100644 index 000000000..4a217233b --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/mcuconf.h @@ -0,0 +1,330 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_RANGE1 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI16_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_MSIPLL_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_SAI1_CLOCK_ENABLED TRUE +#define STM32_SAI2_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_4M +#define STM32_MSISRANGE STM32_MSISRANGE_4M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_MSI +#define STM32_PLLM_VALUE 1 +#define STM32_PLLN_VALUE 80 +#define STM32_PLLP_VALUE 7 +#define STM32_PLLQ_VALUE 6 +#define STM32_PLLR_VALUE 4 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_STOPWUCK STM32_STOPWUCK_MSI +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK +#define STM32_PLLSAI1N_VALUE 72 +#define STM32_PLLSAI1P_VALUE 7 +#define STM32_PLLSAI1Q_VALUE 6 +#define STM32_PLLSAI1R_VALUE 6 +#define STM32_PLLSAI2N_VALUE 72 +#define STM32_PLLSAI2P_VALUE 7 +#define STM32_PLLSAI2R_VALUE 6 +#define STM32_USART1SEL STM32_USART1SEL_SYSCLK +#define STM32_USART2SEL STM32_USART2SEL_SYSCLK +#define STM32_USART3SEL STM32_USART3SEL_SYSCLK +#define STM32_UART4SEL STM32_UART4SEL_SYSCLK +#define STM32_UART5SEL STM32_UART5SEL_SYSCLK +#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK +#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK +#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_ADCSEL STM32_ADCSEL_SYSCLK +#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 +#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1 +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1635_38_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2122_IRQ_PRIORITY 15 + + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM15_IRQ_PRIORITY 7 +#define STM32_GPT_TIM16_IRQ_PRIORITY 7 +#define STM32_GPT_TIM17_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_LPUART1 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_LPUART1_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_LPUART1 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_LPUART1_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/testhal/STM32/STM32L4xx/I2C-LIS3MLD/readme.txt b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/readme.txt new file mode 100644 index 000000000..9a34e6b20 --- /dev/null +++ b/testhal/STM32/STM32L4xx/I2C-LIS3MLD/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/HAL + ChibiOS/EX - I2C + LIS3MDL demo for STM32L4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32L4-Nucleo board. It has been +tested with the X-NUCLEO-IKS01A1 shield. + +** The Demo ** + +The application demonstrates the use of the STM32L4xx EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com