mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5849 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
126943984c
commit
8e9ee823a7
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC560Pxx_MCUCONF
|
||||
|
@ -147,6 +149,15 @@
|
|||
#define SPC5_PIT0_IRQ_PRIORITY 4
|
||||
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING 0
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
|
@ -162,3 +173,83 @@
|
|||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define SPC5_SPI_USE_DSPI0 TRUE
|
||||
#define SPC5_SPI_USE_DSPI1 TRUE
|
||||
#define SPC5_SPI_USE_DSPI2 TRUE
|
||||
#define SPC5_SPI_USE_DSPI3 TRUE
|
||||
#define SPC5_SPI_USE_DSPI4 FALSE
|
||||
#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI0_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI4_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||||
#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
|
|
@ -58,10 +58,6 @@
|
|||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP1_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP2_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP3_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
|
|
|
@ -59,7 +59,7 @@ include $(CHIBIOS)/os/kernel/kernel.mk
|
|||
include $(CHIBIOS)/test/test.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(PORTLD)/SPC564A80.ld
|
||||
LDSCRIPT= $(PORTLD)/SPC564A70.ld
|
||||
|
||||
# C sources here.
|
||||
CSRC = $(PORTSRC) \
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC564Axx_MCUCONF
|
||||
|
@ -44,6 +46,25 @@
|
|||
BIUCR_PFLIM_ON_MISS | \
|
||||
BIUCR_BFEN)
|
||||
|
||||
/*
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
|
||||
EDMA_CR_GRP2PRI(2) | \
|
||||
EDMA_CR_GRP1PRI(1) | \
|
||||
EDMA_CR_GRP0PRI(0) | \
|
||||
EDMA_CR_ERGA)
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP1_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP2_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP3_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* ADC driver settings.
|
||||
*/
|
||||
|
@ -53,12 +74,6 @@
|
|||
#define SPC5_ADC_USE_ADC1_Q3 FALSE
|
||||
#define SPC5_ADC_USE_ADC1_Q4 FALSE
|
||||
#define SPC5_ADC_USE_ADC1_Q5 FALSE
|
||||
#define SPC5_ADC_FIFO0_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO1_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO2_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO3_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO4_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO5_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
|
||||
#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
|
||||
#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
|
||||
|
@ -88,9 +103,9 @@
|
|||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define SPC5_SPI_USE_DSPI1 TRUE
|
||||
#define SPC5_SPI_USE_DSPI2 TRUE
|
||||
#define SPC5_SPI_USE_DSPI3 TRUE
|
||||
#define SPC5_SPI_USE_DSPI1 FALSE
|
||||
#define SPC5_SPI_USE_DSPI2 FALSE
|
||||
#define SPC5_SPI_USE_DSPI3 FALSE
|
||||
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
|
@ -115,9 +130,6 @@
|
|||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI1_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC56ELxx_MCUCONF
|
||||
|
@ -41,9 +43,9 @@
|
|||
#define SPC5_FMPLL1_IDF_VALUE 5
|
||||
#define SPC5_FMPLL1_NDIV_VALUE 60
|
||||
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
|
||||
#define SPC5_SYSCLK_DIVIDER_VALUE 1
|
||||
#define SPC5_SYSCLK_DIVIDER_VALUE 2
|
||||
#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
|
||||
#define SPC5_MCONTROL_DIVIDER_VALUE 2
|
||||
#define SPC5_MCONTROL_DIVIDER_VALUE 15
|
||||
#define SPC5_SWG_DIVIDER_VALUE 2
|
||||
#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1
|
||||
#define SPC5_FLEXRAY_DIVIDER_VALUE 2
|
||||
|
@ -104,18 +106,6 @@
|
|||
SPC5_ME_MC_PLL1ON | \
|
||||
SPC5_ME_MC_FLAON_NORMAL | \
|
||||
SPC5_ME_MC_MVRON)
|
||||
#define SPC5_ME_RUN_PC0_BITS 0
|
||||
#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \
|
||||
SPC5_ME_RUN_PC_DRUN | \
|
||||
SPC5_ME_RUN_PC_RUN0 | \
|
||||
SPC5_ME_RUN_PC_RUN1 | \
|
||||
SPC5_ME_RUN_PC_RUN2 | \
|
||||
SPC5_ME_RUN_PC_RUN3)
|
||||
#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
|
||||
SPC5_ME_RUN_PC_RUN0 | \
|
||||
SPC5_ME_RUN_PC_RUN1 | \
|
||||
SPC5_ME_RUN_PC_RUN2 | \
|
||||
SPC5_ME_RUN_PC_RUN3)
|
||||
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
||||
SPC5_ME_RUN_PC_RUN1 | \
|
||||
SPC5_ME_RUN_PC_RUN2 | \
|
||||
|
@ -136,11 +126,6 @@
|
|||
SPC5_ME_RUN_PC_RUN1 | \
|
||||
SPC5_ME_RUN_PC_RUN2 | \
|
||||
SPC5_ME_RUN_PC_RUN3)
|
||||
#define SPC5_ME_LP_PC0_BITS 0
|
||||
#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
|
||||
SPC5_ME_LP_PC_STOP0)
|
||||
#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
|
||||
#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
|
||||
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
|
||||
SPC5_ME_LP_PC_STOP0)
|
||||
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
|
||||
|
@ -151,6 +136,15 @@
|
|||
SPC5_ME_LP_PC_STOP0)
|
||||
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING 0
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
|
@ -166,3 +160,121 @@
|
|||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define SPC5_PWM_USE_SMOD0 FALSE
|
||||
#define SPC5_PWM_USE_SMOD1 FALSE
|
||||
#define SPC5_PWM_USE_SMOD2 FALSE
|
||||
#define SPC5_PWM_USE_SMOD3 FALSE
|
||||
#define SPC5_PWM_SMOD0_PRIORITY 7
|
||||
#define SPC5_PWM_SMOD1_PRIORITY 7
|
||||
#define SPC5_PWM_SMOD2_PRIORITY 7
|
||||
#define SPC5_PWM_SMOD3_PRIORITY 7
|
||||
#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
#define SPC5_PWM_USE_SMOD4 FALSE
|
||||
#define SPC5_PWM_USE_SMOD5 FALSE
|
||||
#define SPC5_PWM_USE_SMOD6 FALSE
|
||||
#define SPC5_PWM_USE_SMOD7 FALSE
|
||||
#define SPC5_PWM_SMOD4_PRIORITY 7
|
||||
#define SPC5_PWM_SMOD5_PRIORITY 7
|
||||
#define SPC5_PWM_SMOD6_PRIORITY 7
|
||||
#define SPC5_PWM_SMOD7_PRIORITY 7
|
||||
#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define SPC5_ICU_USE_SMOD0 FALSE
|
||||
#define SPC5_ICU_USE_SMOD1 FALSE
|
||||
#define SPC5_ICU_USE_SMOD2 FALSE
|
||||
#define SPC5_ICU_USE_SMOD3 FALSE
|
||||
#define SPC5_ICU_USE_SMOD4 FALSE
|
||||
#define SPC5_ICU_USE_SMOD5 FALSE
|
||||
#define SPC5_ICU_ETIMER0_PRIORITY 7
|
||||
#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
#define SPC5_ICU_USE_SMOD6 FALSE
|
||||
#define SPC5_ICU_USE_SMOD7 FALSE
|
||||
#define SPC5_ICU_USE_SMOD8 FALSE
|
||||
#define SPC5_ICU_USE_SMOD9 FALSE
|
||||
#define SPC5_ICU_USE_SMOD10 FALSE
|
||||
#define SPC5_ICU_USE_SMOD11 FALSE
|
||||
#define SPC5_ICU_ETIMER1_PRIORITY 7
|
||||
#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
#define SPC5_ICU_USE_SMOD12 FALSE
|
||||
#define SPC5_ICU_USE_SMOD13 FALSE
|
||||
#define SPC5_ICU_USE_SMOD14 FALSE
|
||||
#define SPC5_ICU_USE_SMOD15 FALSE
|
||||
#define SPC5_ICU_USE_SMOD16 FALSE
|
||||
#define SPC5_ICU_USE_SMOD17 FALSE
|
||||
#define SPC5_ICU_ETIMER2_PRIORITY 7
|
||||
#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define SPC5_SPI_USE_DSPI0 FALSE
|
||||
#define SPC5_SPI_USE_DSPI1 FALSE
|
||||
#define SPC5_SPI_USE_DSPI2 FALSE
|
||||
#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI0_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||||
#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
|
|
@ -93,6 +93,15 @@
|
|||
#define SPC5_DSPI0_PCTL 4
|
||||
#define SPC5_DSPI1_PCTL 5
|
||||
#define SPC5_DSPI2_PCTL 6
|
||||
#define SPC5_DSPI0_TX1_DMA_CH_ID 4
|
||||
#define SPC5_DSPI0_TX2_DMA_CH_ID 5
|
||||
#define SPC5_DSPI0_RX_DMA_CH_ID 6
|
||||
#define SPC5_DSPI1_TX1_DMA_CH_ID 7
|
||||
#define SPC5_DSPI1_TX2_DMA_CH_ID 8
|
||||
#define SPC5_DSPI1_RX_DMA_CH_ID 9
|
||||
#define SPC5_DSPI2_TX1_DMA_CH_ID 10
|
||||
#define SPC5_DSPI2_TX2_DMA_CH_ID 11
|
||||
#define SPC5_DSPI2_RX_DMA_CH_ID 12
|
||||
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
|
||||
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
|
||||
#define SPC5_DSPI0_RX_DMA_DEV_ID 2
|
||||
|
@ -124,6 +133,9 @@
|
|||
#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
|
||||
#define SPC5_HAS_DSPI3 TRUE
|
||||
#define SPC5_DSPI3_PCTL 7
|
||||
#define SPC5_DSPI3_TX1_DMA_CH_ID 13
|
||||
#define SPC5_DSPI3_TX2_DMA_CH_ID 14
|
||||
#define SPC5_DSPI3_RX_DMA_CH_ID 15
|
||||
#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
|
||||
#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
|
||||
#define SPC5_DSPI3_RX_DMA_DEV_ID 8
|
||||
|
@ -140,6 +152,9 @@
|
|||
#if defined(_SPC560PXX_LARGE_)
|
||||
#define SPC5_HAS_DSPI4 TRUE
|
||||
#define SPC5_DSPI4_PCTL 8
|
||||
#define SPC5_DSPI4_TX1_DMA_CH_ID 1
|
||||
#define SPC5_DSPI4_TX2_DMA_CH_ID 2
|
||||
#define SPC5_DSPI4_RX_DMA_CH_ID 3
|
||||
#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
|
||||
#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
|
||||
#define SPC5_DSPI4_RX_DMA_DEV_ID 21
|
||||
|
|
|
@ -54,15 +54,15 @@
|
|||
#define SPC5_HAS_DSPI3 TRUE
|
||||
#define SPC5_HAS_DSPI4 FALSE
|
||||
#define SPC5_DSPI_FIFO_DEPTH 16
|
||||
#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
|
||||
#define SPC5_DSPI1_TX2_DMA_DEV_ID 24
|
||||
#define SPC5_DSPI1_RX_DMA_DEV_ID 13
|
||||
#define SPC5_DSPI2_TX1_DMA_DEV_ID 14
|
||||
#define SPC5_DSPI2_TX2_DMA_DEV_ID 25
|
||||
#define SPC5_DSPI2_RX_DMA_DEV_ID 15
|
||||
#define SPC5_DSPI3_TX1_DMA_DEV_ID 16
|
||||
#define SPC5_DSPI3_TX2_DMA_DEV_ID 26
|
||||
#define SPC5_DSPI3_RX_DMA_DEV_ID 17
|
||||
#define SPC5_DSPI1_TX1_DMA_CH_ID 12
|
||||
#define SPC5_DSPI1_TX2_DMA_CH_ID 24
|
||||
#define SPC5_DSPI1_RX_DMA_CH_ID 13
|
||||
#define SPC5_DSPI2_TX1_DMA_CH_ID 14
|
||||
#define SPC5_DSPI2_TX2_DMA_CH_ID 25
|
||||
#define SPC5_DSPI2_RX_DMA_CH_ID 15
|
||||
#define SPC5_DSPI3_TX1_DMA_CH_ID 16
|
||||
#define SPC5_DSPI3_TX2_DMA_CH_ID 26
|
||||
#define SPC5_DSPI3_RX_DMA_CH_ID 17
|
||||
#define SPC5_DSPI1_EOQF_HANDLER vector132
|
||||
#define SPC5_DSPI1_EOQF_NUMBER 132
|
||||
#define SPC5_DSPI1_TFFF_HANDLER vector133
|
||||
|
|
|
@ -48,6 +48,15 @@
|
|||
#define SPC5_DSPI0_PCTL 4
|
||||
#define SPC5_DSPI1_PCTL 5
|
||||
#define SPC5_DSPI2_PCTL 6
|
||||
#define SPC5_DSPI0_TX1_DMA_CH_ID 4
|
||||
#define SPC5_DSPI0_TX2_DMA_CH_ID 5
|
||||
#define SPC5_DSPI0_RX_DMA_CH_ID 6
|
||||
#define SPC5_DSPI1_TX1_DMA_CH_ID 7
|
||||
#define SPC5_DSPI1_TX2_DMA_CH_ID 8
|
||||
#define SPC5_DSPI1_RX_DMA_CH_ID 9
|
||||
#define SPC5_DSPI2_TX1_DMA_CH_ID 10
|
||||
#define SPC5_DSPI2_TX2_DMA_CH_ID 11
|
||||
#define SPC5_DSPI2_RX_DMA_CH_ID 12
|
||||
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
|
||||
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
|
||||
#define SPC5_DSPI0_RX_DMA_DEV_ID 2
|
||||
|
|
File diff suppressed because one or more lines are too long
|
@ -116,7 +116,7 @@ int main(void) {
|
|||
SIU.PCR[14].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */
|
||||
SIU.PCR[13].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
|
||||
SIU.PCR[15].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */
|
||||
SIU.PCR[35].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[1] */
|
||||
SIU.PCR[28].R = PAL_MODE_OUTPUT_ALTERNATE(3); /* CS[1] */
|
||||
|
||||
/* Testing sending and receiving at the same time.*/
|
||||
spiExchange(&SPID1, 4, txbuf, rxbuf);
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC560Pxx_MCUCONF
|
||||
|
@ -148,7 +150,16 @@
|
|||
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING 0
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* Serial driver system settings.
|
||||
*/
|
||||
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
|
||||
#define SPC5_SERIAL_USE_LINFLEX1 TRUE
|
||||
|
@ -206,3 +217,82 @@
|
|||
#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define SPC5_SPI_USE_DSPI0 FALSE
|
||||
#define SPC5_SPI_USE_DSPI1 FALSE
|
||||
#define SPC5_SPI_USE_DSPI2 FALSE
|
||||
#define SPC5_SPI_USE_DSPI3 FALSE
|
||||
#define SPC5_SPI_USE_DSPI4 FALSE
|
||||
#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI0_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI4_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||||
#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC560Pxx_MCUCONF
|
||||
|
@ -148,7 +150,16 @@
|
|||
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING 0
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* Serial driver system settings.
|
||||
*/
|
||||
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
|
||||
#define SPC5_SERIAL_USE_LINFLEX1 TRUE
|
||||
|
@ -166,7 +177,7 @@
|
|||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define SPC5_PWM_USE_SMOD0 TRUE
|
||||
#define SPC5_PWM_USE_SMOD0 FALSE
|
||||
#define SPC5_PWM_USE_SMOD1 FALSE
|
||||
#define SPC5_PWM_USE_SMOD2 FALSE
|
||||
#define SPC5_PWM_USE_SMOD3 FALSE
|
||||
|
@ -182,7 +193,7 @@
|
|||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define SPC5_ICU_USE_SMOD0 TRUE
|
||||
#define SPC5_ICU_USE_SMOD0 FALSE
|
||||
#define SPC5_ICU_USE_SMOD1 FALSE
|
||||
#define SPC5_ICU_USE_SMOD2 FALSE
|
||||
#define SPC5_ICU_USE_SMOD3 FALSE
|
||||
|
@ -254,11 +265,6 @@
|
|||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI0_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI4_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
|
|
|
@ -58,10 +58,6 @@
|
|||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP1_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP2_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP3_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
|
|
|
@ -58,10 +58,6 @@
|
|||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP1_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP2_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP3_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC564Axx_MCUCONF
|
||||
|
@ -44,6 +46,25 @@
|
|||
BIUCR_PFLIM_ON_MISS | \
|
||||
BIUCR_BFEN)
|
||||
|
||||
/*
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
|
||||
EDMA_CR_GRP2PRI(2) | \
|
||||
EDMA_CR_GRP1PRI(1) | \
|
||||
EDMA_CR_GRP0PRI(0) | \
|
||||
EDMA_CR_ERGA)
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP1_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP2_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_GROUP3_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* ADC driver settings.
|
||||
*/
|
||||
|
@ -53,12 +74,6 @@
|
|||
#define SPC5_ADC_USE_ADC1_Q3 FALSE
|
||||
#define SPC5_ADC_USE_ADC1_Q4 FALSE
|
||||
#define SPC5_ADC_USE_ADC1_Q5 FALSE
|
||||
#define SPC5_ADC_FIFO0_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO1_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO2_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO3_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO4_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO5_DMA_PRIO 12
|
||||
#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
|
||||
#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
|
||||
#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
|
||||
|
@ -115,9 +130,6 @@
|
|||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI1_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC56ELxx_MCUCONF
|
||||
|
@ -41,7 +43,7 @@
|
|||
#define SPC5_FMPLL1_IDF_VALUE 5
|
||||
#define SPC5_FMPLL1_NDIV_VALUE 60
|
||||
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
|
||||
#define SPC5_SYSCLK_DIVIDER_VALUE 1
|
||||
#define SPC5_SYSCLK_DIVIDER_VALUE 2
|
||||
#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
|
||||
#define SPC5_MCONTROL_DIVIDER_VALUE 15
|
||||
#define SPC5_SWG_DIVIDER_VALUE 2
|
||||
|
@ -134,6 +136,15 @@
|
|||
SPC5_ME_LP_PC_STOP0)
|
||||
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING 0
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
|
@ -217,3 +228,53 @@
|
|||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define SPC5_SPI_USE_DSPI0 FALSE
|
||||
#define SPC5_SPI_USE_DSPI1 FALSE
|
||||
#define SPC5_SPI_USE_DSPI2 FALSE
|
||||
#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
|
||||
SPC5_MCR_PCSIS1 | \
|
||||
SPC5_MCR_PCSIS2 | \
|
||||
SPC5_MCR_PCSIS3 | \
|
||||
SPC5_MCR_PCSIS4 | \
|
||||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI0_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||||
#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
||||
SPC5_ME_PCTL_LP(2))
|
||||
#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
||||
SPC5_ME_PCTL_LP(0))
|
||||
|
|
|
@ -30,7 +30,7 @@ static const SPIConfig hs_spicfg = {
|
|||
};
|
||||
|
||||
/*
|
||||
* Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first).
|
||||
* Low speed SPI configuration.
|
||||
*/
|
||||
static const SPIConfig ls_spicfg = {
|
||||
NULL,
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
*
|
||||
* IRQ priorities:
|
||||
* 1...15 Lowest...Highest.
|
||||
* DMA priorities:
|
||||
* 0...15 Highest...Lowest.
|
||||
*/
|
||||
|
||||
#define SPC56ELxx_MCUCONF
|
||||
|
@ -134,6 +136,15 @@
|
|||
SPC5_ME_LP_PC_STOP0)
|
||||
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* EDMA driver settings.
|
||||
*/
|
||||
#define SPC5_EDMA_CR_SETTING 0
|
||||
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
||||
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
|
@ -153,7 +164,7 @@
|
|||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define SPC5_PWM_USE_SMOD0 TRUE
|
||||
#define SPC5_PWM_USE_SMOD0 FALSE
|
||||
#define SPC5_PWM_USE_SMOD1 FALSE
|
||||
#define SPC5_PWM_USE_SMOD2 FALSE
|
||||
#define SPC5_PWM_USE_SMOD3 FALSE
|
||||
|
@ -182,7 +193,7 @@
|
|||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define SPC5_ICU_USE_SMOD0 TRUE
|
||||
#define SPC5_ICU_USE_SMOD0 FALSE
|
||||
#define SPC5_ICU_USE_SMOD1 FALSE
|
||||
#define SPC5_ICU_USE_SMOD2 FALSE
|
||||
#define SPC5_ICU_USE_SMOD3 FALSE
|
||||
|
@ -248,9 +259,6 @@
|
|||
SPC5_MCR_PCSIS5 | \
|
||||
SPC5_MCR_PCSIS6 | \
|
||||
SPC5_MCR_PCSIS7)
|
||||
#define SPC5_SPI_DSPI0_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_PRIO 10
|
||||
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
||||
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
||||
|
|
Loading…
Reference in New Issue