From 90527794f02f544505e34b89687401aeaa964e35 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 26 Jun 2015 08:15:18 +0000 Subject: [PATCH] Merged LTDC DMA2D code in STM32F4xx HAL. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8052 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/boards/ST_STM32F429I_DISCOVERY/board.h | 44 +++++----- .../ST_STM32F429I_DISCOVERY/cfg/board.chcfg | 20 ++--- os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 54 +++++++++++++ os/hal/ports/STM32/STM32F1xx/stm32_registry.h | 63 +++++++++++++++ os/hal/ports/STM32/STM32F37x/stm32_registry.h | 18 +++++ os/hal/ports/STM32/STM32F3xx/stm32_registry.h | 81 +++++++++++++++++++ os/hal/ports/STM32/STM32F4xx/hal_lld.c | 11 +++ os/hal/ports/STM32/STM32F4xx/hal_lld.h | 53 ++++++++++++ os/hal/ports/STM32/STM32F4xx/stm32_isr.h | 16 ++++ os/hal/ports/STM32/STM32F4xx/stm32_rcc.h | 30 +++++++ os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 28 +++++++ os/hal/ports/STM32/STM32L1xx/stm32_registry.h | 18 +++++ 12 files changed, 404 insertions(+), 32 deletions(-) diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h index d3e981f53..a61509aa5 100644 --- a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h +++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h @@ -63,8 +63,8 @@ #define GPIOA_LCD_G2 6U #define GPIOA_ACP_RST 7U #define GPIOA_I2C3_SCL 8U -#define GPIOA_PIN9 9U -#define GPIOA_PIN10 10U +#define GPIOA_UART_TX 9U +#define GPIOA_UART_RX 10U #define GPIOA_LCD_R4 11U #define GPIOA_LCD_R5 12U #define GPIOA_SWDIO 13U @@ -241,8 +241,8 @@ * PA6 - LCD_G2 (alternate 14). * PA7 - ACP_RST (input pullup). * PA8 - I2C3_SCL (alternate 4). - * PA9 - PIN9 (input pullup). - * PA10 - PIN10 (input pullup). + * PA9 - UART_TX (alternate 7). + * PA10 - UART_RX (alternate 7). * PA11 - LCD_R4 (alternate 14). * PA12 - LCD_R5 (alternate 14). * PA13 - SWDIO (alternate 0). @@ -258,8 +258,8 @@ PIN_MODE_ALTERNATE(GPIOA_LCD_G2) | \ PIN_MODE_INPUT(GPIOA_ACP_RST) | \ PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) | \ - PIN_MODE_INPUT(GPIOA_PIN9) | \ - PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOA_UART_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_UART_RX) | \ PIN_MODE_ALTERNATE(GPIOA_LCD_R4) | \ PIN_MODE_ALTERNATE(GPIOA_LCD_R5) | \ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ @@ -274,8 +274,8 @@ PIN_OTYPE_PUSHPULL(GPIOA_LCD_G2) | \ PIN_OTYPE_PUSHPULL(GPIOA_ACP_RST) | \ PIN_OTYPE_OPENDRAIN(GPIOA_I2C3_SCL) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART_RX) | \ PIN_OTYPE_PUSHPULL(GPIOA_LCD_R4) | \ PIN_OTYPE_PUSHPULL(GPIOA_LCD_R5) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ @@ -290,8 +290,8 @@ PIN_OSPEED_100M(GPIOA_LCD_G2) | \ PIN_OSPEED_2M(GPIOA_ACP_RST) | \ PIN_OSPEED_100M(GPIOA_I2C3_SCL) | \ - PIN_OSPEED_2M(GPIOA_PIN9) | \ - PIN_OSPEED_2M(GPIOA_PIN10) | \ + PIN_OSPEED_2M(GPIOA_UART_TX) | \ + PIN_OSPEED_2M(GPIOA_UART_RX) | \ PIN_OSPEED_100M(GPIOA_LCD_R4) | \ PIN_OSPEED_100M(GPIOA_LCD_R5) | \ PIN_OSPEED_100M(GPIOA_SWDIO) | \ @@ -306,8 +306,8 @@ PIN_PUPDR_FLOATING(GPIOA_LCD_G2) | \ PIN_PUPDR_PULLUP(GPIOA_ACP_RST) | \ PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOA_UART_TX) | \ + PIN_PUPDR_PULLUP(GPIOA_UART_RX) | \ PIN_PUPDR_FLOATING(GPIOA_LCD_R4) | \ PIN_PUPDR_FLOATING(GPIOA_LCD_R5) | \ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ @@ -322,8 +322,8 @@ PIN_ODR_HIGH(GPIOA_LCD_G2) | \ PIN_ODR_HIGH(GPIOA_ACP_RST) | \ PIN_ODR_HIGH(GPIOA_I2C3_SCL) | \ - PIN_ODR_HIGH(GPIOA_PIN9) | \ - PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_UART_TX) | \ + PIN_ODR_HIGH(GPIOA_UART_RX) | \ PIN_ODR_HIGH(GPIOA_LCD_R4) | \ PIN_ODR_HIGH(GPIOA_LCD_R5) | \ PIN_ODR_HIGH(GPIOA_SWDIO) | \ @@ -338,8 +338,8 @@ PIN_AFIO_AF(GPIOA_LCD_G2, 14) | \ PIN_AFIO_AF(GPIOA_ACP_RST, 0)) #define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4) | \ - PIN_AFIO_AF(GPIOA_PIN9, 0) | \ - PIN_AFIO_AF(GPIOA_PIN10, 0) | \ + PIN_AFIO_AF(GPIOA_UART_TX, 7) | \ + PIN_AFIO_AF(GPIOA_UART_RX, 7) | \ PIN_AFIO_AF(GPIOA_LCD_R4, 14) | \ PIN_AFIO_AF(GPIOA_LCD_R5, 14) | \ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ @@ -824,10 +824,10 @@ * PF4 - FMC_A4 (alternate 12). * PF5 - FMC_A5 (alternate 12). * PF6 - PIN6 (input pullup). - * PF7 - LCD_DCX (output pushpull maximum). + * PF7 - LCD_DCX (alternate 5). * PF8 - SPI5_MISO (alternate 5). * PF9 - SPI5_MOSI (alternate 5). - * PF10 - LCD_DE (output pushpull maximum). + * PF10 - LCD_DE (alternate 14). * PF11 - FMC_SDNRAS (alternate 12). * PF12 - FMC_A6 (alternate 12). * PF13 - FMC_A7 (alternate 12). @@ -841,10 +841,10 @@ PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_OUTPUT(GPIOF_LCD_DCX) | \ + PIN_MODE_ALTERNATE(GPIOF_LCD_DCX) | \ PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \ PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \ - PIN_MODE_OUTPUT(GPIOF_LCD_DE) | \ + PIN_MODE_ALTERNATE(GPIOF_LCD_DE) | \ PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ @@ -921,10 +921,10 @@ PIN_AFIO_AF(GPIOF_FMC_A4, 12) | \ PIN_AFIO_AF(GPIOF_FMC_A5, 12) | \ PIN_AFIO_AF(GPIOF_PIN6, 0) | \ - PIN_AFIO_AF(GPIOF_LCD_DCX, 0)) + PIN_AFIO_AF(GPIOF_LCD_DCX, 5)) #define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5) | \ PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5) | \ - PIN_AFIO_AF(GPIOF_LCD_DE, 0) | \ + PIN_AFIO_AF(GPIOF_LCD_DE, 14) | \ PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12) | \ PIN_AFIO_AF(GPIOF_FMC_A6, 12) | \ PIN_AFIO_AF(GPIOF_FMC_A7, 12) | \ diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg index 9e668b10e..d4357d3e3 100644 --- a/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg +++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg @@ -93,21 +93,21 @@ Mode="Alternate" Alternate="4" /> + Mode="Alternate" + Alternate="7" /> + Mode="Alternate" + Alternate="7" /> + Mode="Alternate" + Alternate="5" /> + Mode="Alternate" + Alternate="14" /> PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ; + RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST; + RCC->CR |= RCC_CR_PLLSAION; + + /* Waiting for PLL lock.*/ + while (!(RCC->CR & RCC_CR_PLLSAIRDY)) + ; +#endif + /* Other clock-related settings (dividers, MCO etc).*/ RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index c466a8274..ab5a327de 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -362,6 +362,13 @@ #define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ #define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ +#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */ +#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */ +#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */ +#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */ +#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */ +#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */ + #define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ #define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ #define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ @@ -1278,6 +1285,52 @@ #error "invalid STM32_PLLI2SR_VALUE value specified" #endif +/* + * PLLSAI enable check. + */ +#if !defined(STM32_SAISRC) +#define STM32_SAISRC STM32_SAISRC_NOCLOCK +#endif + +/** + * @brief PLL activation flag. + */ +#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__) +#define STM32_ACTIVATE_PLLSAI TRUE +#else +#define STM32_ACTIVATE_PLLSAI FALSE +#endif + +/** + * @brief STM32_PLLSAIN field. + */ +#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6) +#else +#error "invalid STM32_PLLSAIN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLSAIQ field. + */ +#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24) +#else +#error "invalid STM32_PLLSAIR_VALUE value specified" +#endif + +/** + * @brief STM32_PLLSAIR field. + */ +#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28) +#else +#error "invalid STM32_PLLSAIR_VALUE value specified" +#endif + /** * @brief PLL VCO frequency. */ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h index 1c9a90a0a..548fc62c7 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h @@ -158,6 +158,22 @@ #define STM32_FSMC_NUMBER 48 +/* + * LTDC + */ +#define STM32_LTDC_EV_HANDLER Vector1A0 +#define STM32_LTDC_ER_HANDLER Vector1A4 + +#define STM32_LTDC_EV_NUMBER 88 +#define STM32_LTDC_ER_NUMBER 89 + +/* + * DMA2D + */ +#define STM32_DMA2D_HANDLER Vector1A8 + +#define STM32_DMA2D_NUMBER 90 + /** @} */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h index 393fa5994..b86c85d58 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h @@ -1467,6 +1467,36 @@ */ #define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST) +/** + * @name DMA2D peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA2D peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp) + +/** + * @brief Disables the DMA2D peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp) + +/** + * @brief Resets the DMA2D peripheral. + * + * @api + */ +#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST) +/** @} */ + /** * @name FSMC peripherals specific RCC operations * @{ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index b875fe02a..c3fa55879 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -322,6 +322,12 @@ #define STM32_HAS_OTG1 TRUE #define STM32_HAS_OTG2 TRUE +/* LTDC attributes.*/ +#define STM32_HAS_LTDC TRUE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D TRUE + /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE #define STM32_FSMC_IS_FMC TRUE @@ -334,6 +340,7 @@ STM32_DMA_STREAM_ID_MSK(2, 6) |\ STM32_DMA_STREAM_ID_MSK(2, 7)) #define STM32_FSMC_DMA_CHN 0x03010201 + #endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */ /*===========================================================================*/ @@ -591,6 +598,12 @@ #define STM32_HAS_OTG1 TRUE #define STM32_HAS_OTG2 TRUE +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE #define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ @@ -602,6 +615,7 @@ STM32_DMA_STREAM_ID_MSK(2, 6) |\ STM32_DMA_STREAM_ID_MSK(2, 7)) #define STM32_FSMC_DMA_CHN 0x03010201 + #endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */ /*===========================================================================*/ @@ -815,8 +829,15 @@ #define STM32_HAS_OTG1 TRUE #define STM32_HAS_OTG2 FALSE +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE + #endif /* defined(STM32F401xx) */ /*===========================================================================*/ @@ -1029,8 +1050,15 @@ #define STM32_HAS_OTG1 TRUE #define STM32_HAS_OTG2 FALSE +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE + #endif /** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h index 4c5067db5..129f4c871 100644 --- a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h @@ -190,6 +190,15 @@ #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + #else /* STM32L1XX_HD */ /* ADC attributes.*/ @@ -355,6 +364,15 @@ #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + #endif /* STM32L1XX_HD */ /** @} */