diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/Makefile b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile index 00405071a..792a57e5f 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/Makefile +++ b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.icf b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.icf index 138f1a1a3..f33d49367 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.icf +++ b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.icf @@ -13,15 +13,15 @@ define symbol __ICFEDIT_size_cstack__ = 0x400; define symbol __ICFEDIT_size_heap__ = 0x400; /**** End of ICF editor section. ###ICF###*/ -/* Size of the Process Stack.*/ -define symbol __ICFEDIT_size_pstack__ = 0x400; +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PSTACK with alignment = 8, size = __ICFEDIT_size_pstack__ { }; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block SYSHEAP with alignment = 8, size = 0 { }; @@ -32,6 +32,6 @@ keep { section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; place in ROM_region { readonly }; -place in RAM_region { block PSTACK, block CSTACK, readwrite, block HEAP, block SYSHEAP}; +place in RAM_region { block IRQSTACK, block CSTACK, readwrite, block HEAP, block SYSHEAP}; -define exported symbol __heap_end__ = end(RAM_region) + 1; \ No newline at end of file +define exported symbol __heap_end__ = end(RAM_region) + 1; diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvopt b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvopt new file mode 100644 index 000000000..2ee08979e --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvopt @@ -0,0 +1,2031 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj new file mode 100644 index 000000000..6324a3f09 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj @@ -0,0 +1,1055 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F103RB + STMicroelectronics + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code") + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + 4231 + stm32f10x_lib.h + + + + + + + + + + + 0 + + + + ST\STM32F10x\ + ST\STM32F10x\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x20002000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\boards\OLIMEX_STM32_P103;..\..\..\os\ports\RVCT\ARMCMx\STM32 + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\ST_STM32VL_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\boards\ST_STM32VL_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\STM32\vectors.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + nvic.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + + + platform + + + adc_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\adc_lld.c + + + can_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\can_lld.c + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\hal_lld.c + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pal_lld.c + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\serial_lld.c + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\spi_lld.c + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32\stm32_dma.c + + + uart_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\uart_lld.c + + + adc_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\adc_lld.h + + + can_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\can_lld.h + + + core_cm3.h + 5 + ..\..\..\os\hal\platforms\STM32\core_cm3.h + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\hal_lld.h + + + hal_lld_f103.h + 5 + ..\..\..\os\hal\platforms\STM32\hal_lld_f103.h + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pal_lld.h + + + pwm_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\spi_lld.h + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32\stm32_dma.h + + + stm32f10x.h + 5 + ..\..\..\os\hal\platforms\STM32\stm32f10x.h + + + uart_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\uart_lld.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + + diff --git a/docs/reports/STM32F100-24-IAR.txt b/docs/reports/STM32F100-24-IAR.txt new file mode 100644 index 000000000..5230cd9fe --- /dev/null +++ b/docs/reports/STM32F100-24-IAR.txt @@ -0,0 +1,162 @@ +*************************************************************************** +Options: -Ohs +Settings: SYSCLK=24, ACR=0x10 (no wait states) +Compiler: IAR C/C++ Compiler for ARM 6.10.1.32143 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.1.7unstable +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Platform: STM32 Value Line Medium Density +*** Test Board: ST STM32VL-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 97050 msgs/S, 194100 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 84666 msgs/S, 169332 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 84666 msgs/S, 169332 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 336864 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 60909 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 88760 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 28086 reschedules/S, 168516 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 183660 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 214132 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 310062 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 463584 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 271312 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 360 bytes +--- Thread: 68 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F100-24-RVCT.txt b/docs/reports/STM32F100-24-RVCT.txt new file mode 100644 index 000000000..29fcd3156 --- /dev/null +++ b/docs/reports/STM32F100-24-RVCT.txt @@ -0,0 +1,162 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=24, ACR=0x10 (no wait states) +Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.1.7unstable +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Platform: STM32 Value Line Medium Density +*** Test Board: ST STM32VL-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 99090 msgs/S, 198180 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 86522 msgs/S, 173044 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 86522 msgs/S, 173044 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 343016 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 65072 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 91152 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 29264 reschedules/S, 175584 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 202360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 228520 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 294828 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 454856 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 277668 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 360 bytes +--- Thread: 68 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F100-24.txt b/docs/reports/STM32F100-24.txt index 5c87b1e52..17c4954c3 100644 --- a/docs/reports/STM32F100-24.txt +++ b/docs/reports/STM32F100-24.txt @@ -1,5 +1,5 @@ *************************************************************************** -Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu Settings: SYSCLK=24, ACR=0x10 (no wait states) *************************************************************************** diff --git a/docs/reports/STM32F103-72-RVCT.txt b/docs/reports/STM32F103-72-RVCT.txt index 7695e1d17..0a1ab838c 100644 --- a/docs/reports/STM32F103-72-RVCT.txt +++ b/docs/reports/STM32F103-72-RVCT.txt @@ -1,7 +1,7 @@ *************************************************************************** Options: -O3 -Otime --apcs=interwork Settings: SYSCLK=72, ACR=0x12 (2 wait states) -Compiler: IAR C/C++ Compiler for ARM 6.10.1.32143 +Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation]. *************************************************************************** *** ChibiOS/RT test suite diff --git a/readme.txt b/readme.txt index dec1c4da0..c3e4a4747 100644 --- a/readme.txt +++ b/readme.txt @@ -74,8 +74,8 @@ to 2.0.9). - NEW: New ARM Cortex-Mx port for RVCT compiler (probably will not be included in 2.2.0, requires more testing). -- NEW: Integrated the STM32 GCC, IAR and RVCT demos in a single demo with - multiple project files, the code is exactly the same. +- NEW: Integrated the Cortex-M3 GCC, IAR and RVCT demos in a single demo + with multiple project files, the code is exactly the same. - NEW: Added an USB clock configuration in the STM32 HAL driver (LD, MD, HD). - NEW: New semaphore API chSemSetCounterI(). - NEW: New queue APIs chIQGetFullI() and chOQGetFullI().