mirror of https://github.com/rusefi/ChibiOS.git
New STM32 ADCv2 driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8160 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
314eb6c589
commit
9be84e95da
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@ -13,4 +13,4 @@ STM32_ADC1_IRQ_SHARED_WITH_EXTI - TRUE if the IRQ is shared with EXTI.
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STM32_ADC1_HANDLER - IRQ vector name.
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STM32_ADC1_NUMBER - IRQ vector number.
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STM32_ADC1_DMA_MSK - Mask of the compatible DMA channels.
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STM32_ADC1_DMA_CHN - Mask of the challens mapping.
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STM32_ADC1_DMA_CHN - Mask of the channels mapping.
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@ -0,0 +1,427 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/LLD/ADCv2/adc_lld.c
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* @brief STM32 ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define ADC1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
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#define ADC2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
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#define ADC3_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/** @brief ADC2 driver identifier.*/
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#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
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ADCDriver ADCD2;
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#endif
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/** @brief ADC3 driver identifier.*/
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#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
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ADCDriver ADCD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief ADC DMA ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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/* DMA, this could help only if the DMA tries to access an unmapped
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address space or violates alignment rules.*/
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_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
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}
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else {
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/* It is possible that the conversion group has already be reset by the
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ADC error handler, in this case this interrupt is spurious.*/
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if (adcp->grpp != NULL) {
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_adc_isr_full_code(adcp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_adc_isr_half_code(adcp);
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}
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \
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defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_ADC_HANDLER) {
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uint32_t sr;
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OSAL_IRQ_PROLOGUE();
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#if STM32_ADC_USE_ADC1
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sr = ADC1->SR;
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ADC1->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD1.grpp != NULL)
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_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC2
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sr = ADC2->SR;
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ADC2->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD2.grpp != NULL)
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_adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC2 */
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#if STM32_ADC_USE_ADC3
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sr = ADC3->SR;
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ADC3->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD3.grpp != NULL)
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_adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC3 */
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC1;
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ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
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ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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#if STM32_ADC_USE_ADC2
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/* Driver initialization.*/
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adcObjectInit(&ADCD2);
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ADCD2.adc = ADC2;
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ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
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ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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#if STM32_ADC_USE_ADC3
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/* Driver initialization.*/
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adcObjectInit(&ADCD3);
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ADCD3.adc = ADC3;
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ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
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ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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/* The shared vector is initialized on driver initialization and never
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disabled because sharing.*/
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nvicEnableVector(STM32_ADC_NUMBER, STM32_ADC_IRQ_PRIORITY);
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp) {
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/* If in stopped state then enables the ADC and DMA clocks.*/
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if (adcp->state == ADC_STOP) {
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp) {
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bool b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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osalDbgAssert(!b, "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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rccEnableADC1(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC2
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if (&ADCD2 == adcp) {
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bool b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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osalDbgAssert(!b, "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
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rccEnableADC2(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC2 */
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#if STM32_ADC_USE_ADC3
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if (&ADCD3 == adcp) {
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bool b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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osalDbgAssert(!b, "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
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rccEnableADC3(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC3 */
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/* This is a common register but apparently it requires that at least one
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of the ADCs is clocked in order to allow writing, see bug 3575297.*/
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ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) |
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(STM32_ADC_ADCPRE << 16);
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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adcp->adc->CR2 = ADC_CR2_ADON;
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock.*/
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if (adcp->state == ADC_READY) {
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dmaStreamRelease(adcp->dmastp);
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp)
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rccDisableADC1(FALSE);
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#endif
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#if STM32_ADC_USE_ADC2
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if (&ADCD2 == adcp)
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rccDisableADC2(FALSE);
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#endif
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#if STM32_ADC_USE_ADC3
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if (&ADCD3 == adcp)
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rccDisableADC3(FALSE);
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t mode;
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uint32_t cr2;
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const ADCConversionGroup *grpp = adcp->grpp;
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/* DMA setup.*/
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mode = adcp->dmamode;
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if (grpp->circular) {
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mode |= STM32_DMA_CR_CIRC;
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if (adcp->depth > 1) {
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/* If circular buffer depth > 1, then the half transfer interrupt
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is enabled in order to allow streaming processing.*/
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mode |= STM32_DMA_CR_HTIE;
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}
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}
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dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
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dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
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(uint32_t)adcp->depth);
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dmaStreamSetMode(adcp->dmastp, mode);
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dmaStreamEnable(adcp->dmastp);
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/* ADC setup.*/
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adcp->adc->SR = 0;
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adcp->adc->SMPR1 = grpp->smpr1;
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adcp->adc->SMPR2 = grpp->smpr2;
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adcp->adc->SQR1 = grpp->sqr1;
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adcp->adc->SQR2 = grpp->sqr2;
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adcp->adc->SQR3 = grpp->sqr3;
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/* ADC configuration and start.*/
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adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
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/* Enforcing the mandatory bits in CR2.*/
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cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
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/* The start method is different dependign if HW or SW triggered, the
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start is performed using the method specified in the CR2 configuration.*/
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if ((cr2 & ADC_CR2_SWSTART) != 0) {
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/* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
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adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
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/* Finally enabling ADC_CR2_SWSTART.*/
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adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
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}
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else
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adcp->adc->CR2 = cr2;
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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dmaStreamDisable(adcp->dmastp);
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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adcp->adc->CR2 = ADC_CR2_ADON;
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}
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/**
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* @brief Enables the TSVREFE bit.
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* @details The TSVREFE bit is required in order to sample the internal
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* temperature sensor and internal reference voltage.
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* @note This is an STM32-only functionality.
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*/
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void adcSTM32EnableTSVREFE(void) {
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ADC->CCR |= ADC_CCR_TSVREFE;
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}
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/**
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* @brief Disables the TSVREFE bit.
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* @details The TSVREFE bit is required in order to sample the internal
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* temperature sensor and internal reference voltage.
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* @note This is an STM32-only functionality.
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*/
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void adcSTM32DisableTSVREFE(void) {
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ADC->CCR &= ~ADC_CCR_TSVREFE;
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}
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/**
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* @brief Enables the VBATE bit.
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* @details The VBATE bit is required in order to sample the VBAT channel.
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* @note This is an STM32-only functionality.
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* @note This function is meant to be called after @p adcStart().
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*/
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void adcSTM32EnableVBATE(void) {
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ADC->CCR |= ADC_CCR_VBATE;
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}
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/**
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* @brief Disables the VBATE bit.
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* @details The VBATE bit is required in order to sample the VBAT channel.
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* @note This is an STM32-only functionality.
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* @note This function is meant to be called after @p adcStart().
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*/
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void adcSTM32DisableVBATE(void) {
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ADC->CCR &= ~ADC_CCR_VBATE;
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}
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#endif /* HAL_USE_ADC */
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/** @} */
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@ -0,0 +1,563 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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||||
you may not use this file except in compliance with the License.
|
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You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
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Unless required by applicable law or agreed to in writing, software
|
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distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32/LLD/ADCv2/adc_lld.h
|
||||
* @brief STM32 ADC subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _ADC_LLD_H_
|
||||
#define _ADC_LLD_H_
|
||||
|
||||
#if HAL_USE_ADC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Absolute Maximum Ratings
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Minimum ADC clock frequency.
|
||||
*/
|
||||
#define STM32_ADCCLK_MIN 600000
|
||||
|
||||
/**
|
||||
* @brief Maximum ADC clock frequency.
|
||||
*/
|
||||
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
||||
#define STM32_ADCCLK_MAX 36000000
|
||||
#else
|
||||
#define STM32_ADCCLK_MAX 30000000
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Triggers selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC clock divider settings
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CCR_ADCPRE_DIV2 0
|
||||
#define ADC_CCR_ADCPRE_DIV4 1
|
||||
#define ADC_CCR_ADCPRE_DIV6 2
|
||||
#define ADC_CCR_ADCPRE_DIV8 3
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Available analog channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
|
||||
#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
|
||||
#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
|
||||
#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
|
||||
#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
|
||||
#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
|
||||
#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
|
||||
#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
|
||||
#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
|
||||
#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
|
||||
#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
|
||||
#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
|
||||
#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
|
||||
#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
|
||||
#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
|
||||
#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
|
||||
#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.
|
||||
@note Available onADC1 only. */
|
||||
#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference.
|
||||
@note Available onADC1 only. */
|
||||
#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT.
|
||||
@note Available onADC1 only. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rates
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */
|
||||
#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */
|
||||
#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */
|
||||
#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */
|
||||
#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */
|
||||
#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */
|
||||
#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */
|
||||
#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief ADC common clock divider.
|
||||
* @note This setting is influenced by the VDDA voltage and other
|
||||
* external conditions, please refer to the datasheet for more
|
||||
* info.<br>
|
||||
* See section 5.3.20 "12-bit ADC characteristics".
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC1 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC2 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC2 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC3 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for ADC1 operations.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for ADC2 operations.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for ADC3 operations.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC interrupt priority level setting.
|
||||
* @note This setting is shared among ADC1, ADC2 and ADC3 because
|
||||
* all ADCs share the same vector.
|
||||
*/
|
||||
#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
|
||||
#error "ADC1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
|
||||
#error "ADC2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
|
||||
#error "ADC3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3
|
||||
#error "ADC driver activated but no ADC peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
|
||||
#error "invalid DMA stream associated to ADC1"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
|
||||
#error "invalid DMA stream associated to ADC2"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
|
||||
#error "invalid DMA stream associated to ADC3"
|
||||
#endif
|
||||
|
||||
/* ADC clock related settings and checks.*/
|
||||
#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 2)
|
||||
#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 4)
|
||||
#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 6)
|
||||
#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 8)
|
||||
#else
|
||||
#error "invalid STM32_ADC_ADCPRE value specified"
|
||||
#endif
|
||||
|
||||
#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX)
|
||||
#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief ADC sample data type.
|
||||
*/
|
||||
typedef uint16_t adcsample_t;
|
||||
|
||||
/**
|
||||
* @brief Channels number in a conversion group.
|
||||
*/
|
||||
typedef uint16_t adc_channels_num_t;
|
||||
|
||||
/**
|
||||
* @brief Possible ADC failure causes.
|
||||
* @note Error codes are architecture dependent and should not relied
|
||||
* upon.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
||||
ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
|
||||
} adcerror_t;
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an ADC driver.
|
||||
*/
|
||||
typedef struct ADCDriver ADCDriver;
|
||||
|
||||
/**
|
||||
* @brief ADC notification callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] buffer pointer to the most recent samples data
|
||||
* @param[in] n number of buffer rows available starting from @p buffer
|
||||
*/
|
||||
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
|
||||
|
||||
/**
|
||||
* @brief ADC error callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] err ADC error code
|
||||
*/
|
||||
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
|
||||
|
||||
/**
|
||||
* @brief Conversion group configuration structure.
|
||||
* @details This implementation-dependent structure describes a conversion
|
||||
* operation.
|
||||
* @note The use of this configuration structure requires knowledge of
|
||||
* STM32 ADC cell registers interface, please refer to the STM32
|
||||
* reference manual for details.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Enables the circular buffer mode for the group.
|
||||
*/
|
||||
bool circular;
|
||||
/**
|
||||
* @brief Number of the analog channels belonging to the conversion group.
|
||||
*/
|
||||
adc_channels_num_t num_channels;
|
||||
/**
|
||||
* @brief Callback function associated to the group or @p NULL.
|
||||
*/
|
||||
adccallback_t end_cb;
|
||||
/**
|
||||
* @brief Error callback or @p NULL.
|
||||
*/
|
||||
adcerrorcallback_t error_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief ADC CR1 register initialization data.
|
||||
* @note All the required bits must be defined into this field except
|
||||
* @p ADC_CR1_SCAN that is enforced inside the driver.
|
||||
*/
|
||||
uint32_t cr1;
|
||||
/**
|
||||
* @brief ADC CR2 register initialization data.
|
||||
* @note All the required bits must be defined into this field except
|
||||
* @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
|
||||
* enforced inside the driver.
|
||||
*/
|
||||
uint32_t cr2;
|
||||
/**
|
||||
* @brief ADC SMPR1 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 10...18.
|
||||
*/
|
||||
uint32_t smpr1;
|
||||
/**
|
||||
* @brief ADC SMPR2 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 0...9.
|
||||
*/
|
||||
uint32_t smpr2;
|
||||
/**
|
||||
* @brief ADC SQR1 register initialization data.
|
||||
* @details Conversion group sequence 13...16 + sequence length.
|
||||
*/
|
||||
uint32_t sqr1;
|
||||
/**
|
||||
* @brief ADC SQR2 register initialization data.
|
||||
* @details Conversion group sequence 7...12.
|
||||
*/
|
||||
uint32_t sqr2;
|
||||
/**
|
||||
* @brief ADC SQR3 register initialization data.
|
||||
* @details Conversion group sequence 1...6.
|
||||
*/
|
||||
uint32_t sqr3;
|
||||
} ADCConversionGroup;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
* @note It could be empty on some architectures.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t dummy;
|
||||
} ADCConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an ADC driver.
|
||||
*/
|
||||
struct ADCDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
adcstate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const ADCConfig *config;
|
||||
/**
|
||||
* @brief Current samples buffer pointer or @p NULL.
|
||||
*/
|
||||
adcsample_t *samples;
|
||||
/**
|
||||
* @brief Current samples buffer depth or @p 0.
|
||||
*/
|
||||
size_t depth;
|
||||
/**
|
||||
* @brief Current conversion group pointer or @p NULL.
|
||||
*/
|
||||
const ADCConversionGroup *grpp;
|
||||
#if ADC_USE_WAIT || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Waiting thread.
|
||||
*/
|
||||
thread_reference_t thread;
|
||||
#endif
|
||||
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Mutex protecting the peripheral.
|
||||
*/
|
||||
mutex_t mutex;
|
||||
#endif /* ADC_USE_MUTUAL_EXCLUSION */
|
||||
#if defined(ADC_DRIVER_EXT_FIELDS)
|
||||
ADC_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adc;
|
||||
/**
|
||||
* @brief Pointer to associated DMA channel.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmastp;
|
||||
/**
|
||||
* @brief DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Sequences building helper macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Number of channels in a conversion sequence.
|
||||
*/
|
||||
#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
|
||||
|
||||
#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
|
||||
#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
|
||||
#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
|
||||
#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
|
||||
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
|
||||
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
|
||||
|
||||
#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
|
||||
#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
|
||||
#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
|
||||
#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
|
||||
#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
|
||||
#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
|
||||
|
||||
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
|
||||
#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
|
||||
#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
|
||||
#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rate settings helper macros
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
|
||||
|
||||
#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
|
||||
#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
|
||||
sampling time. */
|
||||
#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
|
||||
sampling time. */
|
||||
#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD2;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD3;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void adc_lld_init(void);
|
||||
void adc_lld_start(ADCDriver *adcp);
|
||||
void adc_lld_stop(ADCDriver *adcp);
|
||||
void adc_lld_start_conversion(ADCDriver *adcp);
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||||
void adcSTM32EnableTSVREFE(void);
|
||||
void adcSTM32DisableTSVREFE(void);
|
||||
void adcSTM32EnableVBATE(void);
|
||||
void adcSTM32DisableVBATE(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
#endif /* _ADC_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
STM32 ADCv2 driver.
|
||||
|
||||
Driver capability:
|
||||
|
||||
- Supports the STM32 "advanced" ADC found on F2, F4 and F4 sub-families.
|
||||
|
||||
The file registry must export:
|
||||
|
||||
STM32_HAS_ADCx - ADCx presence flag (1..3).
|
||||
STM32_ADC_HANDLER - IRQ vector name for ADCs (shared).
|
||||
STM32_ADC_NUMBER - IRQ vector number for ADCs (shared).
|
||||
STM32_ADCx_DMA_MSK - Mask of the compatible DMA channels.
|
||||
STM32_ADCx_DMA_CHN - Mask of the channels mapping.
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
STM32 DMAv2 driver.
|
||||
|
||||
Driver capability:
|
||||
|
||||
- The driver supports the STM32 enhanced DMA controller found on F2, F4 and
|
||||
F7 sub-families.
|
||||
- Support for automatic the channel selection.
|
||||
|
||||
The file registry must export:
|
||||
|
||||
STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other
|
||||
drivers use it to enable checks on DMA
|
||||
channels. Probably will be removed in the
|
||||
future.
|
||||
STM32_HAS_DMAx - Support for DMA unit "x" (1..2).
|
||||
STM32_DMAx_CHn_HANDLER - Vector name for channel "n" (0..7).
|
||||
STM32_DMAn_CHx_NUMBER - Vector number for channel "n" (0..7).
|
||||
|
|
@ -39,6 +39,9 @@
|
|||
#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \
|
||||
defined(__DOXYGEN__)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
#define STM32_ADC_NUMBER 18
|
||||
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
|
|
|
|||
|
|
@ -82,7 +82,8 @@
|
|||
- HAL: New STM32 shared DMAv2 driver supporting channel selection (F2, F4, F7).
|
||||
- HAL: New STM32 shared DMAv1 driver supporting channel selection and fixing
|
||||
the behavior with shared IRQs (F0, L0).
|
||||
- HAL: New STM32 ADCv1 driver supporting small STM32 devices.
|
||||
- HAL: New STM32 ADCv2 driver supporting large STM32 devices (F2, F4, F7).
|
||||
- HAL: New STM32 ADCv1 driver supporting small STM32 devices (F0, L0).
|
||||
- HAL: Introduced support for TIM21 and TIM22 in STM32 ST driver.
|
||||
- HAL: Updated STM32F0xx headers to STM32CubeF0 version 1.3.0. Added support
|
||||
for STM32F030xC, STM32F070x6, STM32F070xB devices.
|
||||
|
|
|
|||
Loading…
Reference in New Issue