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Fixed TIMPRE. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12029 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-05-12 15:44:39 +00:00
parent 11522ff1c5
commit a4fa6c2041
2 changed files with 22 additions and 45 deletions
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65
os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
View File

@ -2062,50 +2062,8 @@
#define STM32_PLL48CLK 0
#endif /* STM32_CLOCK48_REQUIRED */
#if defined(STM32F446xx)
#if STM32_TIMPRE == STM32_TIMPRE_HCLK
/**
* @brief Clock of timers connected to APB1
* (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
(STM32_PPRE1 == STM32_PPRE1_DIV2) || \
(STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) || \
#if !STM32_HAS_RCC_DCKCFGR || (STM32_TIMPRE == STM32_TIMPRE_PCLK) || \
defined(__DOXYGEN__)
#define STM32_TIMCLK1 STM32_HCLK
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
#endif
#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 STM32_HCLK
#else /* !(STM32_TIMPRE_HCLK == STM32_TIMPRE_HCLK) */
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#endif
#endif /* STM32_TIMPRE == STM32_TIMPRE_HCLK */
#if (STM32_TIMPRE == STM32_TIMPRE_HCLK) || defined(STM32F446xx)
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
(STM32_PPRE1 == STM32_PPRE1_DIV2) || \
(STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) || \
defined(__DOXYGEN__)
/**
* @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
*/
#define STM32_TIMCLK2 STM32_HCLK
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
#endif
#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 STM32_HCLK
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#endif
#endif /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
#else /* !defined(STM32F446xx) */
/**
* @brief Clock of timers connected to APB1
* (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
@ -2124,7 +2082,26 @@
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#endif
#endif /* !defined(STM32F446xx) */
#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
(STM32_PPRE1 == STM32_PPRE1_DIV2) || \
(STM32_PPRE1 == STM32_PPRE1_DIV4) || \
defined(__DOXYGEN__)
#define STM32_TIMCLK1 STM32_HCLK
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
#endif
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
(STM32_PPRE2 == STM32_PPRE2_DIV2) || \
(STM32_PPRE2 == STM32_PPRE2_DIV4) || \
defined(__DOXYGEN__)
#define STM32_TIMCLK2 STM32_HCLK
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
#endif
#endif /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
/**
* @brief Flash settings.

2
os/hal/ports/STM32/STM32F4xx/stm32_registry.h
View File

@ -2868,7 +2868,7 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S FALSE
#define STM32_HAS_RCC_DCKCFGR FALSE
#define STM32_HAS_RCC_DCKCFGR TRUE
#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC FALSE